[sim] integrated SoftFloat-3 with ISA sim; removed SoftFloat-2b

diff --git a/configure b/configure
index 5e9e2a394b1151e9508d81f319b950a3790ba711..30b9fc3e7439ba80c694a374c9dadc10a1133c61 100755 (executable)
--- a/configure
+++ b/configure
@@ -4169,6 +4169,51 @@ $as_echo "#define SOFTFLOAT_ENABLED /**/" >>confdefs.h
 
 
 
+    # Determine if this is a required or an optional subproject
+
+
+
+    # Determine if there is a group with the same name
+
+
+
+    # Create variations of the subproject name suitable for use as a CPP
+    # enabled define, a shell enabled variable, and a shell function
+
+
+
+
+
+
+
+
+
+
+
+    # Add subproject to our running list
+
+    subprojects="$subprojects softfloat_riscv"
+
+    # Process the subproject appropriately. If enabled add it to the
+    # $enabled_subprojects running shell variable, set a
+    # SUBPROJECT_ENABLED C define, and include the appropriate
+    # 'subproject.ac'.
+
+
+      { $as_echo "$as_me:${as_lineno-$LINENO}: configuring default subproject : softfloat_riscv" >&5
+$as_echo "$as_me: configuring default subproject : softfloat_riscv" >&6;}
+      ac_config_files="$ac_config_files softfloat_riscv.mk:softfloat_riscv/softfloat_riscv.mk.in"
+
+      enable_softfloat_riscv_sproj="yes"
+      subprojects_enabled="$subprojects_enabled softfloat_riscv"
+
+$as_echo "#define SOFTFLOAT_RISCV_ENABLED /**/" >>confdefs.h
+
+
+
+
+
+
   # Output make variables
 
 
@@ -4876,6 +4921,7 @@ do
   case $ac_config_target in
     "riscv.mk") CONFIG_FILES="$CONFIG_FILES riscv.mk:riscv/riscv.mk.in" ;;
     "softfloat.mk") CONFIG_FILES="$CONFIG_FILES softfloat.mk:softfloat/softfloat.mk.in" ;;
+    "softfloat_riscv.mk") CONFIG_FILES="$CONFIG_FILES softfloat_riscv.mk:softfloat_riscv/softfloat_riscv.mk.in" ;;
     "config.h") CONFIG_HEADERS="$CONFIG_HEADERS config.h" ;;
     "Makefile") CONFIG_FILES="$CONFIG_FILES Makefile" ;;
 

diff --git a/configure.ac b/configure.ac
index 967e7c44f97fa7bb16ffa8e8583b661f5d5f5ca6..60abb71e59ee0b879f3620a6578b01c944042d76 100644 (file)
--- a/configure.ac
+++ b/configure.ac
@@ -81,7 +81,7 @@ AC_SUBST([CXXFLAGS],["-Wall -O2"])
 # The '*' suffix indicates an optional subproject. The '**' suffix
 # indicates an optional subproject which is also the name of a group.
 
-MCPPBS_SUBPROJECTS([ riscv, softfloat ])
+MCPPBS_SUBPROJECTS([ riscv, softfloat, softfloat_riscv ])
 
 #-------------------------------------------------------------------------
 # MCPPBS subproject groups

diff --git a/riscv/decode.h b/riscv/decode.h
index 424ad7fdfe85fbe6ec6f9c063e0f74238f7634ae..1b631ae0526017182ca781a901af258fd7a0d8b1 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -38,20 +38,21 @@ const int BIGIMM_BITS = 20;
 #define SR_IM    0x000000000000FF00ULL
 #define SR_ZERO  ~(SR_ET | SR_PS | SR_S | SR_EF | SR_UX | SR_KX | SR_IM)
 
-#define FP_RD_NE 0
-#define FP_RD_0  1
-#define FP_RD_UP 2
-#define FP_RD_DN 3
+#define FP_RD_NE  0
+#define FP_RD_0   1
+#define FP_RD_DN  2
+#define FP_RD_UP  3
+#define FP_RD_NMM 4
 #define FSR_RD_SHIFT 10
-#define FSR_RD   (0x3 << FSR_RD_SHIFT)
+#define FSR_RD   (0x7 << FSR_RD_SHIFT)
 
-#define FPEXC_NV 0x10
-#define FPEXC_OF 0x08
-#define FPEXC_UF 0x04
-#define FPEXC_DZ 0x02
 #define FPEXC_NX 0x01
+#define FPEXC_UF 0x02
+#define FPEXC_OF 0x04
+#define FPEXC_DZ 0x02
+#define FPEXC_NV 0x10
 
-#define FSR_AEXC_SHIFT 5
+#define FSR_AEXC_SHIFT 0
 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
@@ -59,15 +60,7 @@ const int BIGIMM_BITS = 20;
 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
 
-#define FSR_CEXC_SHIFT 0
-#define FSR_NVC  (FPEXC_NV << FSR_AEXC_SHIFT)
-#define FSR_OFC  (FPEXC_OF << FSR_AEXC_SHIFT)
-#define FSR_UFC  (FPEXC_UF << FSR_AEXC_SHIFT)
-#define FSR_DZC  (FPEXC_DZ << FSR_AEXC_SHIFT)
-#define FSR_NXC  (FPEXC_NX << FSR_AEXC_SHIFT)
-#define FSR_CEXC (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
-
-#define FSR_ZERO ~(FSR_RD | FSR_AEXC | FSR_CEXC)
+#define FSR_ZERO ~(FSR_RD | FSR_AEXC)
 
 // note: bit fields are in little-endian order
 struct itype_t
@@ -143,10 +136,9 @@ union insn_t
 #define require64 if(gprlen != 64) throw trap_illegal_instruction
 #define require_fp if(!(sr & SR_EF)) throw trap_fp_disabled
 #define cmp_trunc(reg) (reg_t(reg) << (64-gprlen))
-#define set_fp_exceptions ({ set_fsr((fsr & ~FSR_CEXC) | \
-                                (float_exception_flags << FSR_AEXC_SHIFT) | \
-                                (float_exception_flags << FSR_CEXC_SHIFT)); \
-                             float_exception_flags = 0; })
+#define set_fp_exceptions ({ set_fsr(fsr | \
+                                (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
+                             softfloat_exceptionFlags = 0; })
 
 static inline sreg_t sext32(int32_t arg)
 {

diff --git a/riscv/insns/add_d.h b/riscv/insns/add_d.h
index bd0f55a9e12fedd05188bfa430a69b8e8a4304da..964aa20885310f341aaf228611a5cbfe68d6fe1f 100644 (file)
--- a/riscv/insns/add_d.h
+++ b/riscv/insns/add_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = float64_add(FRA, FRB);
+FRC = f64_add(FRA, FRB);
 set_fp_exceptions;

diff --git a/riscv/insns/add_s.h b/riscv/insns/add_s.h
index b4f98f63355a7ffbfeec85ff9403bd00799447de..d4d0cd6037f37e70ce910c7a584df1198a88b562 100644 (file)
--- a/riscv/insns/add_s.h
+++ b/riscv/insns/add_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = float32_add(FRA, FRB);
+FRC = f32_add(FRA, FRB);
 set_fp_exceptions;

diff --git a/riscv/insns/c_eq_d.h b/riscv/insns/c_eq_d.h
index 4387ea3a84c73f1732d1e989d6ea0492621aa59e..cc7b77a92c042a8d08422d813c55bdb6029f34f6 100644 (file)
--- a/riscv/insns/c_eq_d.h
+++ b/riscv/insns/c_eq_d.h
@@ -1,3 +1,3 @@
 require_fp;
-RC = float64_eq(FRA, FRB);
+RC = f64_eq(FRA, FRB);
 set_fp_exceptions;

diff --git a/riscv/insns/c_eq_s.h b/riscv/insns/c_eq_s.h
index 062fb745d3ff2604c6d23adc3fc0222e7b28e89f..5500c4cdadc09d4b0b1c0f580b8563b4636140b1 100644 (file)
--- a/riscv/insns/c_eq_s.h
+++ b/riscv/insns/c_eq_s.h
@@ -1,3 +1,3 @@
 require_fp;
-RC = float32_eq(FRA, FRB);
+RC = f32_eq(FRA, FRB);
 set_fp_exceptions;

diff --git a/riscv/insns/c_le_d.h b/riscv/insns/c_le_d.h
index 24ea65782e27b6dcb248d0396ce1507ada8fa919..2fe6f3283907fb1f60d16f9baa9f2b65afd89d99 100644 (file)
--- a/riscv/insns/c_le_d.h
+++ b/riscv/insns/c_le_d.h
@@ -1,3 +1,3 @@
 require_fp;
-RC = float64_le(FRA, FRB);
+RC = f64_le(FRA, FRB);
 set_fp_exceptions;

diff --git a/riscv/insns/c_le_s.h b/riscv/insns/c_le_s.h
index 107622f87bd38cb71ac033709ff1cece302f9ffc..e6e26b3d944d904db6ca6fe258df626a323ec941 100644 (file)
--- a/riscv/insns/c_le_s.h
+++ b/riscv/insns/c_le_s.h
@@ -1,3 +1,3 @@
 require_fp;
-RC = float32_le(FRA, FRB);
+RC = f32_le(FRA, FRB);
 set_fp_exceptions;

diff --git a/riscv/insns/c_lt_d.h b/riscv/insns/c_lt_d.h
index 3d42500aa0ab60e55ff89f12413a149dccfa3447..3f3756d674569579c0366d5bd02939f1851c6768 100644 (file)
--- a/riscv/insns/c_lt_d.h
+++ b/riscv/insns/c_lt_d.h
@@ -1,3 +1,3 @@
 require_fp;
-RC = float64_lt(FRA, FRB);
+RC = f64_lt(FRA, FRB);
 set_fp_exceptions;

diff --git a/riscv/insns/c_lt_s.h b/riscv/insns/c_lt_s.h
index 1f7a0e191e6d8541dbcd76fe6993541aa0e59924..aef73340d7d88530b11f3173c674c939af7a4090 100644 (file)
--- a/riscv/insns/c_lt_s.h
+++ b/riscv/insns/c_lt_s.h
@@ -1,3 +1,3 @@
 require_fp;
-RC = float32_lt(FRA, FRB);
+RC = f32_lt(FRA, FRB);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_d_l.h b/riscv/insns/cvt_d_l.h
index 5246f6f7001d89c63c38991ac64fb465a99b6009..808d20cc81a4b09d2a43b045888584c010865603 100644 (file)
--- a/riscv/insns/cvt_d_l.h
+++ b/riscv/insns/cvt_d_l.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = int64_to_float64(FRA);
+FRC = i64_to_f64(FRA);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_d_s.h b/riscv/insns/cvt_d_s.h
index 481a4d1b50e7ad1d57e8dfa6ad088e1bf6d4afa7..69206e1a80456c515164a9a649b67197568a1d21 100644 (file)
--- a/riscv/insns/cvt_d_s.h
+++ b/riscv/insns/cvt_d_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = float32_to_float64(FRA);
+FRC = f32_to_f64(FRA);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_d_w.h b/riscv/insns/cvt_d_w.h
index 67702a20b9409d94c558e3db78a5c0f82d898485..e1c36f22822b1a0bfc3278ecb09c36b65eb8b6c2 100644 (file)
--- a/riscv/insns/cvt_d_w.h
+++ b/riscv/insns/cvt_d_w.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = int32_to_float64(FRA);
+FRC = i32_to_f64(FRA);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_s_d.h b/riscv/insns/cvt_s_d.h
index 528f11ca6e12d1f9e85f0c00080bd01fd879f82e..0ee755e8e6ecb3a7ac559e7d3cafe0fabf14796f 100644 (file)
--- a/riscv/insns/cvt_s_d.h
+++ b/riscv/insns/cvt_s_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = float64_to_float32(FRA);
+FRC = f64_to_f32(FRA);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_s_l.h b/riscv/insns/cvt_s_l.h
index 2d1f93a61f22c13481324b0bbfd4056820700e09..66e45664b950100121de02e45dc731b3d7b9f544 100644 (file)
--- a/riscv/insns/cvt_s_l.h
+++ b/riscv/insns/cvt_s_l.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = int64_to_float32(FRA);
+FRC = i64_to_f32(FRA);
 set_fp_exceptions;

diff --git a/riscv/insns/cvt_s_w.h b/riscv/insns/cvt_s_w.h
index c2d583fcf2fe541e3d309c9bcbb3839218357cbd..5bbe61f172ce06c378e6454336fa1ce385a17037 100644 (file)
--- a/riscv/insns/cvt_s_w.h
+++ b/riscv/insns/cvt_s_w.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = int32_to_float32(FRA);
+FRC = i32_to_f32(FRA);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_d_l.h b/riscv/insns/cvtu_d_l.h
index 5246f6f7001d89c63c38991ac64fb465a99b6009..808d20cc81a4b09d2a43b045888584c010865603 100644 (file)
--- a/riscv/insns/cvtu_d_l.h
+++ b/riscv/insns/cvtu_d_l.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = int64_to_float64(FRA);
+FRC = i64_to_f64(FRA);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_d_w.h b/riscv/insns/cvtu_d_w.h
index 67702a20b9409d94c558e3db78a5c0f82d898485..1a61ad6417fc0b5f6671301362877e800c91b7bb 100644 (file)
--- a/riscv/insns/cvtu_d_w.h
+++ b/riscv/insns/cvtu_d_w.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = int32_to_float64(FRA);
+FRC = ui32_to_f64(FRA);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_s_l.h b/riscv/insns/cvtu_s_l.h
index 2d1f93a61f22c13481324b0bbfd4056820700e09..66e45664b950100121de02e45dc731b3d7b9f544 100644 (file)
--- a/riscv/insns/cvtu_s_l.h
+++ b/riscv/insns/cvtu_s_l.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = int64_to_float32(FRA);
+FRC = i64_to_f32(FRA);
 set_fp_exceptions;

diff --git a/riscv/insns/cvtu_s_w.h b/riscv/insns/cvtu_s_w.h
index c2d583fcf2fe541e3d309c9bcbb3839218357cbd..8eaeca3d8f2df691203132f0c32d48f5da3cb3c0 100644 (file)
--- a/riscv/insns/cvtu_s_w.h
+++ b/riscv/insns/cvtu_s_w.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = int32_to_float32(FRA);
+FRC = ui32_to_f32(FRA);
 set_fp_exceptions;

diff --git a/riscv/insns/div_d.h b/riscv/insns/div_d.h
index 3b4756337f00e7cba76c24bcdc6caa6d7d71d498..884effcbcef48c10bbdda0b17ad10041ef3a9b31 100644 (file)
--- a/riscv/insns/div_d.h
+++ b/riscv/insns/div_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = float64_div(FRA, FRB);
+FRC = f64_div(FRA, FRB);
 set_fp_exceptions;

diff --git a/riscv/insns/div_s.h b/riscv/insns/div_s.h
index cb5c9bdbed74f11988cec08c88566aef38d2a7a1..b2d086910e1d4171ccd405b52465ee8c5583a0af 100644 (file)
--- a/riscv/insns/div_s.h
+++ b/riscv/insns/div_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = float32_div(FRA, FRB);
+FRC = f32_div(FRA, FRB);
 set_fp_exceptions;

diff --git a/riscv/insns/mul_d.h b/riscv/insns/mul_d.h
index b2a0dbf74db784073e114baf573e6b2546aba0fd..d16e6c5e8cd3a305d17acc82a8e760ea7e87c74b 100644 (file)
--- a/riscv/insns/mul_d.h
+++ b/riscv/insns/mul_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = float64_mul(FRA, FRB);
+FRC = f64_mul(FRA, FRB);
 set_fp_exceptions;

diff --git a/riscv/insns/mul_s.h b/riscv/insns/mul_s.h
index e7d4f3f3e9030d59af9853b89f9c67536cf01385..d700d846fa3d23a2533eeedbf1bc55daf82d7077 100644 (file)
--- a/riscv/insns/mul_s.h
+++ b/riscv/insns/mul_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = float32_mul(FRA, FRB);
+FRC = f32_mul(FRA, FRB);
 set_fp_exceptions;

diff --git a/riscv/insns/sqrt_d.h b/riscv/insns/sqrt_d.h
index 3f831f545238c1edb708f0822c827f80548937eb..fdfc19aaa8c7a0ec24addeb17d10aecba15a642c 100644 (file)
--- a/riscv/insns/sqrt_d.h
+++ b/riscv/insns/sqrt_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = float64_sqrt(FRA);
+FRC = f64_sqrt(FRA);
 set_fp_exceptions;

diff --git a/riscv/insns/sqrt_s.h b/riscv/insns/sqrt_s.h
index 51b589200467c0da7173e806769cae58a52efc08..5f2968c39740d3b50347d541f9c72155e96c0a32 100644 (file)
--- a/riscv/insns/sqrt_s.h
+++ b/riscv/insns/sqrt_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = float32_sqrt(FRA);
+FRC = f32_sqrt(FRA);
 set_fp_exceptions;

diff --git a/riscv/insns/sub_d.h b/riscv/insns/sub_d.h
index 55d0e86212a4c196e5edc6f9874ad906d4d1891e..023a1f324f2770080345f0d81bf4fd3a0922efa6 100644 (file)
--- a/riscv/insns/sub_d.h
+++ b/riscv/insns/sub_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = float64_sub(FRA, FRB);
+FRC = f64_sub(FRA, FRB);
 set_fp_exceptions;

diff --git a/riscv/insns/sub_s.h b/riscv/insns/sub_s.h
index 4a359bfc5a428f4a152fec47a1a110b59a22f09e..fd83da031b63a2f38862cbde04de2a598b61fd62 100644 (file)
--- a/riscv/insns/sub_s.h
+++ b/riscv/insns/sub_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = float32_sub(FRA, FRB);
+FRC = f32_sub(FRA, FRB);
 set_fp_exceptions;

diff --git a/riscv/insns/trunc_l_d.h b/riscv/insns/trunc_l_d.h
index ecca8cd2afc3b40b0c80edd1f1cd4f3641ff81dd..0fad400c10cd33dedfbfb4a04aef78490ba40b74 100644 (file)
--- a/riscv/insns/trunc_l_d.h
+++ b/riscv/insns/trunc_l_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = float64_to_int64_round_to_zero(FRA);
+FRC = f64_to_i64_r_minMag(FRA,true);
 set_fp_exceptions;

diff --git a/riscv/insns/trunc_l_s.h b/riscv/insns/trunc_l_s.h
index 9dd0e5188041f60fb4eb8721809195debddca894..5d5a9408e31b70d89c7f613ca63cda865572011d 100644 (file)
--- a/riscv/insns/trunc_l_s.h
+++ b/riscv/insns/trunc_l_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = float32_to_int64_round_to_zero(FRA);
+FRC = f32_to_i64_r_minMag(FRA,true);
 set_fp_exceptions;

diff --git a/riscv/insns/trunc_w_d.h b/riscv/insns/trunc_w_d.h
index 9b7cdb059ff4dc65ab5d36cd0ef5ed45405f60ec..b91640a3ac59c91f72fdcaa5919bf72f38660782 100644 (file)
--- a/riscv/insns/trunc_w_d.h
+++ b/riscv/insns/trunc_w_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = float64_to_int32_round_to_zero(FRA);
+FRC = f64_to_i32_r_minMag(FRA,true);
 set_fp_exceptions;

diff --git a/riscv/insns/trunc_w_s.h b/riscv/insns/trunc_w_s.h
index 147ec8bc54b3a78e74c996786e199562623c4e66..73974d1f28362ddf457913d35ebebde7d2a0077d 100644 (file)
--- a/riscv/insns/trunc_w_s.h
+++ b/riscv/insns/trunc_w_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = float32_to_int32_round_to_zero(FRA);
+FRC = f32_to_i32_r_minMag(FRA,true);
 set_fp_exceptions;

diff --git a/riscv/insns/truncu_l_d.h b/riscv/insns/truncu_l_d.h
index ecca8cd2afc3b40b0c80edd1f1cd4f3641ff81dd..0fad400c10cd33dedfbfb4a04aef78490ba40b74 100644 (file)
--- a/riscv/insns/truncu_l_d.h
+++ b/riscv/insns/truncu_l_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = float64_to_int64_round_to_zero(FRA);
+FRC = f64_to_i64_r_minMag(FRA,true);
 set_fp_exceptions;

diff --git a/riscv/insns/truncu_l_s.h b/riscv/insns/truncu_l_s.h
index 9dd0e5188041f60fb4eb8721809195debddca894..5d5a9408e31b70d89c7f613ca63cda865572011d 100644 (file)
--- a/riscv/insns/truncu_l_s.h
+++ b/riscv/insns/truncu_l_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = float32_to_int64_round_to_zero(FRA);
+FRC = f32_to_i64_r_minMag(FRA,true);
 set_fp_exceptions;

diff --git a/riscv/insns/truncu_w_d.h b/riscv/insns/truncu_w_d.h
index 9b7cdb059ff4dc65ab5d36cd0ef5ed45405f60ec..255fba550a6577d565ed5b7829e47bdc9d63296c 100644 (file)
--- a/riscv/insns/truncu_w_d.h
+++ b/riscv/insns/truncu_w_d.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = float64_to_int32_round_to_zero(FRA);
+FRC = f64_to_ui32_r_minMag(FRA,true);
 set_fp_exceptions;

diff --git a/riscv/insns/truncu_w_s.h b/riscv/insns/truncu_w_s.h
index 147ec8bc54b3a78e74c996786e199562623c4e66..337b9ea1e1de3a210e10aac5652bccee41940765 100644 (file)
--- a/riscv/insns/truncu_w_s.h
+++ b/riscv/insns/truncu_w_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = float32_to_int32_round_to_zero(FRA);
+FRC = f32_to_ui32_r_minMag(FRA,true);
 set_fp_exceptions;

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 3f6427dc292bd22012f766106740ae67a4baf47d..6d55c8033876d848c66c85cfd0db6f511d10caa3 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -1,4 +1,6 @@
-riscv_subproject_deps = softfloat \
+riscv_subproject_deps = \
+       softfloat_riscv \
+       softfloat \
 
 riscv_hdrs = \
     applink.h \

diff --git a/softfloat/8086/OLD-specialize.c b/softfloat/8086/OLD-specialize.c
new file mode 100755 (executable)
index 0000000..ffb306d
--- /dev/null
+++ b/softfloat/8086/OLD-specialize.c
@@ -0,0 +1,40 @@
+\r
+/*============================================================================\r
+\r
+*** FIX.\r
+\r
+This C source fragment is part of the SoftFloat IEC/IEEE Floating-point\r
+Arithmetic Package, Release 2b.\r
+\r
+Written by John R. Hauser.  This work was made possible in part by the\r
+International Computer Science Institute, located at Suite 600, 1947 Center\r
+Street, Berkeley, California 94704.  Funding was partially provided by the\r
+National Science Foundation under grant MIP-9311980.  The original version\r
+of this code was written as part of a project to build a fixed-point vector\r
+processor in collaboration with the University of California at Berkeley,\r
+overseen by Profs. Nelson Morgan and John Wawrzynek.  More information\r
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
+arithmetic/SoftFloat.html'.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has\r
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
+RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
+\r
+Derivative works are acceptable, even for commercial purposes, so long as\r
+(1) the source code for the derivative work includes prominent notice that\r
+the work is derivative, and (2) the source code includes prominent notice with\r
+these four paragraphs for those parts of this code that are retained.\r
+\r
+=============================================================================*/\r
+\r
+/*----------------------------------------------------------------------------\r
+| Underflow tininess-detection mode, statically initialized to default value.\r
+| (The declaration in `softfloat.h' must match the `int8' type here.)\r
+*----------------------------------------------------------------------------*/\r
+bool float_detectTininess = float_tininess_afterRounding;\r
+\r

diff --git a/softfloat/8086/OLD-specialize.h b/softfloat/8086/OLD-specialize.h
new file mode 100755 (executable)
index 0000000..9e4461c
--- /dev/null
+++ b/softfloat/8086/OLD-specialize.h
@@ -0,0 +1,379 @@
+\r
+/*============================================================================\r
+\r
+*** FIX.\r
+\r
+This C source fragment is part of the SoftFloat IEC/IEEE Floating-point\r
+Arithmetic Package, Release 2b.\r
+\r
+Written by John R. Hauser.  This work was made possible in part by the\r
+International Computer Science Institute, located at Suite 600, 1947 Center\r
+Street, Berkeley, California 94704.  Funding was partially provided by the\r
+National Science Foundation under grant MIP-9311980.  The original version\r
+of this code was written as part of a project to build a fixed-point vector\r
+processor in collaboration with the University of California at Berkeley,\r
+overseen by Profs. Nelson Morgan and John Wawrzynek.  More information\r
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
+arithmetic/SoftFloat.html'.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has\r
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
+RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
+\r
+Derivative works are acceptable, even for commercial purposes, so long as\r
+(1) the source code for the derivative work includes prominent notice that\r
+the work is derivative, and (2) the source code includes prominent notice with\r
+these four paragraphs for those parts of this code that are retained.\r
+\r
+=============================================================================*/\r
+\r
+/*----------------------------------------------------------------------------\r
+| Internal canonical NaN format.\r
+*----------------------------------------------------------------------------*/\r
+*** COMMON\r
+typedef struct {\r
+    flag sign;\r
+    uint128_t bits;\r
+} commonNaNT;\r
+\r
+/*----------------------------------------------------------------------------\r
+| The pattern for a default generated single-precision NaN.\r
+*----------------------------------------------------------------------------*/\r
+#define float32Bits_defaultNaN 0xFFC00000\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the single-precision floating-point value `a' is a NaN;\r
+| otherwise, returns 0.\r
+*----------------------------------------------------------------------------*/\r
+*** COMMON\r
+#define softfloat_isNaNFloat32Bits( a ) ( 0xFF000000 < (uint32_t) ( a )<<1 )\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the single-precision floating-point value `a' is a signaling\r
+| NaN; otherwise, returns 0.\r
+*----------------------------------------------------------------------------*/\r
+inline bool softfloat_isSigNaNFloat32Bits( uint32_t a )\r
+    { return ( ( a>>22 & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF ); }\r
+\r
+/*----------------------------------------------------------------------------\r
+*----------------------------------------------------------------------------*/\r
+commonNaNT softfloat_NaNFromFloat32Bits( uint32_t );\r
+uint32_t softfloat_float32BitsFromNaN( commonNaNT );\r
+uint32_t softfloat_propNaNFloat32Bits( uint32_t, uint32_t );\r
+\r
+/*----------------------------------------------------------------------------\r
+| The pattern for a default generated double-precision NaN.\r
+*----------------------------------------------------------------------------*/\r
+#define float64Bits_defaultNaN 0xFFF8000000000000\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the double-precision floating-point value `a' is a NaN;\r
+| otherwise, returns 0.\r
+*----------------------------------------------------------------------------*/\r
+*** COMMON\r
+#define softfloat_isNaNFloat64Bits( a ) ( 0xFFE0000000000000 < (uint64_t) ( a )<<1 )\r
+\r
+\r
+\r
+\r
+\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the double-precision floating-point value `a' is a signaling\r
+| NaN; otherwise, returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float64_is_signaling_nan( float64 a )\r
+{\r
+\r
+    return\r
+           ( ( ( a>>51 ) & 0xFFF ) == 0xFFE )\r
+        && ( a & LIT64( 0x0007FFFFFFFFFFFF ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the double-precision floating-point NaN\r
+| `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid\r
+| exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static commonNaNT float64ToCommonNaN( float64 a )\r
+{\r
+    commonNaNT z;\r
+\r
+    if ( float64_is_signaling_nan( a ) ) float_raise( float_flag_invalid );\r
+    z.sign = a>>63;\r
+    z.low = 0;\r
+    z.high = a<<12;\r
+    return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the canonical NaN `a' to the double-\r
+| precision floating-point format.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float64 commonNaNToFloat64( commonNaNT a )\r
+{\r
+\r
+    return\r
+          ( ( (bits64) a.sign )<<63 )\r
+        | LIT64( 0x7FF8000000000000 )\r
+        | ( a.high>>12 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes two double-precision floating-point values `a' and `b', one of which\r
+| is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a\r
+| signaling NaN, the invalid exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float64 propagateFloat64NaN( float64 a, float64 b )\r
+{\r
+    flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;\r
+\r
+    aIsNaN = float64_is_nan( a );\r
+    aIsSignalingNaN = float64_is_signaling_nan( a );\r
+    bIsNaN = float64_is_nan( b );\r
+    bIsSignalingNaN = float64_is_signaling_nan( b );\r
+    a |= LIT64( 0x0008000000000000 );\r
+    b |= LIT64( 0x0008000000000000 );\r
+    if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );\r
+    if ( aIsSignalingNaN ) {\r
+        if ( bIsSignalingNaN ) goto returnLargerSignificand;\r
+        return bIsNaN ? b : a;\r
+    }\r
+    else if ( aIsNaN ) {\r
+        if ( bIsSignalingNaN | ! bIsNaN ) return a;\r
+ returnLargerSignificand:\r
+        if ( (bits64) ( a<<1 ) < (bits64) ( b<<1 ) ) return b;\r
+        if ( (bits64) ( b<<1 ) < (bits64) ( a<<1 ) ) return a;\r
+        return ( a < b ) ? a : b;\r
+    }\r
+    else {\r
+        return b;\r
+    }\r
+\r
+}\r
+\r
+#ifdef FLOATX80\r
+\r
+/*----------------------------------------------------------------------------\r
+| The pattern for a default generated extended double-precision NaN.  The\r
+| `high' and `low' values hold the most- and least-significant bits,\r
+| respectively.\r
+*----------------------------------------------------------------------------*/\r
+#define floatx80_default_nan_high 0xFFFF\r
+#define floatx80_default_nan_low  LIT64( 0xC000000000000000 )\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the extended double-precision floating-point value `a' is a\r
+| NaN; otherwise, returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag floatx80_is_nan( floatx80 a )\r
+{\r
+\r
+    return ( ( a.high & 0x7FFF ) == 0x7FFF ) && (bits64) ( a.low<<1 );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the extended double-precision floating-point value `a' is a\r
+| signaling NaN; otherwise, returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag floatx80_is_signaling_nan( floatx80 a )\r
+{\r
+    bits64 aLow;\r
+\r
+    aLow = a.low & ~ LIT64( 0x4000000000000000 );\r
+    return\r
+           ( ( a.high & 0x7FFF ) == 0x7FFF )\r
+        && (bits64) ( aLow<<1 )\r
+        && ( a.low == aLow );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the extended double-precision floating-\r
+| point NaN `a' to the canonical NaN format.  If `a' is a signaling NaN, the\r
+| invalid exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static commonNaNT floatx80ToCommonNaN( floatx80 a )\r
+{\r
+    commonNaNT z;\r
+\r
+    if ( floatx80_is_signaling_nan( a ) ) float_raise( float_flag_invalid );\r
+    z.sign = a.high>>15;\r
+    z.low = 0;\r
+    z.high = a.low<<1;\r
+    return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the canonical NaN `a' to the extended\r
+| double-precision floating-point format.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static floatx80 commonNaNToFloatx80( commonNaNT a )\r
+{\r
+    floatx80 z;\r
+\r
+    z.low = LIT64( 0xC000000000000000 ) | ( a.high>>1 );\r
+    z.high = ( ( (bits16) a.sign )<<15 ) | 0x7FFF;\r
+    return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes two extended double-precision floating-point values `a' and `b', one\r
+| of which is a NaN, and returns the appropriate NaN result.  If either `a' or\r
+| `b' is a signaling NaN, the invalid exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static floatx80 propagateFloatx80NaN( floatx80 a, floatx80 b )\r
+{\r
+    flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;\r
+\r
+    aIsNaN = floatx80_is_nan( a );\r
+    aIsSignalingNaN = floatx80_is_signaling_nan( a );\r
+    bIsNaN = floatx80_is_nan( b );\r
+    bIsSignalingNaN = floatx80_is_signaling_nan( b );\r
+    a.low |= LIT64( 0xC000000000000000 );\r
+    b.low |= LIT64( 0xC000000000000000 );\r
+    if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );\r
+    if ( aIsSignalingNaN ) {\r
+        if ( bIsSignalingNaN ) goto returnLargerSignificand;\r
+        return bIsNaN ? b : a;\r
+    }\r
+    else if ( aIsNaN ) {\r
+        if ( bIsSignalingNaN | ! bIsNaN ) return a;\r
+ returnLargerSignificand:\r
+        if ( a.low < b.low ) return b;\r
+        if ( b.low < a.low ) return a;\r
+        return ( a.high < b.high ) ? a : b;\r
+    }\r
+    else {\r
+        return b;\r
+    }\r
+\r
+}\r
+\r
+#endif\r
+\r
+#ifdef FLOAT128\r
+\r
+/*----------------------------------------------------------------------------\r
+| The pattern for a default generated quadruple-precision NaN.  The `high' and\r
+| `low' values hold the most- and least-significant bits, respectively.\r
+*----------------------------------------------------------------------------*/\r
+#define float128_default_nan_high LIT64( 0xFFFF800000000000 )\r
+#define float128_default_nan_low  LIT64( 0x0000000000000000 )\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the quadruple-precision floating-point value `a' is a NaN;\r
+| otherwise, returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float128_is_nan( float128 a )\r
+{\r
+\r
+    return\r
+           ( LIT64( 0xFFFE000000000000 ) <= (bits64) ( a.high<<1 ) )\r
+        && ( a.low || ( a.high & LIT64( 0x0000FFFFFFFFFFFF ) ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the quadruple-precision floating-point value `a' is a\r
+| signaling NaN; otherwise, returns 0.\r
+*----------------------------------------------------------------------------*/\r
+\r
+flag float128_is_signaling_nan( float128 a )\r
+{\r
+\r
+    return\r
+           ( ( ( a.high>>47 ) & 0xFFFF ) == 0xFFFE )\r
+        && ( a.low || ( a.high & LIT64( 0x00007FFFFFFFFFFF ) ) );\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the quadruple-precision floating-point NaN\r
+| `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid\r
+| exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static commonNaNT float128ToCommonNaN( float128 a )\r
+{\r
+    commonNaNT z;\r
+\r
+    if ( float128_is_signaling_nan( a ) ) float_raise( float_flag_invalid );\r
+    z.sign = a.high>>63;\r
+    shortShift128Left( a.high, a.low, 16, &z.high, &z.low );\r
+    return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the canonical NaN `a' to the quadruple-\r
+| precision floating-point format.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float128 commonNaNToFloat128( commonNaNT a )\r
+{\r
+    float128 z;\r
+\r
+    shift128Right( a.high, a.low, 16, &z.high, &z.low );\r
+    z.high |= ( ( (bits64) a.sign )<<63 ) | LIT64( 0x7FFF800000000000 );\r
+    return z;\r
+\r
+}\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes two quadruple-precision floating-point values `a' and `b', one of\r
+| which is a NaN, and returns the appropriate NaN result.  If either `a' or\r
+| `b' is a signaling NaN, the invalid exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+static float128 propagateFloat128NaN( float128 a, float128 b )\r
+{\r
+    flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;\r
+\r
+    aIsNaN = float128_is_nan( a );\r
+    aIsSignalingNaN = float128_is_signaling_nan( a );\r
+    bIsNaN = float128_is_nan( b );\r
+    bIsSignalingNaN = float128_is_signaling_nan( b );\r
+    a.high |= LIT64( 0x0000800000000000 );\r
+    b.high |= LIT64( 0x0000800000000000 );\r
+    if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );\r
+    if ( aIsSignalingNaN ) {\r
+        if ( bIsSignalingNaN ) goto returnLargerSignificand;\r
+        return bIsNaN ? b : a;\r
+    }\r
+    else if ( aIsNaN ) {\r
+        if ( bIsSignalingNaN | ! bIsNaN ) return a;\r
+ returnLargerSignificand:\r
+        if ( lt128( a.high<<1, a.low, b.high<<1, b.low ) ) return b;\r
+        if ( lt128( b.high<<1, b.low, a.high<<1, a.low ) ) return a;\r
+        return ( a.high < b.high ) ? a : b;\r
+    }\r
+    else {\r
+        return b;\r
+    }\r
+\r
+}\r
+\r
+#endif\r
+\r

diff --git a/softfloat/8086/platform.h b/softfloat/8086/platform.h
new file mode 100755 (executable)
index 0000000..9355edf
--- /dev/null
+++ b/softfloat/8086/platform.h
@@ -0,0 +1,38 @@
+
+/*============================================================================
+
+*** FIX.
+
+This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
+Arithmetic Package, Release 2b.
+
+Written by John R. Hauser.  This work was made possible in part by the
+International Computer Science Institute, located at Suite 600, 1947 Center
+Street, Berkeley, California 94704.  Funding was partially provided by the
+National Science Foundation under grant MIP-9311980.  The original version
+of this code was written as part of a project to build a fixed-point vector
+processor in collaboration with the University of California at Berkeley,
+overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/
+arithmetic/SoftFloat.html'.
+
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
+RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
+
+Derivative works are acceptable, even for commercial purposes, so long as
+(1) the source code for the derivative work includes prominent notice that
+the work is derivative, and (2) the source code includes prominent notice with
+these four paragraphs for those parts of this code that are retained.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define LITTLEENDIAN
+

diff --git a/softfloat/8086/s_commonNaNToF32UI.c b/softfloat/8086/s_commonNaNToF32UI.c
new file mode 100755 (executable)
index 0000000..3b96c41
--- /dev/null
+++ b/softfloat/8086/s_commonNaNToF32UI.c
@@ -0,0 +1,17 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "specialize.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the canonical NaN `a' to the single-\r
+| precision floating-point format.\r
+*----------------------------------------------------------------------------*/\r
+\r
+uint_fast32_t softfloat_commonNaNToF32UI( struct commonNaN a )\r
+{\r
+\r
+    return (uint_fast32_t) a.sign<<31 | 0x7FC00000 | a.v64>>41;\r
+\r
+}\r
+\r

diff --git a/softfloat/8086/s_commonNaNToF64UI.c b/softfloat/8086/s_commonNaNToF64UI.c
new file mode 100755 (executable)
index 0000000..474ceee
--- /dev/null
+++ b/softfloat/8086/s_commonNaNToF64UI.c
@@ -0,0 +1,19 @@
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Returns the result of converting the canonical NaN `a' to the double-
+| precision floating-point format.
+*----------------------------------------------------------------------------*/
+
+uint_fast64_t softfloat_commonNaNToF64UI( struct commonNaN a )
+{
+
+    return
+        (uint_fast64_t) a.sign<<63 | UINT64_C( 0x7FF8000000000000 )
+            | a.v64>>12;
+
+}
+

diff --git a/softfloat/8086/s_f32UIToCommonNaN.c b/softfloat/8086/s_f32UIToCommonNaN.c
new file mode 100755 (executable)
index 0000000..067e8da
--- /dev/null
+++ b/softfloat/8086/s_f32UIToCommonNaN.c
@@ -0,0 +1,25 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "specialize.h"\r
+#include "softfloat.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the single-precision floating-point NaN\r
+| `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid\r
+| exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+struct commonNaN softfloat_f32UIToCommonNaN( uint_fast32_t uiA )\r
+{\r
+    struct commonNaN z;\r
+\r
+    if ( softfloat_isSigNaNF32UI( uiA ) ) {\r
+        softfloat_raiseFlags( softfloat_flag_invalid );\r
+    }\r
+    z.sign = uiA>>31;\r
+    z.v64 = (uint_fast64_t) uiA<<41;\r
+    z.v0 = 0;\r
+    return z;\r
+\r
+}\r
+\r

diff --git a/softfloat/8086/s_f64UIToCommonNaN.c b/softfloat/8086/s_f64UIToCommonNaN.c
new file mode 100755 (executable)
index 0000000..f933ded
--- /dev/null
+++ b/softfloat/8086/s_f64UIToCommonNaN.c
@@ -0,0 +1,25 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "specialize.h"\r
+#include "softfloat.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the double-precision floating-point NaN\r
+| `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid\r
+| exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+struct commonNaN softfloat_f64UIToCommonNaN( uint_fast64_t uiA )\r
+{\r
+    struct commonNaN z;\r
+\r
+    if ( softfloat_isSigNaNF64UI( uiA ) ) {\r
+        softfloat_raiseFlags( softfloat_flag_invalid );\r
+    }\r
+    z.sign = uiA>>63;\r
+    z.v64 = uiA<<12;\r
+    z.v0 = 0;\r
+    return z;\r
+\r
+}\r
+\r

diff --git a/softfloat/8086/s_isSigNaNF32UI.c b/softfloat/8086/s_isSigNaNF32UI.c
new file mode 100755 (executable)
index 0000000..0a9c33f
--- /dev/null
+++ b/softfloat/8086/s_isSigNaNF32UI.c
@@ -0,0 +1,13 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+
+bool softfloat_isSigNaNF32UI( uint_fast32_t ui )
+{
+
+    return ( ( ui>>22 & 0x1FF ) == 0x1FE ) && ( ui & 0x003FFFFF );
+
+}
+

diff --git a/softfloat/8086/s_isSigNaNF64UI.c b/softfloat/8086/s_isSigNaNF64UI.c
new file mode 100755 (executable)
index 0000000..d255213
--- /dev/null
+++ b/softfloat/8086/s_isSigNaNF64UI.c
@@ -0,0 +1,15 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+
+bool softfloat_isSigNaNF64UI( uint_fast64_t ui )
+{
+
+    return
+        ( ( ui>>51 & 0xFFF ) == 0xFFE )
+            && ( ui & UINT64_C( 0x0007FFFFFFFFFFFF ) );
+
+}
+

diff --git a/softfloat/8086/s_propagateNaNF32UI.c b/softfloat/8086/s_propagateNaNF32UI.c
new file mode 100755 (executable)
index 0000000..07774e8
--- /dev/null
+++ b/softfloat/8086/s_propagateNaNF32UI.c
@@ -0,0 +1,55 @@
+\r
+/*** UPDATE COMMENTS. ***/\r
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "internals.h"\r
+#include "specialize.h"\r
+#include "softfloat.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes two single-precision floating-point values `a' and `b', one of which\r
+| is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a\r
+| signaling NaN, the invalid exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+uint_fast32_t\r
+ softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB )\r
+{\r
+    bool isNaNA, isSigNaNA, isNaNB, isSigNaNB;\r
+    uint_fast32_t uiMagA, uiMagB;\r
+\r
+    /*------------------------------------------------------------------------\r
+    *------------------------------------------------------------------------*/\r
+    isNaNA = isNaNF32UI( uiA );\r
+    isSigNaNA = softfloat_isSigNaNF32UI( uiA );\r
+    isNaNB = isNaNF32UI( uiB );\r
+    isSigNaNB = softfloat_isSigNaNF32UI( uiB );\r
+    /*------------------------------------------------------------------------\r
+    | Make NaNs non-signaling.\r
+    *------------------------------------------------------------------------*/\r
+    uiA |= 0x00400000;\r
+    uiB |= 0x00400000;\r
+    /*------------------------------------------------------------------------\r
+    *------------------------------------------------------------------------*/\r
+    if ( isSigNaNA | isSigNaNB ) {\r
+        softfloat_raiseFlags( softfloat_flag_invalid );\r
+    }\r
+    if ( isSigNaNA ) {\r
+        if ( isSigNaNB ) goto returnLargerSignificand;\r
+        return isNaNB ? uiB : uiA;\r
+    } else if ( isNaNA ) {\r
+        if ( isSigNaNB || ! isNaNB ) return uiA;\r
+ returnLargerSignificand:\r
+        uiMagA = uiA<<1;\r
+        uiMagB = uiB<<1;\r
+        if ( uiMagA < uiMagB ) return uiB;\r
+        if ( uiMagB < uiMagA ) return uiA;\r
+        return ( uiA < uiB ) ? uiA : uiB;\r
+    } else {\r
+        return uiB;\r
+    }\r
+\r
+}\r
+\r

diff --git a/softfloat/8086/s_propagateNaNF64UI.c b/softfloat/8086/s_propagateNaNF64UI.c
new file mode 100755 (executable)
index 0000000..0ff6446
--- /dev/null
+++ b/softfloat/8086/s_propagateNaNF64UI.c
@@ -0,0 +1,55 @@
+
+/*** UPDATE COMMENTS. ***/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Takes two double-precision floating-point values `a' and `b', one of which
+| is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+
+uint_fast64_t
+ softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB )
+{
+    bool isNaNA, isSigNaNA, isNaNB, isSigNaNB;
+    uint_fast64_t uiMagA, uiMagB;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    isNaNA = isNaNF64UI( uiA );
+    isSigNaNA = softfloat_isSigNaNF64UI( uiA );
+    isNaNB = isNaNF64UI( uiB );
+    isSigNaNB = softfloat_isSigNaNF64UI( uiB );
+    /*------------------------------------------------------------------------
+    | Make NaNs non-signaling.
+    *------------------------------------------------------------------------*/
+    uiA |= UINT64_C( 0x0008000000000000 );
+    uiB |= UINT64_C( 0x0008000000000000 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( isSigNaNA | isSigNaNB ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    if ( isSigNaNA ) {
+        if ( isSigNaNB ) goto returnLargerSignificand;
+        return isNaNB ? uiB : uiA;
+    } else if ( isNaNA ) {
+        if ( isSigNaNB || ! isNaNB ) return uiA;
+ returnLargerSignificand:
+        uiMagA = uiA & UINT64_C( 0x7FFFFFFFFFFFFFFF );
+        uiMagB = uiB & UINT64_C( 0x7FFFFFFFFFFFFFFF );
+        if ( uiMagA < uiMagB ) return uiB;
+        if ( uiMagB < uiMagA ) return uiA;
+        return ( uiA < uiB ) ? uiA : uiB;
+    } else {
+        return uiB;
+    }
+
+}
+

diff --git a/softfloat/8086/softfloat_raiseFlags.c b/softfloat/8086/softfloat_raiseFlags.c
new file mode 100755 (executable)
index 0000000..c0c0dc8
--- /dev/null
+++ b/softfloat/8086/softfloat_raiseFlags.c
@@ -0,0 +1,51 @@
+
+/*============================================================================
+
+*** FIX.
+
+This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
+Arithmetic Package, Release 2b.
+
+Written by John R. Hauser.  This work was made possible in part by the
+International Computer Science Institute, located at Suite 600, 1947 Center
+Street, Berkeley, California 94704.  Funding was partially provided by the
+National Science Foundation under grant MIP-9311980.  The original version
+of this code was written as part of a project to build a fixed-point vector
+processor in collaboration with the University of California at Berkeley,
+overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/
+arithmetic/SoftFloat.html'.
+
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
+RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
+
+Derivative works are acceptable, even for commercial purposes, so long as
+(1) the source code for the derivative work includes prominent notice that
+the work is derivative, and (2) the source code includes prominent notice with
+these four paragraphs for those parts of this code that are retained.
+
+=============================================================================*/
+
+#include "platform.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Raises the exceptions specified by `flags'.  Floating-point traps can be
+| defined here if desired.  It is currently not possible for such a trap
+| to substitute a result value.  If traps are not implemented, this routine
+| should be simply `float_exception_flags |= flags;'.
+*----------------------------------------------------------------------------*/
+
+void softfloat_raiseFlags( int_fast8_t flags )
+{
+
+    softfloat_exceptionFlags |= flags;
+
+}
+

diff --git a/softfloat/8086/softfloat_types.h b/softfloat/8086/softfloat_types.h
new file mode 100755 (executable)
index 0000000..b5c1828
--- /dev/null
+++ b/softfloat/8086/softfloat_types.h
@@ -0,0 +1,16 @@
+
+#ifndef softfloat_types_h
+#define softfloat_types_h
+
+/*** COMMENTS. ***/
+
+#include <stdbool.h>
+#include <stdint.h>
+
+typedef struct { uint32_t v; } float32_t;
+typedef struct { uint64_t v; } float64_t;
+typedef struct { uint64_t v; uint16_t x; } floatx80_t;
+typedef struct { uint64_t v[ 2 ]; } float128_t;
+
+#endif
+

diff --git a/softfloat/8086/specialize.h b/softfloat/8086/specialize.h
new file mode 100755 (executable)
index 0000000..ca0bb1d
--- /dev/null
+++ b/softfloat/8086/specialize.h
@@ -0,0 +1,113 @@
+\r
+/*============================================================================\r
+\r
+*** FIX.\r
+\r
+This C source fragment is part of the SoftFloat IEC/IEEE Floating-point\r
+Arithmetic Package, Release 2b.\r
+\r
+Written by John R. Hauser.  This work was made possible in part by the\r
+International Computer Science Institute, located at Suite 600, 1947 Center\r
+Street, Berkeley, California 94704.  Funding was partially provided by the\r
+National Science Foundation under grant MIP-9311980.  The original version\r
+of this code was written as part of a project to build a fixed-point vector\r
+processor in collaboration with the University of California at Berkeley,\r
+overseen by Profs. Nelson Morgan and John Wawrzynek.  More information\r
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
+arithmetic/SoftFloat.html'.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has\r
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
+RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
+\r
+Derivative works are acceptable, even for commercial purposes, so long as\r
+(1) the source code for the derivative work includes prominent notice that\r
+the work is derivative, and (2) the source code includes prominent notice with\r
+these four paragraphs for those parts of this code that are retained.\r
+\r
+=============================================================================*/\r
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+*----------------------------------------------------------------------------*/\r
+#define init_detectTininess softfloat_tininess_afterRounding;\r
+\r
+/*----------------------------------------------------------------------------\r
+| Structure used to transfer NaN representations from one format to another.\r
+*----------------------------------------------------------------------------*/\r
+struct commonNaN {\r
+    bool sign;\r
+    uint64_t v64, v0;\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+| The pattern for a default generated single-precision NaN.\r
+*----------------------------------------------------------------------------*/\r
+#define defaultNaNF32UI 0xFFC00000\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the single-precision floating-point value `a' is a signaling\r
+| NaN; otherwise, returns 0.\r
+*----------------------------------------------------------------------------*/\r
+#if defined INLINE_LEVEL && ( 1 <= INLINE_LEVEL )\r
+INLINE bool softfloat_isSigNaNF32UI( uint_fast32_t ui )\r
+    { return ( ( ui>>22 & 0x1FF ) == 0x1FE ) && ( ui & 0x003FFFFF ); }\r
+#else\r
+bool softfloat_isSigNaNF32UI( uint_fast32_t );\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+*----------------------------------------------------------------------------*/\r
+struct commonNaN softfloat_f32UIToCommonNaN( uint_fast32_t );\r
+#if defined INLINE_LEVEL && ( 1 <= INLINE_LEVEL )\r
+INLINE uint_fast32_t softfloat_commonNaNToF32UI( struct commonNaN a )\r
+    { return (uint_fast32_t) a.sign<<31 | 0x7FC00000 | a.v64>>41; }\r
+#else\r
+uint_fast32_t softfloat_commonNaNToF32UI( struct commonNaN );\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes two single-precision floating-point values `a' and `b', one of which\r
+| is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a\r
+| signaling NaN, the invalid exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+uint_fast32_t softfloat_propagateNaNF32UI( uint_fast32_t, uint_fast32_t );\r
+\r
+/*----------------------------------------------------------------------------\r
+| The pattern for a default generated double-precision NaN.\r
+*----------------------------------------------------------------------------*/\r
+#define defaultNaNF64UI UINT64_C(0xFFF8000000000000)\r
+\r
+/*----------------------------------------------------------------------------\r
+*----------------------------------------------------------------------------*/\r
+#if defined INLINE_LEVEL && ( 1 <= INLINE_LEVEL )\r
+INLINE bool softfloat_isSigNaNF64UI( uint_fast64_t ui )\r
+{\r
+    return\r
+        ( ( ui>>51 & 0xFFF ) == 0xFFE )\r
+            && ( ui & UINT64_C( 0x0007FFFFFFFFFFFF ) );\r
+}\r
+#else\r
+bool softfloat_isSigNaNF64UI( uint_fast64_t );\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+*----------------------------------------------------------------------------*/\r
+/*** MIGHT BE INLINE'D. ***/\r
+struct commonNaN softfloat_f64UIToCommonNaN( uint_fast64_t );\r
+uint_fast64_t softfloat_commonNaNToF64UI( struct commonNaN );\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes two double-precision floating-point values `a' and `b', one of which\r
+| is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a\r
+| signaling NaN, the invalid exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+uint_fast64_t softfloat_propagateNaNF64UI( uint_fast64_t, uint_fast64_t );\r
+\r

diff --git a/softfloat/SoftFloat-3/source/8086/OLD-specialize.c b/softfloat/SoftFloat-3/source/8086/OLD-specialize.c
deleted file mode 100755 (executable)
index ffb306d..0000000
--- a/softfloat/SoftFloat-3/source/8086/OLD-specialize.c
+++ /dev/null
@@ -1,40 +0,0 @@
-\r
-/*============================================================================\r
-\r
-*** FIX.\r
-\r
-This C source fragment is part of the SoftFloat IEC/IEEE Floating-point\r
-Arithmetic Package, Release 2b.\r
-\r
-Written by John R. Hauser.  This work was made possible in part by the\r
-International Computer Science Institute, located at Suite 600, 1947 Center\r
-Street, Berkeley, California 94704.  Funding was partially provided by the\r
-National Science Foundation under grant MIP-9311980.  The original version\r
-of this code was written as part of a project to build a fixed-point vector\r
-processor in collaboration with the University of California at Berkeley,\r
-overseen by Profs. Nelson Morgan and John Wawrzynek.  More information\r
-is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
-arithmetic/SoftFloat.html'.\r
-\r
-THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has\r
-been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
-RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
-AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
-COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
-EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
-INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
-OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
-\r
-Derivative works are acceptable, even for commercial purposes, so long as\r
-(1) the source code for the derivative work includes prominent notice that\r
-the work is derivative, and (2) the source code includes prominent notice with\r
-these four paragraphs for those parts of this code that are retained.\r
-\r
-=============================================================================*/\r
-\r
-/*----------------------------------------------------------------------------\r
-| Underflow tininess-detection mode, statically initialized to default value.\r
-| (The declaration in `softfloat.h' must match the `int8' type here.)\r
-*----------------------------------------------------------------------------*/\r
-bool float_detectTininess = float_tininess_afterRounding;\r
-\r

diff --git a/softfloat/SoftFloat-3/source/8086/OLD-specialize.h b/softfloat/SoftFloat-3/source/8086/OLD-specialize.h
deleted file mode 100755 (executable)
index 9e4461c..0000000
--- a/softfloat/SoftFloat-3/source/8086/OLD-specialize.h
+++ /dev/null
@@ -1,379 +0,0 @@
-\r
-/*============================================================================\r
-\r
-*** FIX.\r
-\r
-This C source fragment is part of the SoftFloat IEC/IEEE Floating-point\r
-Arithmetic Package, Release 2b.\r
-\r
-Written by John R. Hauser.  This work was made possible in part by the\r
-International Computer Science Institute, located at Suite 600, 1947 Center\r
-Street, Berkeley, California 94704.  Funding was partially provided by the\r
-National Science Foundation under grant MIP-9311980.  The original version\r
-of this code was written as part of a project to build a fixed-point vector\r
-processor in collaboration with the University of California at Berkeley,\r
-overseen by Profs. Nelson Morgan and John Wawrzynek.  More information\r
-is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
-arithmetic/SoftFloat.html'.\r
-\r
-THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has\r
-been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
-RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
-AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
-COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
-EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
-INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
-OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
-\r
-Derivative works are acceptable, even for commercial purposes, so long as\r
-(1) the source code for the derivative work includes prominent notice that\r
-the work is derivative, and (2) the source code includes prominent notice with\r
-these four paragraphs for those parts of this code that are retained.\r
-\r
-=============================================================================*/\r
-\r
-/*----------------------------------------------------------------------------\r
-| Internal canonical NaN format.\r
-*----------------------------------------------------------------------------*/\r
-*** COMMON\r
-typedef struct {\r
-    flag sign;\r
-    uint128_t bits;\r
-} commonNaNT;\r
-\r
-/*----------------------------------------------------------------------------\r
-| The pattern for a default generated single-precision NaN.\r
-*----------------------------------------------------------------------------*/\r
-#define float32Bits_defaultNaN 0xFFC00000\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the single-precision floating-point value `a' is a NaN;\r
-| otherwise, returns 0.\r
-*----------------------------------------------------------------------------*/\r
-*** COMMON\r
-#define softfloat_isNaNFloat32Bits( a ) ( 0xFF000000 < (uint32_t) ( a )<<1 )\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the single-precision floating-point value `a' is a signaling\r
-| NaN; otherwise, returns 0.\r
-*----------------------------------------------------------------------------*/\r
-inline bool softfloat_isSigNaNFloat32Bits( uint32_t a )\r
-    { return ( ( a>>22 & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF ); }\r
-\r
-/*----------------------------------------------------------------------------\r
-*----------------------------------------------------------------------------*/\r
-commonNaNT softfloat_NaNFromFloat32Bits( uint32_t );\r
-uint32_t softfloat_float32BitsFromNaN( commonNaNT );\r
-uint32_t softfloat_propNaNFloat32Bits( uint32_t, uint32_t );\r
-\r
-/*----------------------------------------------------------------------------\r
-| The pattern for a default generated double-precision NaN.\r
-*----------------------------------------------------------------------------*/\r
-#define float64Bits_defaultNaN 0xFFF8000000000000\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the double-precision floating-point value `a' is a NaN;\r
-| otherwise, returns 0.\r
-*----------------------------------------------------------------------------*/\r
-*** COMMON\r
-#define softfloat_isNaNFloat64Bits( a ) ( 0xFFE0000000000000 < (uint64_t) ( a )<<1 )\r
-\r
-\r
-\r
-\r
-\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the double-precision floating-point value `a' is a signaling\r
-| NaN; otherwise, returns 0.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag float64_is_signaling_nan( float64 a )\r
-{\r
-\r
-    return\r
-           ( ( ( a>>51 ) & 0xFFF ) == 0xFFE )\r
-        && ( a & LIT64( 0x0007FFFFFFFFFFFF ) );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the double-precision floating-point NaN\r
-| `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid\r
-| exception is raised.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static commonNaNT float64ToCommonNaN( float64 a )\r
-{\r
-    commonNaNT z;\r
-\r
-    if ( float64_is_signaling_nan( a ) ) float_raise( float_flag_invalid );\r
-    z.sign = a>>63;\r
-    z.low = 0;\r
-    z.high = a<<12;\r
-    return z;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the canonical NaN `a' to the double-\r
-| precision floating-point format.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static float64 commonNaNToFloat64( commonNaNT a )\r
-{\r
-\r
-    return\r
-          ( ( (bits64) a.sign )<<63 )\r
-        | LIT64( 0x7FF8000000000000 )\r
-        | ( a.high>>12 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Takes two double-precision floating-point values `a' and `b', one of which\r
-| is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a\r
-| signaling NaN, the invalid exception is raised.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static float64 propagateFloat64NaN( float64 a, float64 b )\r
-{\r
-    flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;\r
-\r
-    aIsNaN = float64_is_nan( a );\r
-    aIsSignalingNaN = float64_is_signaling_nan( a );\r
-    bIsNaN = float64_is_nan( b );\r
-    bIsSignalingNaN = float64_is_signaling_nan( b );\r
-    a |= LIT64( 0x0008000000000000 );\r
-    b |= LIT64( 0x0008000000000000 );\r
-    if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );\r
-    if ( aIsSignalingNaN ) {\r
-        if ( bIsSignalingNaN ) goto returnLargerSignificand;\r
-        return bIsNaN ? b : a;\r
-    }\r
-    else if ( aIsNaN ) {\r
-        if ( bIsSignalingNaN | ! bIsNaN ) return a;\r
- returnLargerSignificand:\r
-        if ( (bits64) ( a<<1 ) < (bits64) ( b<<1 ) ) return b;\r
-        if ( (bits64) ( b<<1 ) < (bits64) ( a<<1 ) ) return a;\r
-        return ( a < b ) ? a : b;\r
-    }\r
-    else {\r
-        return b;\r
-    }\r
-\r
-}\r
-\r
-#ifdef FLOATX80\r
-\r
-/*----------------------------------------------------------------------------\r
-| The pattern for a default generated extended double-precision NaN.  The\r
-| `high' and `low' values hold the most- and least-significant bits,\r
-| respectively.\r
-*----------------------------------------------------------------------------*/\r
-#define floatx80_default_nan_high 0xFFFF\r
-#define floatx80_default_nan_low  LIT64( 0xC000000000000000 )\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the extended double-precision floating-point value `a' is a\r
-| NaN; otherwise, returns 0.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag floatx80_is_nan( floatx80 a )\r
-{\r
-\r
-    return ( ( a.high & 0x7FFF ) == 0x7FFF ) && (bits64) ( a.low<<1 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the extended double-precision floating-point value `a' is a\r
-| signaling NaN; otherwise, returns 0.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag floatx80_is_signaling_nan( floatx80 a )\r
-{\r
-    bits64 aLow;\r
-\r
-    aLow = a.low & ~ LIT64( 0x4000000000000000 );\r
-    return\r
-           ( ( a.high & 0x7FFF ) == 0x7FFF )\r
-        && (bits64) ( aLow<<1 )\r
-        && ( a.low == aLow );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the extended double-precision floating-\r
-| point NaN `a' to the canonical NaN format.  If `a' is a signaling NaN, the\r
-| invalid exception is raised.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static commonNaNT floatx80ToCommonNaN( floatx80 a )\r
-{\r
-    commonNaNT z;\r
-\r
-    if ( floatx80_is_signaling_nan( a ) ) float_raise( float_flag_invalid );\r
-    z.sign = a.high>>15;\r
-    z.low = 0;\r
-    z.high = a.low<<1;\r
-    return z;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the canonical NaN `a' to the extended\r
-| double-precision floating-point format.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static floatx80 commonNaNToFloatx80( commonNaNT a )\r
-{\r
-    floatx80 z;\r
-\r
-    z.low = LIT64( 0xC000000000000000 ) | ( a.high>>1 );\r
-    z.high = ( ( (bits16) a.sign )<<15 ) | 0x7FFF;\r
-    return z;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Takes two extended double-precision floating-point values `a' and `b', one\r
-| of which is a NaN, and returns the appropriate NaN result.  If either `a' or\r
-| `b' is a signaling NaN, the invalid exception is raised.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static floatx80 propagateFloatx80NaN( floatx80 a, floatx80 b )\r
-{\r
-    flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;\r
-\r
-    aIsNaN = floatx80_is_nan( a );\r
-    aIsSignalingNaN = floatx80_is_signaling_nan( a );\r
-    bIsNaN = floatx80_is_nan( b );\r
-    bIsSignalingNaN = floatx80_is_signaling_nan( b );\r
-    a.low |= LIT64( 0xC000000000000000 );\r
-    b.low |= LIT64( 0xC000000000000000 );\r
-    if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );\r
-    if ( aIsSignalingNaN ) {\r
-        if ( bIsSignalingNaN ) goto returnLargerSignificand;\r
-        return bIsNaN ? b : a;\r
-    }\r
-    else if ( aIsNaN ) {\r
-        if ( bIsSignalingNaN | ! bIsNaN ) return a;\r
- returnLargerSignificand:\r
-        if ( a.low < b.low ) return b;\r
-        if ( b.low < a.low ) return a;\r
-        return ( a.high < b.high ) ? a : b;\r
-    }\r
-    else {\r
-        return b;\r
-    }\r
-\r
-}\r
-\r
-#endif\r
-\r
-#ifdef FLOAT128\r
-\r
-/*----------------------------------------------------------------------------\r
-| The pattern for a default generated quadruple-precision NaN.  The `high' and\r
-| `low' values hold the most- and least-significant bits, respectively.\r
-*----------------------------------------------------------------------------*/\r
-#define float128_default_nan_high LIT64( 0xFFFF800000000000 )\r
-#define float128_default_nan_low  LIT64( 0x0000000000000000 )\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the quadruple-precision floating-point value `a' is a NaN;\r
-| otherwise, returns 0.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag float128_is_nan( float128 a )\r
-{\r
-\r
-    return\r
-           ( LIT64( 0xFFFE000000000000 ) <= (bits64) ( a.high<<1 ) )\r
-        && ( a.low || ( a.high & LIT64( 0x0000FFFFFFFFFFFF ) ) );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the quadruple-precision floating-point value `a' is a\r
-| signaling NaN; otherwise, returns 0.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag float128_is_signaling_nan( float128 a )\r
-{\r
-\r
-    return\r
-           ( ( ( a.high>>47 ) & 0xFFFF ) == 0xFFFE )\r
-        && ( a.low || ( a.high & LIT64( 0x00007FFFFFFFFFFF ) ) );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the quadruple-precision floating-point NaN\r
-| `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid\r
-| exception is raised.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static commonNaNT float128ToCommonNaN( float128 a )\r
-{\r
-    commonNaNT z;\r
-\r
-    if ( float128_is_signaling_nan( a ) ) float_raise( float_flag_invalid );\r
-    z.sign = a.high>>63;\r
-    shortShift128Left( a.high, a.low, 16, &z.high, &z.low );\r
-    return z;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the canonical NaN `a' to the quadruple-\r
-| precision floating-point format.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static float128 commonNaNToFloat128( commonNaNT a )\r
-{\r
-    float128 z;\r
-\r
-    shift128Right( a.high, a.low, 16, &z.high, &z.low );\r
-    z.high |= ( ( (bits64) a.sign )<<63 ) | LIT64( 0x7FFF800000000000 );\r
-    return z;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Takes two quadruple-precision floating-point values `a' and `b', one of\r
-| which is a NaN, and returns the appropriate NaN result.  If either `a' or\r
-| `b' is a signaling NaN, the invalid exception is raised.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static float128 propagateFloat128NaN( float128 a, float128 b )\r
-{\r
-    flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;\r
-\r
-    aIsNaN = float128_is_nan( a );\r
-    aIsSignalingNaN = float128_is_signaling_nan( a );\r
-    bIsNaN = float128_is_nan( b );\r
-    bIsSignalingNaN = float128_is_signaling_nan( b );\r
-    a.high |= LIT64( 0x0000800000000000 );\r
-    b.high |= LIT64( 0x0000800000000000 );\r
-    if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );\r
-    if ( aIsSignalingNaN ) {\r
-        if ( bIsSignalingNaN ) goto returnLargerSignificand;\r
-        return bIsNaN ? b : a;\r
-    }\r
-    else if ( aIsNaN ) {\r
-        if ( bIsSignalingNaN | ! bIsNaN ) return a;\r
- returnLargerSignificand:\r
-        if ( lt128( a.high<<1, a.low, b.high<<1, b.low ) ) return b;\r
-        if ( lt128( b.high<<1, b.low, a.high<<1, a.low ) ) return a;\r
-        return ( a.high < b.high ) ? a : b;\r
-    }\r
-    else {\r
-        return b;\r
-    }\r
-\r
-}\r
-\r
-#endif\r
-\r

diff --git a/softfloat/SoftFloat-3/source/8086/platform.h b/softfloat/SoftFloat-3/source/8086/platform.h
deleted file mode 100755 (executable)
index 9355edf..0000000
--- a/softfloat/SoftFloat-3/source/8086/platform.h
+++ /dev/null
@@ -1,38 +0,0 @@
-
-/*============================================================================
-
-*** FIX.
-
-This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
-Arithmetic Package, Release 2b.
-
-Written by John R. Hauser.  This work was made possible in part by the
-International Computer Science Institute, located at Suite 600, 1947 Center
-Street, Berkeley, California 94704.  Funding was partially provided by the
-National Science Foundation under grant MIP-9311980.  The original version
-of this code was written as part of a project to build a fixed-point vector
-processor in collaboration with the University of California at Berkeley,
-overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
-is available through the Web page `http://www.cs.berkeley.edu/~jhauser/
-arithmetic/SoftFloat.html'.
-
-THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has
-been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
-RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
-AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
-COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
-EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
-INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR
-OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
-
-Derivative works are acceptable, even for commercial purposes, so long as
-(1) the source code for the derivative work includes prominent notice that
-the work is derivative, and (2) the source code includes prominent notice with
-these four paragraphs for those parts of this code that are retained.
-
-=============================================================================*/
-
-/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
-#define LITTLEENDIAN
-

diff --git a/softfloat/SoftFloat-3/source/8086/s_commonNaNToF32UI.c b/softfloat/SoftFloat-3/source/8086/s_commonNaNToF32UI.c
deleted file mode 100755 (executable)
index 3b96c41..0000000
--- a/softfloat/SoftFloat-3/source/8086/s_commonNaNToF32UI.c
+++ /dev/null
@@ -1,17 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "specialize.h"\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the canonical NaN `a' to the single-\r
-| precision floating-point format.\r
-*----------------------------------------------------------------------------*/\r
-\r
-uint_fast32_t softfloat_commonNaNToF32UI( struct commonNaN a )\r
-{\r
-\r
-    return (uint_fast32_t) a.sign<<31 | 0x7FC00000 | a.v64>>41;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/8086/s_commonNaNToF64UI.c b/softfloat/SoftFloat-3/source/8086/s_commonNaNToF64UI.c
deleted file mode 100755 (executable)
index 474ceee..0000000
--- a/softfloat/SoftFloat-3/source/8086/s_commonNaNToF64UI.c
+++ /dev/null
@@ -1,19 +0,0 @@
-
-#include <stdint.h>
-#include "platform.h"
-#include "specialize.h"
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the canonical NaN `a' to the double-
-| precision floating-point format.
-*----------------------------------------------------------------------------*/
-
-uint_fast64_t softfloat_commonNaNToF64UI( struct commonNaN a )
-{
-
-    return
-        (uint_fast64_t) a.sign<<63 | UINT64_C( 0x7FF8000000000000 )
-            | a.v64>>12;
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/8086/s_f32UIToCommonNaN.c b/softfloat/SoftFloat-3/source/8086/s_f32UIToCommonNaN.c
deleted file mode 100755 (executable)
index 067e8da..0000000
--- a/softfloat/SoftFloat-3/source/8086/s_f32UIToCommonNaN.c
+++ /dev/null
@@ -1,25 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "specialize.h"\r
-#include "softfloat.h"\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the single-precision floating-point NaN\r
-| `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid\r
-| exception is raised.\r
-*----------------------------------------------------------------------------*/\r
-struct commonNaN softfloat_f32UIToCommonNaN( uint_fast32_t uiA )\r
-{\r
-    struct commonNaN z;\r
-\r
-    if ( softfloat_isSigNaNF32UI( uiA ) ) {\r
-        softfloat_raiseFlags( softfloat_flag_invalid );\r
-    }\r
-    z.sign = uiA>>31;\r
-    z.v64 = (uint_fast64_t) uiA<<41;\r
-    z.v0 = 0;\r
-    return z;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/8086/s_f64UIToCommonNaN.c b/softfloat/SoftFloat-3/source/8086/s_f64UIToCommonNaN.c
deleted file mode 100755 (executable)
index f933ded..0000000
--- a/softfloat/SoftFloat-3/source/8086/s_f64UIToCommonNaN.c
+++ /dev/null
@@ -1,25 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "specialize.h"\r
-#include "softfloat.h"\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the double-precision floating-point NaN\r
-| `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid\r
-| exception is raised.\r
-*----------------------------------------------------------------------------*/\r
-struct commonNaN softfloat_f64UIToCommonNaN( uint_fast64_t uiA )\r
-{\r
-    struct commonNaN z;\r
-\r
-    if ( softfloat_isSigNaNF64UI( uiA ) ) {\r
-        softfloat_raiseFlags( softfloat_flag_invalid );\r
-    }\r
-    z.sign = uiA>>63;\r
-    z.v64 = uiA<<12;\r
-    z.v0 = 0;\r
-    return z;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/8086/s_isSigNaNF32UI.c b/softfloat/SoftFloat-3/source/8086/s_isSigNaNF32UI.c
deleted file mode 100755 (executable)
index 0a9c33f..0000000
--- a/softfloat/SoftFloat-3/source/8086/s_isSigNaNF32UI.c
+++ /dev/null
@@ -1,13 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "specialize.h"
-
-bool softfloat_isSigNaNF32UI( uint_fast32_t ui )
-{
-
-    return ( ( ui>>22 & 0x1FF ) == 0x1FE ) && ( ui & 0x003FFFFF );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/8086/s_isSigNaNF64UI.c b/softfloat/SoftFloat-3/source/8086/s_isSigNaNF64UI.c
deleted file mode 100755 (executable)
index d255213..0000000
--- a/softfloat/SoftFloat-3/source/8086/s_isSigNaNF64UI.c
+++ /dev/null
@@ -1,15 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "specialize.h"
-
-bool softfloat_isSigNaNF64UI( uint_fast64_t ui )
-{
-
-    return
-        ( ( ui>>51 & 0xFFF ) == 0xFFE )
-            && ( ui & UINT64_C( 0x0007FFFFFFFFFFFF ) );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/8086/s_propagateNaNF32UI.c b/softfloat/SoftFloat-3/source/8086/s_propagateNaNF32UI.c
deleted file mode 100755 (executable)
index 07774e8..0000000
--- a/softfloat/SoftFloat-3/source/8086/s_propagateNaNF32UI.c
+++ /dev/null
@@ -1,55 +0,0 @@
-\r
-/*** UPDATE COMMENTS. ***/\r
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "internals.h"\r
-#include "specialize.h"\r
-#include "softfloat.h"\r
-\r
-/*----------------------------------------------------------------------------\r
-| Takes two single-precision floating-point values `a' and `b', one of which\r
-| is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a\r
-| signaling NaN, the invalid exception is raised.\r
-*----------------------------------------------------------------------------*/\r
-\r
-uint_fast32_t\r
- softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB )\r
-{\r
-    bool isNaNA, isSigNaNA, isNaNB, isSigNaNB;\r
-    uint_fast32_t uiMagA, uiMagB;\r
-\r
-    /*------------------------------------------------------------------------\r
-    *------------------------------------------------------------------------*/\r
-    isNaNA = isNaNF32UI( uiA );\r
-    isSigNaNA = softfloat_isSigNaNF32UI( uiA );\r
-    isNaNB = isNaNF32UI( uiB );\r
-    isSigNaNB = softfloat_isSigNaNF32UI( uiB );\r
-    /*------------------------------------------------------------------------\r
-    | Make NaNs non-signaling.\r
-    *------------------------------------------------------------------------*/\r
-    uiA |= 0x00400000;\r
-    uiB |= 0x00400000;\r
-    /*------------------------------------------------------------------------\r
-    *------------------------------------------------------------------------*/\r
-    if ( isSigNaNA | isSigNaNB ) {\r
-        softfloat_raiseFlags( softfloat_flag_invalid );\r
-    }\r
-    if ( isSigNaNA ) {\r
-        if ( isSigNaNB ) goto returnLargerSignificand;\r
-        return isNaNB ? uiB : uiA;\r
-    } else if ( isNaNA ) {\r
-        if ( isSigNaNB || ! isNaNB ) return uiA;\r
- returnLargerSignificand:\r
-        uiMagA = uiA<<1;\r
-        uiMagB = uiB<<1;\r
-        if ( uiMagA < uiMagB ) return uiB;\r
-        if ( uiMagB < uiMagA ) return uiA;\r
-        return ( uiA < uiB ) ? uiA : uiB;\r
-    } else {\r
-        return uiB;\r
-    }\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/8086/s_propagateNaNF64UI.c b/softfloat/SoftFloat-3/source/8086/s_propagateNaNF64UI.c
deleted file mode 100755 (executable)
index 0ff6446..0000000
--- a/softfloat/SoftFloat-3/source/8086/s_propagateNaNF64UI.c
+++ /dev/null
@@ -1,55 +0,0 @@
-
-/*** UPDATE COMMENTS. ***/
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "specialize.h"
-#include "softfloat.h"
-
-/*----------------------------------------------------------------------------
-| Takes two double-precision floating-point values `a' and `b', one of which
-| is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a
-| signaling NaN, the invalid exception is raised.
-*----------------------------------------------------------------------------*/
-
-uint_fast64_t
- softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB )
-{
-    bool isNaNA, isSigNaNA, isNaNB, isSigNaNB;
-    uint_fast64_t uiMagA, uiMagB;
-
-    /*------------------------------------------------------------------------
-    *------------------------------------------------------------------------*/
-    isNaNA = isNaNF64UI( uiA );
-    isSigNaNA = softfloat_isSigNaNF64UI( uiA );
-    isNaNB = isNaNF64UI( uiB );
-    isSigNaNB = softfloat_isSigNaNF64UI( uiB );
-    /*------------------------------------------------------------------------
-    | Make NaNs non-signaling.
-    *------------------------------------------------------------------------*/
-    uiA |= UINT64_C( 0x0008000000000000 );
-    uiB |= UINT64_C( 0x0008000000000000 );
-    /*------------------------------------------------------------------------
-    *------------------------------------------------------------------------*/
-    if ( isSigNaNA | isSigNaNB ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
-    }
-    if ( isSigNaNA ) {
-        if ( isSigNaNB ) goto returnLargerSignificand;
-        return isNaNB ? uiB : uiA;
-    } else if ( isNaNA ) {
-        if ( isSigNaNB || ! isNaNB ) return uiA;
- returnLargerSignificand:
-        uiMagA = uiA & UINT64_C( 0x7FFFFFFFFFFFFFFF );
-        uiMagB = uiB & UINT64_C( 0x7FFFFFFFFFFFFFFF );
-        if ( uiMagA < uiMagB ) return uiB;
-        if ( uiMagB < uiMagA ) return uiA;
-        return ( uiA < uiB ) ? uiA : uiB;
-    } else {
-        return uiB;
-    }
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/8086/softfloat_raiseFlags.c b/softfloat/SoftFloat-3/source/8086/softfloat_raiseFlags.c
deleted file mode 100755 (executable)
index c0c0dc8..0000000
--- a/softfloat/SoftFloat-3/source/8086/softfloat_raiseFlags.c
+++ /dev/null
@@ -1,51 +0,0 @@
-
-/*============================================================================
-
-*** FIX.
-
-This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
-Arithmetic Package, Release 2b.
-
-Written by John R. Hauser.  This work was made possible in part by the
-International Computer Science Institute, located at Suite 600, 1947 Center
-Street, Berkeley, California 94704.  Funding was partially provided by the
-National Science Foundation under grant MIP-9311980.  The original version
-of this code was written as part of a project to build a fixed-point vector
-processor in collaboration with the University of California at Berkeley,
-overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
-is available through the Web page `http://www.cs.berkeley.edu/~jhauser/
-arithmetic/SoftFloat.html'.
-
-THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has
-been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
-RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
-AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
-COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
-EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
-INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR
-OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
-
-Derivative works are acceptable, even for commercial purposes, so long as
-(1) the source code for the derivative work includes prominent notice that
-the work is derivative, and (2) the source code includes prominent notice with
-these four paragraphs for those parts of this code that are retained.
-
-=============================================================================*/
-
-#include "platform.h"
-#include "softfloat.h"
-
-/*----------------------------------------------------------------------------
-| Raises the exceptions specified by `flags'.  Floating-point traps can be
-| defined here if desired.  It is currently not possible for such a trap
-| to substitute a result value.  If traps are not implemented, this routine
-| should be simply `float_exception_flags |= flags;'.
-*----------------------------------------------------------------------------*/
-
-void softfloat_raiseFlags( int_fast8_t flags )
-{
-
-    softfloat_exceptionFlags |= flags;
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/8086/softfloat_types.h b/softfloat/SoftFloat-3/source/8086/softfloat_types.h
deleted file mode 100755 (executable)
index b5c1828..0000000
--- a/softfloat/SoftFloat-3/source/8086/softfloat_types.h
+++ /dev/null
@@ -1,16 +0,0 @@
-
-#ifndef softfloat_types_h
-#define softfloat_types_h
-
-/*** COMMENTS. ***/
-
-#include <stdbool.h>
-#include <stdint.h>
-
-typedef struct { uint32_t v; } float32_t;
-typedef struct { uint64_t v; } float64_t;
-typedef struct { uint64_t v; uint16_t x; } floatx80_t;
-typedef struct { uint64_t v[ 2 ]; } float128_t;
-
-#endif
-

diff --git a/softfloat/SoftFloat-3/source/8086/specialize.h b/softfloat/SoftFloat-3/source/8086/specialize.h
deleted file mode 100755 (executable)
index ca0bb1d..0000000
--- a/softfloat/SoftFloat-3/source/8086/specialize.h
+++ /dev/null
@@ -1,113 +0,0 @@
-\r
-/*============================================================================\r
-\r
-*** FIX.\r
-\r
-This C source fragment is part of the SoftFloat IEC/IEEE Floating-point\r
-Arithmetic Package, Release 2b.\r
-\r
-Written by John R. Hauser.  This work was made possible in part by the\r
-International Computer Science Institute, located at Suite 600, 1947 Center\r
-Street, Berkeley, California 94704.  Funding was partially provided by the\r
-National Science Foundation under grant MIP-9311980.  The original version\r
-of this code was written as part of a project to build a fixed-point vector\r
-processor in collaboration with the University of California at Berkeley,\r
-overseen by Profs. Nelson Morgan and John Wawrzynek.  More information\r
-is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
-arithmetic/SoftFloat.html'.\r
-\r
-THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has\r
-been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
-RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
-AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
-COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
-EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
-INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
-OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
-\r
-Derivative works are acceptable, even for commercial purposes, so long as\r
-(1) the source code for the derivative work includes prominent notice that\r
-the work is derivative, and (2) the source code includes prominent notice with\r
-these four paragraphs for those parts of this code that are retained.\r
-\r
-=============================================================================*/\r
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-\r
-/*----------------------------------------------------------------------------\r
-*----------------------------------------------------------------------------*/\r
-#define init_detectTininess softfloat_tininess_afterRounding;\r
-\r
-/*----------------------------------------------------------------------------\r
-| Structure used to transfer NaN representations from one format to another.\r
-*----------------------------------------------------------------------------*/\r
-struct commonNaN {\r
-    bool sign;\r
-    uint64_t v64, v0;\r
-};\r
-\r
-/*----------------------------------------------------------------------------\r
-| The pattern for a default generated single-precision NaN.\r
-*----------------------------------------------------------------------------*/\r
-#define defaultNaNF32UI 0xFFC00000\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the single-precision floating-point value `a' is a signaling\r
-| NaN; otherwise, returns 0.\r
-*----------------------------------------------------------------------------*/\r
-#if defined INLINE_LEVEL && ( 1 <= INLINE_LEVEL )\r
-INLINE bool softfloat_isSigNaNF32UI( uint_fast32_t ui )\r
-    { return ( ( ui>>22 & 0x1FF ) == 0x1FE ) && ( ui & 0x003FFFFF ); }\r
-#else\r
-bool softfloat_isSigNaNF32UI( uint_fast32_t );\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------\r
-*----------------------------------------------------------------------------*/\r
-struct commonNaN softfloat_f32UIToCommonNaN( uint_fast32_t );\r
-#if defined INLINE_LEVEL && ( 1 <= INLINE_LEVEL )\r
-INLINE uint_fast32_t softfloat_commonNaNToF32UI( struct commonNaN a )\r
-    { return (uint_fast32_t) a.sign<<31 | 0x7FC00000 | a.v64>>41; }\r
-#else\r
-uint_fast32_t softfloat_commonNaNToF32UI( struct commonNaN );\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------\r
-| Takes two single-precision floating-point values `a' and `b', one of which\r
-| is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a\r
-| signaling NaN, the invalid exception is raised.\r
-*----------------------------------------------------------------------------*/\r
-uint_fast32_t softfloat_propagateNaNF32UI( uint_fast32_t, uint_fast32_t );\r
-\r
-/*----------------------------------------------------------------------------\r
-| The pattern for a default generated double-precision NaN.\r
-*----------------------------------------------------------------------------*/\r
-#define defaultNaNF64UI UINT64_C(0xFFF8000000000000)\r
-\r
-/*----------------------------------------------------------------------------\r
-*----------------------------------------------------------------------------*/\r
-#if defined INLINE_LEVEL && ( 1 <= INLINE_LEVEL )\r
-INLINE bool softfloat_isSigNaNF64UI( uint_fast64_t ui )\r
-{\r
-    return\r
-        ( ( ui>>51 & 0xFFF ) == 0xFFE )\r
-            && ( ui & UINT64_C( 0x0007FFFFFFFFFFFF ) );\r
-}\r
-#else\r
-bool softfloat_isSigNaNF64UI( uint_fast64_t );\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------\r
-*----------------------------------------------------------------------------*/\r
-/*** MIGHT BE INLINE'D. ***/\r
-struct commonNaN softfloat_f64UIToCommonNaN( uint_fast64_t );\r
-uint_fast64_t softfloat_commonNaNToF64UI( struct commonNaN );\r
-\r
-/*----------------------------------------------------------------------------\r
-| Takes two double-precision floating-point values `a' and `b', one of which\r
-| is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a\r
-| signaling NaN, the invalid exception is raised.\r
-*----------------------------------------------------------------------------*/\r
-uint_fast64_t softfloat_propagateNaNF64UI( uint_fast64_t, uint_fast64_t );\r
-\r

diff --git a/softfloat/SoftFloat-3/source/OLD-softfloat.c b/softfloat/SoftFloat-3/source/OLD-softfloat.c
deleted file mode 100755 (executable)
index 0096550..0000000
--- a/softfloat/SoftFloat-3/source/OLD-softfloat.c
+++ /dev/null
@@ -1,2962 +0,0 @@
-
-/*============================================================================
-
-This C source file is part of the SoftFloat IEC/IEEE Floating-point Arithmetic
-Package, Release 2b.
-
-Written by John R. Hauser.  This work was made possible in part by the
-International Computer Science Institute, located at Suite 600, 1947 Center
-Street, Berkeley, California 94704.  Funding was partially provided by the
-National Science Foundation under grant MIP-9311980.  The original version
-of this code was written as part of a project to build a fixed-point vector
-processor in collaboration with the University of California at Berkeley,
-overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
-is available through the Web page `http://www.cs.berkeley.edu/~jhauser/
-arithmetic/SoftFloat.html'.
-
-THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has
-been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
-RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
-AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
-COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
-EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
-INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR
-OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
-
-Derivative works are acceptable, even for commercial purposes, so long as
-(1) the source code for the derivative work includes prominent notice that
-the work is derivative, and (2) the source code includes prominent notice with
-these four paragraphs for those parts of this code that are retained.
-
-=============================================================================*/
-
-#include "milieu.h"
-#include "softfloat.h"
-
-/*----------------------------------------------------------------------------
-| Primitive arithmetic functions, including multi-word arithmetic, and
-| division and square root approximations.  (Can be specialized to target if
-| desired.)
-*----------------------------------------------------------------------------*/
-#include "softfloat-macros"
-
-/*----------------------------------------------------------------------------
-| Functions and definitions to determine:  (1) whether tininess for underflow
-| is detected before or after rounding by default, (2) what (if anything)
-| happens when exceptions are raised, (3) how signaling NaNs are distinguished
-| from quiet NaNs, (4) the default generated quiet NaNs, and (5) how NaNs
-| are propagated from function inputs to output.  These details are target-
-| specific.
-*----------------------------------------------------------------------------*/
-#include "softfloat-specialize"
-
-#ifdef FLOATX80
-
-/*----------------------------------------------------------------------------
-| Returns the fraction bits of the extended double-precision floating-point
-| value `a'.
-*----------------------------------------------------------------------------*/
-
-INLINE bits64 extractFloatx80Frac( floatx80 a )
-{
-
-    return a.low;
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the exponent bits of the extended double-precision floating-point
-| value `a'.
-*----------------------------------------------------------------------------*/
-
-INLINE int32 extractFloatx80Exp( floatx80 a )
-{
-
-    return a.high & 0x7FFF;
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the sign bit of the extended double-precision floating-point value
-| `a'.
-*----------------------------------------------------------------------------*/
-
-INLINE flag extractFloatx80Sign( floatx80 a )
-{
-
-    return a.high>>15;
-
-}
-
-/*----------------------------------------------------------------------------
-| Normalizes the subnormal extended double-precision floating-point value
-| represented by the denormalized significand `aSig'.  The normalized exponent
-| and significand are stored at the locations pointed to by `zExpPtr' and
-| `zSigPtr', respectively.
-*----------------------------------------------------------------------------*/
-
-static void
- normalizeFloatx80Subnormal( bits64 aSig, int32 *zExpPtr, bits64 *zSigPtr )
-{
-    int8 shiftCount;
-
-    shiftCount = countLeadingZeros64( aSig );
-    *zSigPtr = aSig<<shiftCount;
-    *zExpPtr = 1 - shiftCount;
-
-}
-
-/*----------------------------------------------------------------------------
-| Packs the sign `zSign', exponent `zExp', and significand `zSig' into an
-| extended double-precision floating-point value, returning the result.
-*----------------------------------------------------------------------------*/
-
-INLINE floatx80 packFloatx80( flag zSign, int32 zExp, bits64 zSig )
-{
-    floatx80 z;
-
-    z.low = zSig;
-    z.high = ( ( (bits16) zSign )<<15 ) + zExp;
-    return z;
-
-}
-
-/*----------------------------------------------------------------------------
-| Takes an abstract floating-point value having sign `zSign', exponent `zExp',
-| and extended significand formed by the concatenation of `zSig0' and `zSig1',
-| and returns the proper extended double-precision floating-point value
-| corresponding to the abstract input.  Ordinarily, the abstract value is
-| rounded and packed into the extended double-precision format, with the
-| inexact exception raised if the abstract input cannot be represented
-| exactly.  However, if the abstract value is too large, the overflow and
-| inexact exceptions are raised and an infinity or maximal finite value is
-| returned.  If the abstract value is too small, the input value is rounded to
-| a subnormal number, and the underflow and inexact exceptions are raised if
-| the abstract input cannot be represented exactly as a subnormal extended
-| double-precision floating-point number.
-|     If `roundingPrecision' is 32 or 64, the result is rounded to the same
-| number of bits as single or double precision, respectively.  Otherwise, the
-| result is rounded to the full precision of the extended double-precision
-| format.
-|     The input significand must be normalized or smaller.  If the input
-| significand is not normalized, `zExp' must be 0; in that case, the result
-| returned is a subnormal number, and it must not require rounding.  The
-| handling of underflow and overflow follows the IEC/IEEE Standard for Binary
-| Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-static floatx80
- roundAndPackFloatx80(
-     int8 roundingPrecision, flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1
- )
-{
-    int8 roundingMode;
-    flag roundNearestEven, increment, isTiny;
-    int64 roundIncrement, roundMask, roundBits;
-
-    roundingMode = float_rounding_mode;
-    roundNearestEven = ( roundingMode == float_round_nearest_even );
-    if ( roundingPrecision == 80 ) goto precision80;
-    if ( roundingPrecision == 64 ) {
-        roundIncrement = LIT64( 0x0000000000000400 );
-        roundMask = LIT64( 0x00000000000007FF );
-    }
-    else if ( roundingPrecision == 32 ) {
-        roundIncrement = LIT64( 0x0000008000000000 );
-        roundMask = LIT64( 0x000000FFFFFFFFFF );
-    }
-    else {
-        goto precision80;
-    }
-    zSig0 |= ( zSig1 != 0 );
-    if ( ! roundNearestEven ) {
-        if ( roundingMode == float_round_to_zero ) {
-            roundIncrement = 0;
-        }
-        else {
-            roundIncrement = roundMask;
-            if ( zSign ) {
-                if ( roundingMode == float_round_up ) roundIncrement = 0;
-            }
-            else {
-                if ( roundingMode == float_round_down ) roundIncrement = 0;
-            }
-        }
-    }
-    roundBits = zSig0 & roundMask;
-    if ( 0x7FFD <= (bits32) ( zExp - 1 ) ) {
-        if (    ( 0x7FFE < zExp )
-             || ( ( zExp == 0x7FFE ) && ( zSig0 + roundIncrement < zSig0 ) )
-           ) {
-            goto overflow;
-        }
-        if ( zExp <= 0 ) {
-            isTiny =
-                   ( float_detect_tininess == float_tininess_before_rounding )
-                || ( zExp < 0 )
-                || ( zSig0 <= zSig0 + roundIncrement );
-            shift64RightJamming( zSig0, 1 - zExp, &zSig0 );
-            zExp = 0;
-            roundBits = zSig0 & roundMask;
-            if ( isTiny && roundBits ) float_raise( float_flag_underflow );
-            if ( roundBits ) float_exception_flags |= float_flag_inexact;
-            zSig0 += roundIncrement;
-            if ( (sbits64) zSig0 < 0 ) zExp = 1;
-            roundIncrement = roundMask + 1;
-            if ( roundNearestEven && ( roundBits<<1 == roundIncrement ) ) {
-                roundMask |= roundIncrement;
-            }
-            zSig0 &= ~ roundMask;
-            return packFloatx80( zSign, zExp, zSig0 );
-        }
-    }
-    if ( roundBits ) float_exception_flags |= float_flag_inexact;
-    zSig0 += roundIncrement;
-    if ( zSig0 < roundIncrement ) {
-        ++zExp;
-        zSig0 = LIT64( 0x8000000000000000 );
-    }
-    roundIncrement = roundMask + 1;
-    if ( roundNearestEven && ( roundBits<<1 == roundIncrement ) ) {
-        roundMask |= roundIncrement;
-    }
-    zSig0 &= ~ roundMask;
-    if ( zSig0 == 0 ) zExp = 0;
-    return packFloatx80( zSign, zExp, zSig0 );
- precision80:
-    increment = ( (sbits64) zSig1 < 0 );
-    if ( ! roundNearestEven ) {
-        if ( roundingMode == float_round_to_zero ) {
-            increment = 0;
-        }
-        else {
-            if ( zSign ) {
-                increment = ( roundingMode == float_round_down ) && zSig1;
-            }
-            else {
-                increment = ( roundingMode == float_round_up ) && zSig1;
-            }
-        }
-    }
-    if ( 0x7FFD <= (bits32) ( zExp - 1 ) ) {
-        if (    ( 0x7FFE < zExp )
-             || (    ( zExp == 0x7FFE )
-                  && ( zSig0 == LIT64( 0xFFFFFFFFFFFFFFFF ) )
-                  && increment
-                )
-           ) {
-            roundMask = 0;
- overflow:
-            float_raise( float_flag_overflow | float_flag_inexact );
-            if (    ( roundingMode == float_round_to_zero )
-                 || ( zSign && ( roundingMode == float_round_up ) )
-                 || ( ! zSign && ( roundingMode == float_round_down ) )
-               ) {
-                return packFloatx80( zSign, 0x7FFE, ~ roundMask );
-            }
-            return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
-        }
-        if ( zExp <= 0 ) {
-            isTiny =
-                   ( float_detect_tininess == float_tininess_before_rounding )
-                || ( zExp < 0 )
-                || ! increment
-                || ( zSig0 < LIT64( 0xFFFFFFFFFFFFFFFF ) );
-            shift64ExtraRightJamming( zSig0, zSig1, 1 - zExp, &zSig0, &zSig1 );
-            zExp = 0;
-            if ( isTiny && zSig1 ) float_raise( float_flag_underflow );
-            if ( zSig1 ) float_exception_flags |= float_flag_inexact;
-            if ( roundNearestEven ) {
-                increment = ( (sbits64) zSig1 < 0 );
-            }
-            else {
-                if ( zSign ) {
-                    increment = ( roundingMode == float_round_down ) && zSig1;
-                }
-                else {
-                    increment = ( roundingMode == float_round_up ) && zSig1;
-                }
-            }
-            if ( increment ) {
-                ++zSig0;
-                zSig0 &=
-                    ~ ( ( (bits64) ( zSig1<<1 ) == 0 ) & roundNearestEven );
-                if ( (sbits64) zSig0 < 0 ) zExp = 1;
-            }
-            return packFloatx80( zSign, zExp, zSig0 );
-        }
-    }
-    if ( zSig1 ) float_exception_flags |= float_flag_inexact;
-    if ( increment ) {
-        ++zSig0;
-        if ( zSig0 == 0 ) {
-            ++zExp;
-            zSig0 = LIT64( 0x8000000000000000 );
-        }
-        else {
-            zSig0 &= ~ ( ( (bits64) ( zSig1<<1 ) == 0 ) & roundNearestEven );
-        }
-    }
-    else {
-        if ( zSig0 == 0 ) zExp = 0;
-    }
-    return packFloatx80( zSign, zExp, zSig0 );
-
-}
-
-/*----------------------------------------------------------------------------
-| Takes an abstract floating-point value having sign `zSign', exponent
-| `zExp', and significand formed by the concatenation of `zSig0' and `zSig1',
-| and returns the proper extended double-precision floating-point value
-| corresponding to the abstract input.  This routine is just like
-| `roundAndPackFloatx80' except that the input significand does not have to be
-| normalized.
-*----------------------------------------------------------------------------*/
-
-static floatx80
- normalizeRoundAndPackFloatx80(
-     int8 roundingPrecision, flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1
- )
-{
-    int8 shiftCount;
-
-    if ( zSig0 == 0 ) {
-        zSig0 = zSig1;
-        zSig1 = 0;
-        zExp -= 64;
-    }
-    shiftCount = countLeadingZeros64( zSig0 );
-    shortShift128Left( zSig0, zSig1, shiftCount, &zSig0, &zSig1 );
-    zExp -= shiftCount;
-    return
-        roundAndPackFloatx80( roundingPrecision, zSign, zExp, zSig0, zSig1 );
-
-}
-
-#endif
-
-#ifdef FLOAT128
-
-/*----------------------------------------------------------------------------
-| Returns the least-significant 64 fraction bits of the quadruple-precision
-| floating-point value `a'.
-*----------------------------------------------------------------------------*/
-
-INLINE bits64 extractFloat128Frac1( float128 a )
-{
-
-    return a.low;
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the most-significant 48 fraction bits of the quadruple-precision
-| floating-point value `a'.
-*----------------------------------------------------------------------------*/
-
-INLINE bits64 extractFloat128Frac0( float128 a )
-{
-
-    return a.high & LIT64( 0x0000FFFFFFFFFFFF );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the exponent bits of the quadruple-precision floating-point value
-| `a'.
-*----------------------------------------------------------------------------*/
-
-INLINE int32 extractFloat128Exp( float128 a )
-{
-
-    return ( a.high>>48 ) & 0x7FFF;
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the sign bit of the quadruple-precision floating-point value `a'.
-*----------------------------------------------------------------------------*/
-
-INLINE flag extractFloat128Sign( float128 a )
-{
-
-    return a.high>>63;
-
-}
-
-/*----------------------------------------------------------------------------
-| Normalizes the subnormal quadruple-precision floating-point value
-| represented by the denormalized significand formed by the concatenation of
-| `aSig0' and `aSig1'.  The normalized exponent is stored at the location
-| pointed to by `zExpPtr'.  The most significant 49 bits of the normalized
-| significand are stored at the location pointed to by `zSig0Ptr', and the
-| least significant 64 bits of the normalized significand are stored at the
-| location pointed to by `zSig1Ptr'.
-*----------------------------------------------------------------------------*/
-
-static void
- normalizeFloat128Subnormal(
-     bits64 aSig0,
-     bits64 aSig1,
-     int32 *zExpPtr,
-     bits64 *zSig0Ptr,
-     bits64 *zSig1Ptr
- )
-{
-    int8 shiftCount;
-
-    if ( aSig0 == 0 ) {
-        shiftCount = countLeadingZeros64( aSig1 ) - 15;
-        if ( shiftCount < 0 ) {
-            *zSig0Ptr = aSig1>>( - shiftCount );
-            *zSig1Ptr = aSig1<<( shiftCount & 63 );
-        }
-        else {
-            *zSig0Ptr = aSig1<<shiftCount;
-            *zSig1Ptr = 0;
-        }
-        *zExpPtr = - shiftCount - 63;
-    }
-    else {
-        shiftCount = countLeadingZeros64( aSig0 ) - 15;
-        shortShift128Left( aSig0, aSig1, shiftCount, zSig0Ptr, zSig1Ptr );
-        *zExpPtr = 1 - shiftCount;
-    }
-
-}
-
-/*----------------------------------------------------------------------------
-| Packs the sign `zSign', the exponent `zExp', and the significand formed
-| by the concatenation of `zSig0' and `zSig1' into a quadruple-precision
-| floating-point value, returning the result.  After being shifted into the
-| proper positions, the three fields `zSign', `zExp', and `zSig0' are simply
-| added together to form the most significant 32 bits of the result.  This
-| means that any integer portion of `zSig0' will be added into the exponent.
-| Since a properly normalized significand will have an integer portion equal
-| to 1, the `zExp' input should be 1 less than the desired result exponent
-| whenever `zSig0' and `zSig1' concatenated form a complete, normalized
-| significand.
-*----------------------------------------------------------------------------*/
-
-INLINE float128
- packFloat128( flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1 )
-{
-    float128 z;
-
-    z.low = zSig1;
-    z.high = ( ( (bits64) zSign )<<63 ) + ( ( (bits64) zExp )<<48 ) + zSig0;
-    return z;
-
-}
-
-/*----------------------------------------------------------------------------
-| Takes an abstract floating-point value having sign `zSign', exponent `zExp',
-| and extended significand formed by the concatenation of `zSig0', `zSig1',
-| and `zSig2', and returns the proper quadruple-precision floating-point value
-| corresponding to the abstract input.  Ordinarily, the abstract value is
-| simply rounded and packed into the quadruple-precision format, with the
-| inexact exception raised if the abstract input cannot be represented
-| exactly.  However, if the abstract value is too large, the overflow and
-| inexact exceptions are raised and an infinity or maximal finite value is
-| returned.  If the abstract value is too small, the input value is rounded to
-| a subnormal number, and the underflow and inexact exceptions are raised if
-| the abstract input cannot be represented exactly as a subnormal quadruple-
-| precision floating-point number.
-|     The input significand must be normalized or smaller.  If the input
-| significand is not normalized, `zExp' must be 0; in that case, the result
-| returned is a subnormal number, and it must not require rounding.  In the
-| usual case that the input significand is normalized, `zExp' must be 1 less
-| than the ``true'' floating-point exponent.  The handling of underflow and
-| overflow follows the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-static float128
- roundAndPackFloat128(
-     flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1, bits64 zSig2 )
-{
-    int8 roundingMode;
-    flag roundNearestEven, increment, isTiny;
-
-    roundingMode = float_rounding_mode;
-    roundNearestEven = ( roundingMode == float_round_nearest_even );
-    increment = ( (sbits64) zSig2 < 0 );
-    if ( ! roundNearestEven ) {
-        if ( roundingMode == float_round_to_zero ) {
-            increment = 0;
-        }
-        else {
-            if ( zSign ) {
-                increment = ( roundingMode == float_round_down ) && zSig2;
-            }
-            else {
-                increment = ( roundingMode == float_round_up ) && zSig2;
-            }
-        }
-    }
-    if ( 0x7FFD <= (bits32) zExp ) {
-        if (    ( 0x7FFD < zExp )
-             || (    ( zExp == 0x7FFD )
-                  && eq128(
-                         LIT64( 0x0001FFFFFFFFFFFF ),
-                         LIT64( 0xFFFFFFFFFFFFFFFF ),
-                         zSig0,
-                         zSig1
-                     )
-                  && increment
-                )
-           ) {
-            float_raise( float_flag_overflow | float_flag_inexact );
-            if (    ( roundingMode == float_round_to_zero )
-                 || ( zSign && ( roundingMode == float_round_up ) )
-                 || ( ! zSign && ( roundingMode == float_round_down ) )
-               ) {
-                return
-                    packFloat128(
-                        zSign,
-                        0x7FFE,
-                        LIT64( 0x0000FFFFFFFFFFFF ),
-                        LIT64( 0xFFFFFFFFFFFFFFFF )
-                    );
-            }
-            return packFloat128( zSign, 0x7FFF, 0, 0 );
-        }
-        if ( zExp < 0 ) {
-            isTiny =
-                   ( float_detect_tininess == float_tininess_before_rounding )
-                || ( zExp < -1 )
-                || ! increment
-                || lt128(
-                       zSig0,
-                       zSig1,
-                       LIT64( 0x0001FFFFFFFFFFFF ),
-                       LIT64( 0xFFFFFFFFFFFFFFFF )
-                   );
-            shift128ExtraRightJamming(
-                zSig0, zSig1, zSig2, - zExp, &zSig0, &zSig1, &zSig2 );
-            zExp = 0;
-            if ( isTiny && zSig2 ) float_raise( float_flag_underflow );
-            if ( roundNearestEven ) {
-                increment = ( (sbits64) zSig2 < 0 );
-            }
-            else {
-                if ( zSign ) {
-                    increment = ( roundingMode == float_round_down ) && zSig2;
-                }
-                else {
-                    increment = ( roundingMode == float_round_up ) && zSig2;
-                }
-            }
-        }
-    }
-    if ( zSig2 ) float_exception_flags |= float_flag_inexact;
-    if ( increment ) {
-        add128( zSig0, zSig1, 0, 1, &zSig0, &zSig1 );
-        zSig1 &= ~ ( ( zSig2 + zSig2 == 0 ) & roundNearestEven );
-    }
-    else {
-        if ( ( zSig0 | zSig1 ) == 0 ) zExp = 0;
-    }
-    return packFloat128( zSign, zExp, zSig0, zSig1 );
-
-}
-
-/*----------------------------------------------------------------------------
-| Takes an abstract floating-point value having sign `zSign', exponent `zExp',
-| and significand formed by the concatenation of `zSig0' and `zSig1', and
-| returns the proper quadruple-precision floating-point value corresponding
-| to the abstract input.  This routine is just like `roundAndPackFloat128'
-| except that the input significand has fewer bits and does not have to be
-| normalized.  In all cases, `zExp' must be 1 less than the ``true'' floating-
-| point exponent.
-*----------------------------------------------------------------------------*/
-
-static float128
- normalizeRoundAndPackFloat128(
-     flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1 )
-{
-    int8 shiftCount;
-    bits64 zSig2;
-
-    if ( zSig0 == 0 ) {
-        zSig0 = zSig1;
-        zSig1 = 0;
-        zExp -= 64;
-    }
-    shiftCount = countLeadingZeros64( zSig0 ) - 15;
-    if ( 0 <= shiftCount ) {
-        zSig2 = 0;
-        shortShift128Left( zSig0, zSig1, shiftCount, &zSig0, &zSig1 );
-    }
-    else {
-        shift128ExtraRightJamming(
-            zSig0, zSig1, 0, - shiftCount, &zSig0, &zSig1, &zSig2 );
-    }
-    zExp -= shiftCount;
-    return roundAndPackFloat128( zSign, zExp, zSig0, zSig1, zSig2 );
-
-}
-
-#endif
-
-#ifdef FLOATX80
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the 32-bit two's complement integer `a'
-| to the extended double-precision floating-point format.  The conversion
-| is performed according to the IEC/IEEE Standard for Binary Floating-Point
-| Arithmetic.
-*----------------------------------------------------------------------------*/
-
-floatx80 int32_to_floatx80( int32 a )
-{
-    flag zSign;
-    uint32 absA;
-    int8 shiftCount;
-    bits64 zSig;
-
-    if ( a == 0 ) return packFloatx80( 0, 0, 0 );
-    zSign = ( a < 0 );
-    absA = zSign ? - a : a;
-    shiftCount = countLeadingZeros32( absA ) + 32;
-    zSig = absA;
-    return packFloatx80( zSign, 0x403E - shiftCount, zSig<<shiftCount );
-
-}
-
-#endif
-
-#ifdef FLOAT128
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the 32-bit two's complement integer `a' to
-| the quadruple-precision floating-point format.  The conversion is performed
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-float128 int32_to_float128( int32 a )
-{
-    flag zSign;
-    uint32 absA;
-    int8 shiftCount;
-    bits64 zSig0;
-
-    if ( a == 0 ) return packFloat128( 0, 0, 0, 0 );
-    zSign = ( a < 0 );
-    absA = zSign ? - a : a;
-    shiftCount = countLeadingZeros32( absA ) + 17;
-    zSig0 = absA;
-    return packFloat128( zSign, 0x402E - shiftCount, zSig0<<shiftCount, 0 );
-
-}
-
-#endif
-
-#ifdef FLOATX80
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the 64-bit two's complement integer `a'
-| to the extended double-precision floating-point format.  The conversion
-| is performed according to the IEC/IEEE Standard for Binary Floating-Point
-| Arithmetic.
-*----------------------------------------------------------------------------*/
-
-floatx80 int64_to_floatx80( int64 a )
-{
-    flag zSign;
-    uint64 absA;
-    int8 shiftCount;
-
-    if ( a == 0 ) return packFloatx80( 0, 0, 0 );
-    zSign = ( a < 0 );
-    absA = zSign ? - a : a;
-    shiftCount = countLeadingZeros64( absA );
-    return packFloatx80( zSign, 0x403E - shiftCount, absA<<shiftCount );
-
-}
-
-#endif
-
-#ifdef FLOAT128
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the 64-bit two's complement integer `a' to
-| the quadruple-precision floating-point format.  The conversion is performed
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-float128 int64_to_float128( int64 a )
-{
-    flag zSign;
-    uint64 absA;
-    int8 shiftCount;
-    int32 zExp;
-    bits64 zSig0, zSig1;
-
-    if ( a == 0 ) return packFloat128( 0, 0, 0, 0 );
-    zSign = ( a < 0 );
-    absA = zSign ? - a : a;
-    shiftCount = countLeadingZeros64( absA ) + 49;
-    zExp = 0x406E - shiftCount;
-    if ( 64 <= shiftCount ) {
-        zSig1 = 0;
-        zSig0 = absA;
-        shiftCount -= 64;
-    }
-    else {
-        zSig1 = absA;
-        zSig0 = 0;
-    }
-    shortShift128Left( zSig0, zSig1, shiftCount, &zSig0, &zSig1 );
-    return packFloat128( zSign, zExp, zSig0, zSig1 );
-
-}
-
-#endif
-
-#ifdef FLOATX80
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the single-precision floating-point value
-| `a' to the extended double-precision floating-point format.  The conversion
-| is performed according to the IEC/IEEE Standard for Binary Floating-Point
-| Arithmetic.
-*----------------------------------------------------------------------------*/
-
-floatx80 float32_to_floatx80( float32 a )
-{
-    flag aSign;
-    int16 aExp;
-    bits32 aSig;
-
-    aSig = extractFloat32Frac( a );
-    aExp = extractFloat32Exp( a );
-    aSign = extractFloat32Sign( a );
-    if ( aExp == 0xFF ) {
-        if ( aSig ) return commonNaNToFloatx80( float32ToCommonNaN( a ) );
-        return packFloatx80( aSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
-    }
-    if ( aExp == 0 ) {
-        if ( aSig == 0 ) return packFloatx80( aSign, 0, 0 );
-        normalizeFloat32Subnormal( aSig, &aExp, &aSig );
-    }
-    aSig |= 0x00800000;
-    return packFloatx80( aSign, aExp + 0x3F80, ( (bits64) aSig )<<40 );
-
-}
-
-#endif
-
-#ifdef FLOAT128
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the single-precision floating-point value
-| `a' to the double-precision floating-point format.  The conversion is
-| performed according to the IEC/IEEE Standard for Binary Floating-Point
-| Arithmetic.
-*----------------------------------------------------------------------------*/
-
-float128 float32_to_float128( float32 a )
-{
-    flag aSign;
-    int16 aExp;
-    bits32 aSig;
-
-    aSig = extractFloat32Frac( a );
-    aExp = extractFloat32Exp( a );
-    aSign = extractFloat32Sign( a );
-    if ( aExp == 0xFF ) {
-        if ( aSig ) return commonNaNToFloat128( float32ToCommonNaN( a ) );
-        return packFloat128( aSign, 0x7FFF, 0, 0 );
-    }
-    if ( aExp == 0 ) {
-        if ( aSig == 0 ) return packFloat128( aSign, 0, 0, 0 );
-        normalizeFloat32Subnormal( aSig, &aExp, &aSig );
-        --aExp;
-    }
-    return packFloat128( aSign, aExp + 0x3F80, ( (bits64) aSig )<<25, 0 );
-
-}
-
-#endif
-
-#ifdef FLOATX80
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the double-precision floating-point value
-| `a' to the extended double-precision floating-point format.  The conversion
-| is performed according to the IEC/IEEE Standard for Binary Floating-Point
-| Arithmetic.
-*----------------------------------------------------------------------------*/
-
-floatx80 float64_to_floatx80( float64 a )
-{
-    flag aSign;
-    int16 aExp;
-    bits64 aSig;
-
-    aSig = extractFloat64Frac( a );
-    aExp = extractFloat64Exp( a );
-    aSign = extractFloat64Sign( a );
-    if ( aExp == 0x7FF ) {
-        if ( aSig ) return commonNaNToFloatx80( float64ToCommonNaN( a ) );
-        return packFloatx80( aSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
-    }
-    if ( aExp == 0 ) {
-        if ( aSig == 0 ) return packFloatx80( aSign, 0, 0 );
-        normalizeFloat64Subnormal( aSig, &aExp, &aSig );
-    }
-    return
-        packFloatx80(
-            aSign, aExp + 0x3C00, ( aSig | LIT64( 0x0010000000000000 ) )<<11 );
-
-}
-
-#endif
-
-#ifdef FLOAT128
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the double-precision floating-point value
-| `a' to the quadruple-precision floating-point format.  The conversion is
-| performed according to the IEC/IEEE Standard for Binary Floating-Point
-| Arithmetic.
-*----------------------------------------------------------------------------*/
-
-float128 float64_to_float128( float64 a )
-{
-    flag aSign;
-    int16 aExp;
-    bits64 aSig, zSig0, zSig1;
-
-    aSig = extractFloat64Frac( a );
-    aExp = extractFloat64Exp( a );
-    aSign = extractFloat64Sign( a );
-    if ( aExp == 0x7FF ) {
-        if ( aSig ) return commonNaNToFloat128( float64ToCommonNaN( a ) );
-        return packFloat128( aSign, 0x7FFF, 0, 0 );
-    }
-    if ( aExp == 0 ) {
-        if ( aSig == 0 ) return packFloat128( aSign, 0, 0, 0 );
-        normalizeFloat64Subnormal( aSig, &aExp, &aSig );
-        --aExp;
-    }
-    shift128Right( aSig, 0, 4, &zSig0, &zSig1 );
-    return packFloat128( aSign, aExp + 0x3C00, zSig0, zSig1 );
-
-}
-
-#endif
-
-#ifdef FLOATX80
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the extended double-precision floating-
-| point value `a' to the 32-bit two's complement integer format.  The
-| conversion is performed according to the IEC/IEEE Standard for Binary
-| Floating-Point Arithmetic---which means in particular that the conversion
-| is rounded according to the current rounding mode.  If `a' is a NaN, the
-| largest positive integer is returned.  Otherwise, if the conversion
-| overflows, the largest integer with the same sign as `a' is returned.
-*----------------------------------------------------------------------------*/
-
-int32 floatx80_to_int32( floatx80 a )
-{
-    flag aSign;
-    int32 aExp, shiftCount;
-    bits64 aSig;
-
-    aSig = extractFloatx80Frac( a );
-    aExp = extractFloatx80Exp( a );
-    aSign = extractFloatx80Sign( a );
-    if ( ( aExp == 0x7FFF ) && (bits64) ( aSig<<1 ) ) aSign = 0;
-    shiftCount = 0x4037 - aExp;
-    if ( shiftCount <= 0 ) shiftCount = 1;
-    shift64RightJamming( aSig, shiftCount, &aSig );
-    return roundAndPackInt32( aSign, aSig );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the extended double-precision floating-
-| point value `a' to the 32-bit two's complement integer format.  The
-| conversion is performed according to the IEC/IEEE Standard for Binary
-| Floating-Point Arithmetic, except that the conversion is always rounded
-| toward zero.  If `a' is a NaN, the largest positive integer is returned.
-| Otherwise, if the conversion overflows, the largest integer with the same
-| sign as `a' is returned.
-*----------------------------------------------------------------------------*/
-
-int32 floatx80_to_int32_round_to_zero( floatx80 a )
-{
-    flag aSign;
-    int32 aExp, shiftCount;
-    bits64 aSig, savedASig;
-    int32 z;
-
-    aSig = extractFloatx80Frac( a );
-    aExp = extractFloatx80Exp( a );
-    aSign = extractFloatx80Sign( a );
-    if ( 0x401E < aExp ) {
-        if ( ( aExp == 0x7FFF ) && (bits64) ( aSig<<1 ) ) aSign = 0;
-        goto invalid;
-    }
-    else if ( aExp < 0x3FFF ) {
-        if ( aExp || aSig ) float_exception_flags |= float_flag_inexact;
-        return 0;
-    }
-    shiftCount = 0x403E - aExp;
-    savedASig = aSig;
-    aSig >>= shiftCount;
-    z = aSig;
-    if ( aSign ) z = - z;
-    if ( ( z < 0 ) ^ aSign ) {
- invalid:
-        float_raise( float_flag_invalid );
-        return aSign ? (sbits32) 0x80000000 : 0x7FFFFFFF;
-    }
-    if ( ( aSig<<shiftCount ) != savedASig ) {
-        float_exception_flags |= float_flag_inexact;
-    }
-    return z;
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the extended double-precision floating-
-| point value `a' to the 64-bit two's complement integer format.  The
-| conversion is performed according to the IEC/IEEE Standard for Binary
-| Floating-Point Arithmetic---which means in particular that the conversion
-| is rounded according to the current rounding mode.  If `a' is a NaN,
-| the largest positive integer is returned.  Otherwise, if the conversion
-| overflows, the largest integer with the same sign as `a' is returned.
-*----------------------------------------------------------------------------*/
-
-int64 floatx80_to_int64( floatx80 a )
-{
-    flag aSign;
-    int32 aExp, shiftCount;
-    bits64 aSig, aSigExtra;
-
-    aSig = extractFloatx80Frac( a );
-    aExp = extractFloatx80Exp( a );
-    aSign = extractFloatx80Sign( a );
-    shiftCount = 0x403E - aExp;
-    if ( shiftCount <= 0 ) {
-        if ( shiftCount ) {
-            float_raise( float_flag_invalid );
-            if (    ! aSign
-                 || (    ( aExp == 0x7FFF )
-                      && ( aSig != LIT64( 0x8000000000000000 ) ) )
-               ) {
-                return LIT64( 0x7FFFFFFFFFFFFFFF );
-            }
-            return (sbits64) LIT64( 0x8000000000000000 );
-        }
-        aSigExtra = 0;
-    }
-    else {
-        shift64ExtraRightJamming( aSig, 0, shiftCount, &aSig, &aSigExtra );
-    }
-    return roundAndPackInt64( aSign, aSig, aSigExtra );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the extended double-precision floating-
-| point value `a' to the 64-bit two's complement integer format.  The
-| conversion is performed according to the IEC/IEEE Standard for Binary
-| Floating-Point Arithmetic, except that the conversion is always rounded
-| toward zero.  If `a' is a NaN, the largest positive integer is returned.
-| Otherwise, if the conversion overflows, the largest integer with the same
-| sign as `a' is returned.
-*----------------------------------------------------------------------------*/
-
-int64 floatx80_to_int64_round_to_zero( floatx80 a )
-{
-    flag aSign;
-    int32 aExp, shiftCount;
-    bits64 aSig;
-    int64 z;
-
-    aSig = extractFloatx80Frac( a );
-    aExp = extractFloatx80Exp( a );
-    aSign = extractFloatx80Sign( a );
-    shiftCount = aExp - 0x403E;
-    if ( 0 <= shiftCount ) {
-        aSig &= LIT64( 0x7FFFFFFFFFFFFFFF );
-        if ( ( a.high != 0xC03E ) || aSig ) {
-            float_raise( float_flag_invalid );
-            if ( ! aSign || ( ( aExp == 0x7FFF ) && aSig ) ) {
-                return LIT64( 0x7FFFFFFFFFFFFFFF );
-            }
-        }
-        return (sbits64) LIT64( 0x8000000000000000 );
-    }
-    else if ( aExp < 0x3FFF ) {
-        if ( aExp | aSig ) float_exception_flags |= float_flag_inexact;
-        return 0;
-    }
-    z = aSig>>( - shiftCount );
-    if ( (bits64) ( aSig<<( shiftCount & 63 ) ) ) {
-        float_exception_flags |= float_flag_inexact;
-    }
-    if ( aSign ) z = - z;
-    return z;
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the extended double-precision floating-
-| point value `a' to the single-precision floating-point format.  The
-| conversion is performed according to the IEC/IEEE Standard for Binary
-| Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-float32 floatx80_to_float32( floatx80 a )
-{
-    flag aSign;
-    int32 aExp;
-    bits64 aSig;
-
-    aSig = extractFloatx80Frac( a );
-    aExp = extractFloatx80Exp( a );
-    aSign = extractFloatx80Sign( a );
-    if ( aExp == 0x7FFF ) {
-        if ( (bits64) ( aSig<<1 ) ) {
-            return commonNaNToFloat32( floatx80ToCommonNaN( a ) );
-        }
-        return packFloat32( aSign, 0xFF, 0 );
-    }
-    shift64RightJamming( aSig, 33, &aSig );
-    if ( aExp || aSig ) aExp -= 0x3F81;
-    return roundAndPackFloat32( aSign, aExp, aSig );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the extended double-precision floating-
-| point value `a' to the double-precision floating-point format.  The
-| conversion is performed according to the IEC/IEEE Standard for Binary
-| Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-float64 floatx80_to_float64( floatx80 a )
-{
-    flag aSign;
-    int32 aExp;
-    bits64 aSig, zSig;
-
-    aSig = extractFloatx80Frac( a );
-    aExp = extractFloatx80Exp( a );
-    aSign = extractFloatx80Sign( a );
-    if ( aExp == 0x7FFF ) {
-        if ( (bits64) ( aSig<<1 ) ) {
-            return commonNaNToFloat64( floatx80ToCommonNaN( a ) );
-        }
-        return packFloat64( aSign, 0x7FF, 0 );
-    }
-    shift64RightJamming( aSig, 1, &zSig );
-    if ( aExp || aSig ) aExp -= 0x3C01;
-    return roundAndPackFloat64( aSign, aExp, zSig );
-
-}
-
-#ifdef FLOAT128
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the extended double-precision floating-
-| point value `a' to the quadruple-precision floating-point format.  The
-| conversion is performed according to the IEC/IEEE Standard for Binary
-| Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-float128 floatx80_to_float128( floatx80 a )
-{
-    flag aSign;
-    int16 aExp;
-    bits64 aSig, zSig0, zSig1;
-
-    aSig = extractFloatx80Frac( a );
-    aExp = extractFloatx80Exp( a );
-    aSign = extractFloatx80Sign( a );
-    if ( ( aExp == 0x7FFF ) && (bits64) ( aSig<<1 ) ) {
-        return commonNaNToFloat128( floatx80ToCommonNaN( a ) );
-    }
-    shift128Right( aSig<<1, 0, 16, &zSig0, &zSig1 );
-    return packFloat128( aSign, aExp, zSig0, zSig1 );
-
-}
-
-#endif
-
-/*----------------------------------------------------------------------------
-| Rounds the extended double-precision floating-point value `a' to an integer,
-| and returns the result as an extended quadruple-precision floating-point
-| value.  The operation is performed according to the IEC/IEEE Standard for
-| Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-floatx80 floatx80_round_to_int( floatx80 a )
-{
-    flag aSign;
-    int32 aExp;
-    bits64 lastBitMask, roundBitsMask;
-    int8 roundingMode;
-    floatx80 z;
-
-    aExp = extractFloatx80Exp( a );
-    if ( 0x403E <= aExp ) {
-        if ( ( aExp == 0x7FFF ) && (bits64) ( extractFloatx80Frac( a )<<1 ) ) {
-            return propagateFloatx80NaN( a, a );
-        }
-        return a;
-    }
-    if ( aExp < 0x3FFF ) {
-        if (    ( aExp == 0 )
-             && ( (bits64) ( extractFloatx80Frac( a )<<1 ) == 0 ) ) {
-            return a;
-        }
-        float_exception_flags |= float_flag_inexact;
-        aSign = extractFloatx80Sign( a );
-        switch ( float_rounding_mode ) {
-         case float_round_nearest_even:
-            if ( ( aExp == 0x3FFE ) && (bits64) ( extractFloatx80Frac( a )<<1 )
-               ) {
-                return
-                    packFloatx80( aSign, 0x3FFF, LIT64( 0x8000000000000000 ) );
-            }
-            break;
-         case float_round_down:
-            return
-                  aSign ?
-                      packFloatx80( 1, 0x3FFF, LIT64( 0x8000000000000000 ) )
-                : packFloatx80( 0, 0, 0 );
-         case float_round_up:
-            return
-                  aSign ? packFloatx80( 1, 0, 0 )
-                : packFloatx80( 0, 0x3FFF, LIT64( 0x8000000000000000 ) );
-        }
-        return packFloatx80( aSign, 0, 0 );
-    }
-    lastBitMask = 1;
-    lastBitMask <<= 0x403E - aExp;
-    roundBitsMask = lastBitMask - 1;
-    z = a;
-    roundingMode = float_rounding_mode;
-    if ( roundingMode == float_round_nearest_even ) {
-        z.low += lastBitMask>>1;
-        if ( ( z.low & roundBitsMask ) == 0 ) z.low &= ~ lastBitMask;
-    }
-    else if ( roundingMode != float_round_to_zero ) {
-        if ( extractFloatx80Sign( z ) ^ ( roundingMode == float_round_up ) ) {
-            z.low += roundBitsMask;
-        }
-    }
-    z.low &= ~ roundBitsMask;
-    if ( z.low == 0 ) {
-        ++z.high;
-        z.low = LIT64( 0x8000000000000000 );
-    }
-    if ( z.low != a.low ) float_exception_flags |= float_flag_inexact;
-    return z;
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of adding the absolute values of the extended double-
-| precision floating-point values `a' and `b'.  If `zSign' is 1, the sum is
-| negated before being returned.  `zSign' is ignored if the result is a NaN.
-| The addition is performed according to the IEC/IEEE Standard for Binary
-| Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-static floatx80 addFloatx80Sigs( floatx80 a, floatx80 b, flag zSign )
-{
-    int32 aExp, bExp, zExp;
-    bits64 aSig, bSig, zSig0, zSig1;
-    int32 expDiff;
-
-    aSig = extractFloatx80Frac( a );
-    aExp = extractFloatx80Exp( a );
-    bSig = extractFloatx80Frac( b );
-    bExp = extractFloatx80Exp( b );
-    expDiff = aExp - bExp;
-    if ( 0 < expDiff ) {
-        if ( aExp == 0x7FFF ) {
-            if ( (bits64) ( aSig<<1 ) ) return propagateFloatx80NaN( a, b );
-            return a;
-        }
-        if ( bExp == 0 ) --expDiff;
-        shift64ExtraRightJamming( bSig, 0, expDiff, &bSig, &zSig1 );
-        zExp = aExp;
-    }
-    else if ( expDiff < 0 ) {
-        if ( bExp == 0x7FFF ) {
-            if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );
-            return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
-        }
-        if ( aExp == 0 ) ++expDiff;
-        shift64ExtraRightJamming( aSig, 0, - expDiff, &aSig, &zSig1 );
-        zExp = bExp;
-    }
-    else {
-        if ( aExp == 0x7FFF ) {
-            if ( (bits64) ( ( aSig | bSig )<<1 ) ) {
-                return propagateFloatx80NaN( a, b );
-            }
-            return a;
-        }
-        zSig1 = 0;
-        zSig0 = aSig + bSig;
-        if ( aExp == 0 ) {
-            normalizeFloatx80Subnormal( zSig0, &zExp, &zSig0 );
-            goto roundAndPack;
-        }
-        zExp = aExp;
-        goto shiftRight1;
-    }
-    zSig0 = aSig + bSig;
-    if ( (sbits64) zSig0 < 0 ) goto roundAndPack;
- shiftRight1:
-    shift64ExtraRightJamming( zSig0, zSig1, 1, &zSig0, &zSig1 );
-    zSig0 |= LIT64( 0x8000000000000000 );
-    ++zExp;
- roundAndPack:
-    return
-        roundAndPackFloatx80(
-            floatx80_rounding_precision, zSign, zExp, zSig0, zSig1 );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of subtracting the absolute values of the extended
-| double-precision floating-point values `a' and `b'.  If `zSign' is 1, the
-| difference is negated before being returned.  `zSign' is ignored if the
-| result is a NaN.  The subtraction is performed according to the IEC/IEEE
-| Standard for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-static floatx80 subFloatx80Sigs( floatx80 a, floatx80 b, flag zSign )
-{
-    int32 aExp, bExp, zExp;
-    bits64 aSig, bSig, zSig0, zSig1;
-    int32 expDiff;
-    floatx80 z;
-
-    aSig = extractFloatx80Frac( a );
-    aExp = extractFloatx80Exp( a );
-    bSig = extractFloatx80Frac( b );
-    bExp = extractFloatx80Exp( b );
-    expDiff = aExp - bExp;
-    if ( 0 < expDiff ) goto aExpBigger;
-    if ( expDiff < 0 ) goto bExpBigger;
-    if ( aExp == 0x7FFF ) {
-        if ( (bits64) ( ( aSig | bSig )<<1 ) ) {
-            return propagateFloatx80NaN( a, b );
-        }
-        float_raise( float_flag_invalid );
-        z.low = floatx80_default_nan_low;
-        z.high = floatx80_default_nan_high;
-        return z;
-    }
-    if ( aExp == 0 ) {
-        aExp = 1;
-        bExp = 1;
-    }
-    zSig1 = 0;
-    if ( bSig < aSig ) goto aBigger;
-    if ( aSig < bSig ) goto bBigger;
-    return packFloatx80( float_rounding_mode == float_round_down, 0, 0 );
- bExpBigger:
-    if ( bExp == 0x7FFF ) {
-        if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );
-        return packFloatx80( zSign ^ 1, 0x7FFF, LIT64( 0x8000000000000000 ) );
-    }
-    if ( aExp == 0 ) ++expDiff;
-    shift128RightJamming( aSig, 0, - expDiff, &aSig, &zSig1 );
- bBigger:
-    sub128( bSig, 0, aSig, zSig1, &zSig0, &zSig1 );
-    zExp = bExp;
-    zSign ^= 1;
-    goto normalizeRoundAndPack;
- aExpBigger:
-    if ( aExp == 0x7FFF ) {
-        if ( (bits64) ( aSig<<1 ) ) return propagateFloatx80NaN( a, b );
-        return a;
-    }
-    if ( bExp == 0 ) --expDiff;
-    shift128RightJamming( bSig, 0, expDiff, &bSig, &zSig1 );
- aBigger:
-    sub128( aSig, 0, bSig, zSig1, &zSig0, &zSig1 );
-    zExp = aExp;
- normalizeRoundAndPack:
-    return
-        normalizeRoundAndPackFloatx80(
-            floatx80_rounding_precision, zSign, zExp, zSig0, zSig1 );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of adding the extended double-precision floating-point
-| values `a' and `b'.  The operation is performed according to the IEC/IEEE
-| Standard for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-floatx80 floatx80_add( floatx80 a, floatx80 b )
-{
-    flag aSign, bSign;
-
-    aSign = extractFloatx80Sign( a );
-    bSign = extractFloatx80Sign( b );
-    if ( aSign == bSign ) {
-        return addFloatx80Sigs( a, b, aSign );
-    }
-    else {
-        return subFloatx80Sigs( a, b, aSign );
-    }
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of subtracting the extended double-precision floating-
-| point values `a' and `b'.  The operation is performed according to the
-| IEC/IEEE Standard for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-floatx80 floatx80_sub( floatx80 a, floatx80 b )
-{
-    flag aSign, bSign;
-
-    aSign = extractFloatx80Sign( a );
-    bSign = extractFloatx80Sign( b );
-    if ( aSign == bSign ) {
-        return subFloatx80Sigs( a, b, aSign );
-    }
-    else {
-        return addFloatx80Sigs( a, b, aSign );
-    }
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of multiplying the extended double-precision floating-
-| point values `a' and `b'.  The operation is performed according to the
-| IEC/IEEE Standard for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-floatx80 floatx80_mul( floatx80 a, floatx80 b )
-{
-    flag aSign, bSign, zSign;
-    int32 aExp, bExp, zExp;
-    bits64 aSig, bSig, zSig0, zSig1;
-    floatx80 z;
-
-    aSig = extractFloatx80Frac( a );
-    aExp = extractFloatx80Exp( a );
-    aSign = extractFloatx80Sign( a );
-    bSig = extractFloatx80Frac( b );
-    bExp = extractFloatx80Exp( b );
-    bSign = extractFloatx80Sign( b );
-    zSign = aSign ^ bSign;
-    if ( aExp == 0x7FFF ) {
-        if (    (bits64) ( aSig<<1 )
-             || ( ( bExp == 0x7FFF ) && (bits64) ( bSig<<1 ) ) ) {
-            return propagateFloatx80NaN( a, b );
-        }
-        if ( ( bExp | bSig ) == 0 ) goto invalid;
-        return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
-    }
-    if ( bExp == 0x7FFF ) {
-        if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );
-        if ( ( aExp | aSig ) == 0 ) {
- invalid:
-            float_raise( float_flag_invalid );
-            z.low = floatx80_default_nan_low;
-            z.high = floatx80_default_nan_high;
-            return z;
-        }
-        return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
-    }
-    if ( aExp == 0 ) {
-        if ( aSig == 0 ) return packFloatx80( zSign, 0, 0 );
-        normalizeFloatx80Subnormal( aSig, &aExp, &aSig );
-    }
-    if ( bExp == 0 ) {
-        if ( bSig == 0 ) return packFloatx80( zSign, 0, 0 );
-        normalizeFloatx80Subnormal( bSig, &bExp, &bSig );
-    }
-    zExp = aExp + bExp - 0x3FFE;
-    mul64To128( aSig, bSig, &zSig0, &zSig1 );
-    if ( 0 < (sbits64) zSig0 ) {
-        shortShift128Left( zSig0, zSig1, 1, &zSig0, &zSig1 );
-        --zExp;
-    }
-    return
-        roundAndPackFloatx80(
-            floatx80_rounding_precision, zSign, zExp, zSig0, zSig1 );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of dividing the extended double-precision floating-point
-| value `a' by the corresponding value `b'.  The operation is performed
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-floatx80 floatx80_div( floatx80 a, floatx80 b )
-{
-    flag aSign, bSign, zSign;
-    int32 aExp, bExp, zExp;
-    bits64 aSig, bSig, zSig0, zSig1;
-    bits64 rem0, rem1, rem2, term0, term1, term2;
-    floatx80 z;
-
-    aSig = extractFloatx80Frac( a );
-    aExp = extractFloatx80Exp( a );
-    aSign = extractFloatx80Sign( a );
-    bSig = extractFloatx80Frac( b );
-    bExp = extractFloatx80Exp( b );
-    bSign = extractFloatx80Sign( b );
-    zSign = aSign ^ bSign;
-    if ( aExp == 0x7FFF ) {
-        if ( (bits64) ( aSig<<1 ) ) return propagateFloatx80NaN( a, b );
-        if ( bExp == 0x7FFF ) {
-            if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );
-            goto invalid;
-        }
-        return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
-    }
-    if ( bExp == 0x7FFF ) {
-        if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );
-        return packFloatx80( zSign, 0, 0 );
-    }
-    if ( bExp == 0 ) {
-        if ( bSig == 0 ) {
-            if ( ( aExp | aSig ) == 0 ) {
- invalid:
-                float_raise( float_flag_invalid );
-                z.low = floatx80_default_nan_low;
-                z.high = floatx80_default_nan_high;
-                return z;
-            }
-            float_raise( float_flag_divbyzero );
-            return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
-        }
-        normalizeFloatx80Subnormal( bSig, &bExp, &bSig );
-    }
-    if ( aExp == 0 ) {
-        if ( aSig == 0 ) return packFloatx80( zSign, 0, 0 );
-        normalizeFloatx80Subnormal( aSig, &aExp, &aSig );
-    }
-    zExp = aExp - bExp + 0x3FFE;
-    rem1 = 0;
-    if ( bSig <= aSig ) {
-        shift128Right( aSig, 0, 1, &aSig, &rem1 );
-        ++zExp;
-    }
-    zSig0 = estimateDiv128To64( aSig, rem1, bSig );
-    mul64To128( bSig, zSig0, &term0, &term1 );
-    sub128( aSig, rem1, term0, term1, &rem0, &rem1 );
-    while ( (sbits64) rem0 < 0 ) {
-        --zSig0;
-        add128( rem0, rem1, 0, bSig, &rem0, &rem1 );
-    }
-    zSig1 = estimateDiv128To64( rem1, 0, bSig );
-    if ( (bits64) ( zSig1<<1 ) <= 8 ) {
-        mul64To128( bSig, zSig1, &term1, &term2 );
-        sub128( rem1, 0, term1, term2, &rem1, &rem2 );
-        while ( (sbits64) rem1 < 0 ) {
-            --zSig1;
-            add128( rem1, rem2, 0, bSig, &rem1, &rem2 );
-        }
-        zSig1 |= ( ( rem1 | rem2 ) != 0 );
-    }
-    return
-        roundAndPackFloatx80(
-            floatx80_rounding_precision, zSign, zExp, zSig0, zSig1 );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the remainder of the extended double-precision floating-point value
-| `a' with respect to the corresponding value `b'.  The operation is performed
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-floatx80 floatx80_rem( floatx80 a, floatx80 b )
-{
-    flag aSign, bSign, zSign;
-    int32 aExp, bExp, expDiff;
-    bits64 aSig0, aSig1, bSig;
-    bits64 q, term0, term1, alternateASig0, alternateASig1;
-    floatx80 z;
-
-    aSig0 = extractFloatx80Frac( a );
-    aExp = extractFloatx80Exp( a );
-    aSign = extractFloatx80Sign( a );
-    bSig = extractFloatx80Frac( b );
-    bExp = extractFloatx80Exp( b );
-    bSign = extractFloatx80Sign( b );
-    if ( aExp == 0x7FFF ) {
-        if (    (bits64) ( aSig0<<1 )
-             || ( ( bExp == 0x7FFF ) && (bits64) ( bSig<<1 ) ) ) {
-            return propagateFloatx80NaN( a, b );
-        }
-        goto invalid;
-    }
-    if ( bExp == 0x7FFF ) {
-        if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );
-        return a;
-    }
-    if ( bExp == 0 ) {
-        if ( bSig == 0 ) {
- invalid:
-            float_raise( float_flag_invalid );
-            z.low = floatx80_default_nan_low;
-            z.high = floatx80_default_nan_high;
-            return z;
-        }
-        normalizeFloatx80Subnormal( bSig, &bExp, &bSig );
-    }
-    if ( aExp == 0 ) {
-        if ( (bits64) ( aSig0<<1 ) == 0 ) return a;
-        normalizeFloatx80Subnormal( aSig0, &aExp, &aSig0 );
-    }
-    bSig |= LIT64( 0x8000000000000000 );
-    zSign = aSign;
-    expDiff = aExp - bExp;
-    aSig1 = 0;
-    if ( expDiff < 0 ) {
-        if ( expDiff < -1 ) return a;
-        shift128Right( aSig0, 0, 1, &aSig0, &aSig1 );
-        expDiff = 0;
-    }
-    q = ( bSig <= aSig0 );
-    if ( q ) aSig0 -= bSig;
-    expDiff -= 64;
-    while ( 0 < expDiff ) {
-        q = estimateDiv128To64( aSig0, aSig1, bSig );
-        q = ( 2 < q ) ? q - 2 : 0;
-        mul64To128( bSig, q, &term0, &term1 );
-        sub128( aSig0, aSig1, term0, term1, &aSig0, &aSig1 );
-        shortShift128Left( aSig0, aSig1, 62, &aSig0, &aSig1 );
-        expDiff -= 62;
-    }
-    expDiff += 64;
-    if ( 0 < expDiff ) {
-        q = estimateDiv128To64( aSig0, aSig1, bSig );
-        q = ( 2 < q ) ? q - 2 : 0;
-        q >>= 64 - expDiff;
-        mul64To128( bSig, q<<( 64 - expDiff ), &term0, &term1 );
-        sub128( aSig0, aSig1, term0, term1, &aSig0, &aSig1 );
-        shortShift128Left( 0, bSig, 64 - expDiff, &term0, &term1 );
-        while ( le128( term0, term1, aSig0, aSig1 ) ) {
-            ++q;
-            sub128( aSig0, aSig1, term0, term1, &aSig0, &aSig1 );
-        }
-    }
-    else {
-        term1 = 0;
-        term0 = bSig;
-    }
-    sub128( term0, term1, aSig0, aSig1, &alternateASig0, &alternateASig1 );
-    if (    lt128( alternateASig0, alternateASig1, aSig0, aSig1 )
-         || (    eq128( alternateASig0, alternateASig1, aSig0, aSig1 )
-              && ( q & 1 ) )
-       ) {
-        aSig0 = alternateASig0;
-        aSig1 = alternateASig1;
-        zSign = ! zSign;
-    }
-    return
-        normalizeRoundAndPackFloatx80(
-            80, zSign, bExp + expDiff, aSig0, aSig1 );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the square root of the extended double-precision floating-point
-| value `a'.  The operation is performed according to the IEC/IEEE Standard
-| for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-floatx80 floatx80_sqrt( floatx80 a )
-{
-    flag aSign;
-    int32 aExp, zExp;
-    bits64 aSig0, aSig1, zSig0, zSig1, doubleZSig0;
-    bits64 rem0, rem1, rem2, rem3, term0, term1, term2, term3;
-    floatx80 z;
-
-    aSig0 = extractFloatx80Frac( a );
-    aExp = extractFloatx80Exp( a );
-    aSign = extractFloatx80Sign( a );
-    if ( aExp == 0x7FFF ) {
-        if ( (bits64) ( aSig0<<1 ) ) return propagateFloatx80NaN( a, a );
-        if ( ! aSign ) return a;
-        goto invalid;
-    }
-    if ( aSign ) {
-        if ( ( aExp | aSig0 ) == 0 ) return a;
- invalid:
-        float_raise( float_flag_invalid );
-        z.low = floatx80_default_nan_low;
-        z.high = floatx80_default_nan_high;
-        return z;
-    }
-    if ( aExp == 0 ) {
-        if ( aSig0 == 0 ) return packFloatx80( 0, 0, 0 );
-        normalizeFloatx80Subnormal( aSig0, &aExp, &aSig0 );
-    }
-    zExp = ( ( aExp - 0x3FFF )>>1 ) + 0x3FFF;
-    zSig0 = estimateSqrt32( aExp, aSig0>>32 );
-    shift128Right( aSig0, 0, 2 + ( aExp & 1 ), &aSig0, &aSig1 );
-    zSig0 = estimateDiv128To64( aSig0, aSig1, zSig0<<32 ) + ( zSig0<<30 );
-    doubleZSig0 = zSig0<<1;
-    mul64To128( zSig0, zSig0, &term0, &term1 );
-    sub128( aSig0, aSig1, term0, term1, &rem0, &rem1 );
-    while ( (sbits64) rem0 < 0 ) {
-        --zSig0;
-        doubleZSig0 -= 2;
-        add128( rem0, rem1, zSig0>>63, doubleZSig0 | 1, &rem0, &rem1 );
-    }
-    zSig1 = estimateDiv128To64( rem1, 0, doubleZSig0 );
-    if ( ( zSig1 & LIT64( 0x3FFFFFFFFFFFFFFF ) ) <= 5 ) {
-        if ( zSig1 == 0 ) zSig1 = 1;
-        mul64To128( doubleZSig0, zSig1, &term1, &term2 );
-        sub128( rem1, 0, term1, term2, &rem1, &rem2 );
-        mul64To128( zSig1, zSig1, &term2, &term3 );
-        sub192( rem1, rem2, 0, 0, term2, term3, &rem1, &rem2, &rem3 );
-        while ( (sbits64) rem1 < 0 ) {
-            --zSig1;
-            shortShift128Left( 0, zSig1, 1, &term2, &term3 );
-            term3 |= 1;
-            term2 |= doubleZSig0;
-            add192( rem1, rem2, rem3, 0, term2, term3, &rem1, &rem2, &rem3 );
-        }
-        zSig1 |= ( ( rem1 | rem2 | rem3 ) != 0 );
-    }
-    shortShift128Left( 0, zSig1, 1, &zSig0, &zSig1 );
-    zSig0 |= doubleZSig0;
-    return
-        roundAndPackFloatx80(
-            floatx80_rounding_precision, 0, zExp, zSig0, zSig1 );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the extended double-precision floating-point value `a' is
-| equal to the corresponding value `b', and 0 otherwise.  The comparison is
-| performed according to the IEC/IEEE Standard for Binary Floating-Point
-| Arithmetic.
-*----------------------------------------------------------------------------*/
-
-flag floatx80_eq( floatx80 a, floatx80 b )
-{
-
-    if (    (    ( extractFloatx80Exp( a ) == 0x7FFF )
-              && (bits64) ( extractFloatx80Frac( a )<<1 ) )
-         || (    ( extractFloatx80Exp( b ) == 0x7FFF )
-              && (bits64) ( extractFloatx80Frac( b )<<1 ) )
-       ) {
-        if (    floatx80_is_signaling_nan( a )
-             || floatx80_is_signaling_nan( b ) ) {
-            float_raise( float_flag_invalid );
-        }
-        return 0;
-    }
-    return
-           ( a.low == b.low )
-        && (    ( a.high == b.high )
-             || (    ( a.low == 0 )
-                  && ( (bits16) ( ( a.high | b.high )<<1 ) == 0 ) )
-           );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the extended double-precision floating-point value `a' is
-| less than or equal to the corresponding value `b', and 0 otherwise.  The
-| comparison is performed according to the IEC/IEEE Standard for Binary
-| Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-flag floatx80_le( floatx80 a, floatx80 b )
-{
-    flag aSign, bSign;
-
-    if (    (    ( extractFloatx80Exp( a ) == 0x7FFF )
-              && (bits64) ( extractFloatx80Frac( a )<<1 ) )
-         || (    ( extractFloatx80Exp( b ) == 0x7FFF )
-              && (bits64) ( extractFloatx80Frac( b )<<1 ) )
-       ) {
-        float_raise( float_flag_invalid );
-        return 0;
-    }
-    aSign = extractFloatx80Sign( a );
-    bSign = extractFloatx80Sign( b );
-    if ( aSign != bSign ) {
-        return
-               aSign
-            || (    ( ( (bits16) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )
-                 == 0 );
-    }
-    return
-          aSign ? le128( b.high, b.low, a.high, a.low )
-        : le128( a.high, a.low, b.high, b.low );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the extended double-precision floating-point value `a' is
-| less than the corresponding value `b', and 0 otherwise.  The comparison
-| is performed according to the IEC/IEEE Standard for Binary Floating-Point
-| Arithmetic.
-*----------------------------------------------------------------------------*/
-
-flag floatx80_lt( floatx80 a, floatx80 b )
-{
-    flag aSign, bSign;
-
-    if (    (    ( extractFloatx80Exp( a ) == 0x7FFF )
-              && (bits64) ( extractFloatx80Frac( a )<<1 ) )
-         || (    ( extractFloatx80Exp( b ) == 0x7FFF )
-              && (bits64) ( extractFloatx80Frac( b )<<1 ) )
-       ) {
-        float_raise( float_flag_invalid );
-        return 0;
-    }
-    aSign = extractFloatx80Sign( a );
-    bSign = extractFloatx80Sign( b );
-    if ( aSign != bSign ) {
-        return
-               aSign
-            && (    ( ( (bits16) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )
-                 != 0 );
-    }
-    return
-          aSign ? lt128( b.high, b.low, a.high, a.low )
-        : lt128( a.high, a.low, b.high, b.low );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the extended double-precision floating-point value `a' is equal
-| to the corresponding value `b', and 0 otherwise.  The invalid exception is
-| raised if either operand is a NaN.  Otherwise, the comparison is performed
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-flag floatx80_eq_signaling( floatx80 a, floatx80 b )
-{
-
-    if (    (    ( extractFloatx80Exp( a ) == 0x7FFF )
-              && (bits64) ( extractFloatx80Frac( a )<<1 ) )
-         || (    ( extractFloatx80Exp( b ) == 0x7FFF )
-              && (bits64) ( extractFloatx80Frac( b )<<1 ) )
-       ) {
-        float_raise( float_flag_invalid );
-        return 0;
-    }
-    return
-           ( a.low == b.low )
-        && (    ( a.high == b.high )
-             || (    ( a.low == 0 )
-                  && ( (bits16) ( ( a.high | b.high )<<1 ) == 0 ) )
-           );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the extended double-precision floating-point value `a' is less
-| than or equal to the corresponding value `b', and 0 otherwise.  Quiet NaNs
-| do not cause an exception.  Otherwise, the comparison is performed according
-| to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-flag floatx80_le_quiet( floatx80 a, floatx80 b )
-{
-    flag aSign, bSign;
-
-    if (    (    ( extractFloatx80Exp( a ) == 0x7FFF )
-              && (bits64) ( extractFloatx80Frac( a )<<1 ) )
-         || (    ( extractFloatx80Exp( b ) == 0x7FFF )
-              && (bits64) ( extractFloatx80Frac( b )<<1 ) )
-       ) {
-        if (    floatx80_is_signaling_nan( a )
-             || floatx80_is_signaling_nan( b ) ) {
-            float_raise( float_flag_invalid );
-        }
-        return 0;
-    }
-    aSign = extractFloatx80Sign( a );
-    bSign = extractFloatx80Sign( b );
-    if ( aSign != bSign ) {
-        return
-               aSign
-            || (    ( ( (bits16) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )
-                 == 0 );
-    }
-    return
-          aSign ? le128( b.high, b.low, a.high, a.low )
-        : le128( a.high, a.low, b.high, b.low );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the extended double-precision floating-point value `a' is less
-| than the corresponding value `b', and 0 otherwise.  Quiet NaNs do not cause
-| an exception.  Otherwise, the comparison is performed according to the
-| IEC/IEEE Standard for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-flag floatx80_lt_quiet( floatx80 a, floatx80 b )
-{
-    flag aSign, bSign;
-
-    if (    (    ( extractFloatx80Exp( a ) == 0x7FFF )
-              && (bits64) ( extractFloatx80Frac( a )<<1 ) )
-         || (    ( extractFloatx80Exp( b ) == 0x7FFF )
-              && (bits64) ( extractFloatx80Frac( b )<<1 ) )
-       ) {
-        if (    floatx80_is_signaling_nan( a )
-             || floatx80_is_signaling_nan( b ) ) {
-            float_raise( float_flag_invalid );
-        }
-        return 0;
-    }
-    aSign = extractFloatx80Sign( a );
-    bSign = extractFloatx80Sign( b );
-    if ( aSign != bSign ) {
-        return
-               aSign
-            && (    ( ( (bits16) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )
-                 != 0 );
-    }
-    return
-          aSign ? lt128( b.high, b.low, a.high, a.low )
-        : lt128( a.high, a.low, b.high, b.low );
-
-}
-
-#endif
-
-#ifdef FLOAT128
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the quadruple-precision floating-point
-| value `a' to the 32-bit two's complement integer format.  The conversion
-| is performed according to the IEC/IEEE Standard for Binary Floating-Point
-| Arithmetic---which means in particular that the conversion is rounded
-| according to the current rounding mode.  If `a' is a NaN, the largest
-| positive integer is returned.  Otherwise, if the conversion overflows, the
-| largest integer with the same sign as `a' is returned.
-*----------------------------------------------------------------------------*/
-
-int32 float128_to_int32( float128 a )
-{
-    flag aSign;
-    int32 aExp, shiftCount;
-    bits64 aSig0, aSig1;
-
-    aSig1 = extractFloat128Frac1( a );
-    aSig0 = extractFloat128Frac0( a );
-    aExp = extractFloat128Exp( a );
-    aSign = extractFloat128Sign( a );
-    if ( ( aExp == 0x7FFF ) && ( aSig0 | aSig1 ) ) aSign = 0;
-    if ( aExp ) aSig0 |= LIT64( 0x0001000000000000 );
-    aSig0 |= ( aSig1 != 0 );
-    shiftCount = 0x4028 - aExp;
-    if ( 0 < shiftCount ) shift64RightJamming( aSig0, shiftCount, &aSig0 );
-    return roundAndPackInt32( aSign, aSig0 );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the quadruple-precision floating-point
-| value `a' to the 32-bit two's complement integer format.  The conversion
-| is performed according to the IEC/IEEE Standard for Binary Floating-Point
-| Arithmetic, except that the conversion is always rounded toward zero.  If
-| `a' is a NaN, the largest positive integer is returned.  Otherwise, if the
-| conversion overflows, the largest integer with the same sign as `a' is
-| returned.
-*----------------------------------------------------------------------------*/
-
-int32 float128_to_int32_round_to_zero( float128 a )
-{
-    flag aSign;
-    int32 aExp, shiftCount;
-    bits64 aSig0, aSig1, savedASig;
-    int32 z;
-
-    aSig1 = extractFloat128Frac1( a );
-    aSig0 = extractFloat128Frac0( a );
-    aExp = extractFloat128Exp( a );
-    aSign = extractFloat128Sign( a );
-    aSig0 |= ( aSig1 != 0 );
-    if ( 0x401E < aExp ) {
-        if ( ( aExp == 0x7FFF ) && aSig0 ) aSign = 0;
-        goto invalid;
-    }
-    else if ( aExp < 0x3FFF ) {
-        if ( aExp || aSig0 ) float_exception_flags |= float_flag_inexact;
-        return 0;
-    }
-    aSig0 |= LIT64( 0x0001000000000000 );
-    shiftCount = 0x402F - aExp;
-    savedASig = aSig0;
-    aSig0 >>= shiftCount;
-    z = aSig0;
-    if ( aSign ) z = - z;
-    if ( ( z < 0 ) ^ aSign ) {
- invalid:
-        float_raise( float_flag_invalid );
-        return aSign ? (sbits32) 0x80000000 : 0x7FFFFFFF;
-    }
-    if ( ( aSig0<<shiftCount ) != savedASig ) {
-        float_exception_flags |= float_flag_inexact;
-    }
-    return z;
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the quadruple-precision floating-point
-| value `a' to the 64-bit two's complement integer format.  The conversion
-| is performed according to the IEC/IEEE Standard for Binary Floating-Point
-| Arithmetic---which means in particular that the conversion is rounded
-| according to the current rounding mode.  If `a' is a NaN, the largest
-| positive integer is returned.  Otherwise, if the conversion overflows, the
-| largest integer with the same sign as `a' is returned.
-*----------------------------------------------------------------------------*/
-
-int64 float128_to_int64( float128 a )
-{
-    flag aSign;
-    int32 aExp, shiftCount;
-    bits64 aSig0, aSig1;
-
-    aSig1 = extractFloat128Frac1( a );
-    aSig0 = extractFloat128Frac0( a );
-    aExp = extractFloat128Exp( a );
-    aSign = extractFloat128Sign( a );
-    if ( aExp ) aSig0 |= LIT64( 0x0001000000000000 );
-    shiftCount = 0x402F - aExp;
-    if ( shiftCount <= 0 ) {
-        if ( 0x403E < aExp ) {
-            float_raise( float_flag_invalid );
-            if (    ! aSign
-                 || (    ( aExp == 0x7FFF )
-                      && ( aSig1 || ( aSig0 != LIT64( 0x0001000000000000 ) ) )
-                    )
-               ) {
-                return LIT64( 0x7FFFFFFFFFFFFFFF );
-            }
-            return (sbits64) LIT64( 0x8000000000000000 );
-        }
-        shortShift128Left( aSig0, aSig1, - shiftCount, &aSig0, &aSig1 );
-    }
-    else {
-        shift64ExtraRightJamming( aSig0, aSig1, shiftCount, &aSig0, &aSig1 );
-    }
-    return roundAndPackInt64( aSign, aSig0, aSig1 );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the quadruple-precision floating-point
-| value `a' to the 64-bit two's complement integer format.  The conversion
-| is performed according to the IEC/IEEE Standard for Binary Floating-Point
-| Arithmetic, except that the conversion is always rounded toward zero.
-| If `a' is a NaN, the largest positive integer is returned.  Otherwise, if
-| the conversion overflows, the largest integer with the same sign as `a' is
-| returned.
-*----------------------------------------------------------------------------*/
-
-int64 float128_to_int64_round_to_zero( float128 a )
-{
-    flag aSign;
-    int32 aExp, shiftCount;
-    bits64 aSig0, aSig1;
-    int64 z;
-
-    aSig1 = extractFloat128Frac1( a );
-    aSig0 = extractFloat128Frac0( a );
-    aExp = extractFloat128Exp( a );
-    aSign = extractFloat128Sign( a );
-    if ( aExp ) aSig0 |= LIT64( 0x0001000000000000 );
-    shiftCount = aExp - 0x402F;
-    if ( 0 < shiftCount ) {
-        if ( 0x403E <= aExp ) {
-            aSig0 &= LIT64( 0x0000FFFFFFFFFFFF );
-            if (    ( a.high == LIT64( 0xC03E000000000000 ) )
-                 && ( aSig1 < LIT64( 0x0002000000000000 ) ) ) {
-                if ( aSig1 ) float_exception_flags |= float_flag_inexact;
-            }
-            else {
-                float_raise( float_flag_invalid );
-                if ( ! aSign || ( ( aExp == 0x7FFF ) && ( aSig0 | aSig1 ) ) ) {
-                    return LIT64( 0x7FFFFFFFFFFFFFFF );
-                }
-            }
-            return (sbits64) LIT64( 0x8000000000000000 );
-        }
-        z = ( aSig0<<shiftCount ) | ( aSig1>>( ( - shiftCount ) & 63 ) );
-        if ( (bits64) ( aSig1<<shiftCount ) ) {
-            float_exception_flags |= float_flag_inexact;
-        }
-    }
-    else {
-        if ( aExp < 0x3FFF ) {
-            if ( aExp | aSig0 | aSig1 ) {
-                float_exception_flags |= float_flag_inexact;
-            }
-            return 0;
-        }
-        z = aSig0>>( - shiftCount );
-        if (    aSig1
-             || ( shiftCount && (bits64) ( aSig0<<( shiftCount & 63 ) ) ) ) {
-            float_exception_flags |= float_flag_inexact;
-        }
-    }
-    if ( aSign ) z = - z;
-    return z;
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the quadruple-precision floating-point
-| value `a' to the single-precision floating-point format.  The conversion
-| is performed according to the IEC/IEEE Standard for Binary Floating-Point
-| Arithmetic.
-*----------------------------------------------------------------------------*/
-
-float32 float128_to_float32( float128 a )
-{
-    flag aSign;
-    int32 aExp;
-    bits64 aSig0, aSig1;
-    bits32 zSig;
-
-    aSig1 = extractFloat128Frac1( a );
-    aSig0 = extractFloat128Frac0( a );
-    aExp = extractFloat128Exp( a );
-    aSign = extractFloat128Sign( a );
-    if ( aExp == 0x7FFF ) {
-        if ( aSig0 | aSig1 ) {
-            return commonNaNToFloat32( float128ToCommonNaN( a ) );
-        }
-        return packFloat32( aSign, 0xFF, 0 );
-    }
-    aSig0 |= ( aSig1 != 0 );
-    shift64RightJamming( aSig0, 18, &aSig0 );
-    zSig = aSig0;
-    if ( aExp || zSig ) {
-        zSig |= 0x40000000;
-        aExp -= 0x3F81;
-    }
-    return roundAndPackFloat32( aSign, aExp, zSig );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the quadruple-precision floating-point
-| value `a' to the double-precision floating-point format.  The conversion
-| is performed according to the IEC/IEEE Standard for Binary Floating-Point
-| Arithmetic.
-*----------------------------------------------------------------------------*/
-
-float64 float128_to_float64( float128 a )
-{
-    flag aSign;
-    int32 aExp;
-    bits64 aSig0, aSig1;
-
-    aSig1 = extractFloat128Frac1( a );
-    aSig0 = extractFloat128Frac0( a );
-    aExp = extractFloat128Exp( a );
-    aSign = extractFloat128Sign( a );
-    if ( aExp == 0x7FFF ) {
-        if ( aSig0 | aSig1 ) {
-            return commonNaNToFloat64( float128ToCommonNaN( a ) );
-        }
-        return packFloat64( aSign, 0x7FF, 0 );
-    }
-    shortShift128Left( aSig0, aSig1, 14, &aSig0, &aSig1 );
-    aSig0 |= ( aSig1 != 0 );
-    if ( aExp || aSig0 ) {
-        aSig0 |= LIT64( 0x4000000000000000 );
-        aExp -= 0x3C01;
-    }
-    return roundAndPackFloat64( aSign, aExp, aSig0 );
-
-}
-
-#ifdef FLOATX80
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the quadruple-precision floating-point
-| value `a' to the extended double-precision floating-point format.  The
-| conversion is performed according to the IEC/IEEE Standard for Binary
-| Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-floatx80 float128_to_floatx80( float128 a )
-{
-    flag aSign;
-    int32 aExp;
-    bits64 aSig0, aSig1;
-
-    aSig1 = extractFloat128Frac1( a );
-    aSig0 = extractFloat128Frac0( a );
-    aExp = extractFloat128Exp( a );
-    aSign = extractFloat128Sign( a );
-    if ( aExp == 0x7FFF ) {
-        if ( aSig0 | aSig1 ) {
-            return commonNaNToFloatx80( float128ToCommonNaN( a ) );
-        }
-        return packFloatx80( aSign, 0x7FFF, LIT64( 0x8000000000000000 ) );
-    }
-    if ( aExp == 0 ) {
-        if ( ( aSig0 | aSig1 ) == 0 ) return packFloatx80( aSign, 0, 0 );
-        normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );
-    }
-    else {
-        aSig0 |= LIT64( 0x0001000000000000 );
-    }
-    shortShift128Left( aSig0, aSig1, 15, &aSig0, &aSig1 );
-    return roundAndPackFloatx80( 80, aSign, aExp, aSig0, aSig1 );
-
-}
-
-#endif
-
-/*----------------------------------------------------------------------------
-| Rounds the quadruple-precision floating-point value `a' to an integer, and
-| returns the result as a quadruple-precision floating-point value.  The
-| operation is performed according to the IEC/IEEE Standard for Binary
-| Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-float128 float128_round_to_int( float128 a )
-{
-    flag aSign;
-    int32 aExp;
-    bits64 lastBitMask, roundBitsMask;
-    int8 roundingMode;
-    float128 z;
-
-    aExp = extractFloat128Exp( a );
-    if ( 0x402F <= aExp ) {
-        if ( 0x406F <= aExp ) {
-            if (    ( aExp == 0x7FFF )
-                 && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) )
-               ) {
-                return propagateFloat128NaN( a, a );
-            }
-            return a;
-        }
-        lastBitMask = 1;
-        lastBitMask = ( lastBitMask<<( 0x406E - aExp ) )<<1;
-        roundBitsMask = lastBitMask - 1;
-        z = a;
-        roundingMode = float_rounding_mode;
-        if ( roundingMode == float_round_nearest_even ) {
-            if ( lastBitMask ) {
-                add128( z.high, z.low, 0, lastBitMask>>1, &z.high, &z.low );
-                if ( ( z.low & roundBitsMask ) == 0 ) z.low &= ~ lastBitMask;
-            }
-            else {
-                if ( (sbits64) z.low < 0 ) {
-                    ++z.high;
-                    if ( (bits64) ( z.low<<1 ) == 0 ) z.high &= ~1;
-                }
-            }
-        }
-        else if ( roundingMode != float_round_to_zero ) {
-            if (   extractFloat128Sign( z )
-                 ^ ( roundingMode == float_round_up ) ) {
-                add128( z.high, z.low, 0, roundBitsMask, &z.high, &z.low );
-            }
-        }
-        z.low &= ~ roundBitsMask;
-    }
-    else {
-        if ( aExp < 0x3FFF ) {
-            if ( ( ( (bits64) ( a.high<<1 ) ) | a.low ) == 0 ) return a;
-            float_exception_flags |= float_flag_inexact;
-            aSign = extractFloat128Sign( a );
-            switch ( float_rounding_mode ) {
-             case float_round_nearest_even:
-                if (    ( aExp == 0x3FFE )
-                     && (   extractFloat128Frac0( a )
-                          | extractFloat128Frac1( a ) )
-                   ) {
-                    return packFloat128( aSign, 0x3FFF, 0, 0 );
-                }
-                break;
-             case float_round_down:
-                return
-                      aSign ? packFloat128( 1, 0x3FFF, 0, 0 )
-                    : packFloat128( 0, 0, 0, 0 );
-             case float_round_up:
-                return
-                      aSign ? packFloat128( 1, 0, 0, 0 )
-                    : packFloat128( 0, 0x3FFF, 0, 0 );
-            }
-            return packFloat128( aSign, 0, 0, 0 );
-        }
-        lastBitMask = 1;
-        lastBitMask <<= 0x402F - aExp;
-        roundBitsMask = lastBitMask - 1;
-        z.low = 0;
-        z.high = a.high;
-        roundingMode = float_rounding_mode;
-        if ( roundingMode == float_round_nearest_even ) {
-            z.high += lastBitMask>>1;
-            if ( ( ( z.high & roundBitsMask ) | a.low ) == 0 ) {
-                z.high &= ~ lastBitMask;
-            }
-        }
-        else if ( roundingMode != float_round_to_zero ) {
-            if (   extractFloat128Sign( z )
-                 ^ ( roundingMode == float_round_up ) ) {
-                z.high |= ( a.low != 0 );
-                z.high += roundBitsMask;
-            }
-        }
-        z.high &= ~ roundBitsMask;
-    }
-    if ( ( z.low != a.low ) || ( z.high != a.high ) ) {
-        float_exception_flags |= float_flag_inexact;
-    }
-    return z;
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of adding the absolute values of the quadruple-precision
-| floating-point values `a' and `b'.  If `zSign' is 1, the sum is negated
-| before being returned.  `zSign' is ignored if the result is a NaN.
-| The addition is performed according to the IEC/IEEE Standard for Binary
-| Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-static float128 addFloat128Sigs( float128 a, float128 b, flag zSign )
-{
-    int32 aExp, bExp, zExp;
-    bits64 aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2;
-    int32 expDiff;
-
-    aSig1 = extractFloat128Frac1( a );
-    aSig0 = extractFloat128Frac0( a );
-    aExp = extractFloat128Exp( a );
-    bSig1 = extractFloat128Frac1( b );
-    bSig0 = extractFloat128Frac0( b );
-    bExp = extractFloat128Exp( b );
-    expDiff = aExp - bExp;
-    if ( 0 < expDiff ) {
-        if ( aExp == 0x7FFF ) {
-            if ( aSig0 | aSig1 ) return propagateFloat128NaN( a, b );
-            return a;
-        }
-        if ( bExp == 0 ) {
-            --expDiff;
-        }
-        else {
-            bSig0 |= LIT64( 0x0001000000000000 );
-        }
-        shift128ExtraRightJamming(
-            bSig0, bSig1, 0, expDiff, &bSig0, &bSig1, &zSig2 );
-        zExp = aExp;
-    }
-    else if ( expDiff < 0 ) {
-        if ( bExp == 0x7FFF ) {
-            if ( bSig0 | bSig1 ) return propagateFloat128NaN( a, b );
-            return packFloat128( zSign, 0x7FFF, 0, 0 );
-        }
-        if ( aExp == 0 ) {
-            ++expDiff;
-        }
-        else {
-            aSig0 |= LIT64( 0x0001000000000000 );
-        }
-        shift128ExtraRightJamming(
-            aSig0, aSig1, 0, - expDiff, &aSig0, &aSig1, &zSig2 );
-        zExp = bExp;
-    }
-    else {
-        if ( aExp == 0x7FFF ) {
-            if ( aSig0 | aSig1 | bSig0 | bSig1 ) {
-                return propagateFloat128NaN( a, b );
-            }
-            return a;
-        }
-        add128( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1 );
-        if ( aExp == 0 ) return packFloat128( zSign, 0, zSig0, zSig1 );
-        zSig2 = 0;
-        zSig0 |= LIT64( 0x0002000000000000 );
-        zExp = aExp;
-        goto shiftRight1;
-    }
-    aSig0 |= LIT64( 0x0001000000000000 );
-    add128( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1 );
-    --zExp;
-    if ( zSig0 < LIT64( 0x0002000000000000 ) ) goto roundAndPack;
-    ++zExp;
- shiftRight1:
-    shift128ExtraRightJamming(
-        zSig0, zSig1, zSig2, 1, &zSig0, &zSig1, &zSig2 );
- roundAndPack:
-    return roundAndPackFloat128( zSign, zExp, zSig0, zSig1, zSig2 );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of subtracting the absolute values of the quadruple-
-| precision floating-point values `a' and `b'.  If `zSign' is 1, the
-| difference is negated before being returned.  `zSign' is ignored if the
-| result is a NaN.  The subtraction is performed according to the IEC/IEEE
-| Standard for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-static float128 subFloat128Sigs( float128 a, float128 b, flag zSign )
-{
-    int32 aExp, bExp, zExp;
-    bits64 aSig0, aSig1, bSig0, bSig1, zSig0, zSig1;
-    int32 expDiff;
-    float128 z;
-
-    aSig1 = extractFloat128Frac1( a );
-    aSig0 = extractFloat128Frac0( a );
-    aExp = extractFloat128Exp( a );
-    bSig1 = extractFloat128Frac1( b );
-    bSig0 = extractFloat128Frac0( b );
-    bExp = extractFloat128Exp( b );
-    expDiff = aExp - bExp;
-    shortShift128Left( aSig0, aSig1, 14, &aSig0, &aSig1 );
-    shortShift128Left( bSig0, bSig1, 14, &bSig0, &bSig1 );
-    if ( 0 < expDiff ) goto aExpBigger;
-    if ( expDiff < 0 ) goto bExpBigger;
-    if ( aExp == 0x7FFF ) {
-        if ( aSig0 | aSig1 | bSig0 | bSig1 ) {
-            return propagateFloat128NaN( a, b );
-        }
-        float_raise( float_flag_invalid );
-        z.low = float128_default_nan_low;
-        z.high = float128_default_nan_high;
-        return z;
-    }
-    if ( aExp == 0 ) {
-        aExp = 1;
-        bExp = 1;
-    }
-    if ( bSig0 < aSig0 ) goto aBigger;
-    if ( aSig0 < bSig0 ) goto bBigger;
-    if ( bSig1 < aSig1 ) goto aBigger;
-    if ( aSig1 < bSig1 ) goto bBigger;
-    return packFloat128( float_rounding_mode == float_round_down, 0, 0, 0 );
- bExpBigger:
-    if ( bExp == 0x7FFF ) {
-        if ( bSig0 | bSig1 ) return propagateFloat128NaN( a, b );
-        return packFloat128( zSign ^ 1, 0x7FFF, 0, 0 );
-    }
-    if ( aExp == 0 ) {
-        ++expDiff;
-    }
-    else {
-        aSig0 |= LIT64( 0x4000000000000000 );
-    }
-    shift128RightJamming( aSig0, aSig1, - expDiff, &aSig0, &aSig1 );
-    bSig0 |= LIT64( 0x4000000000000000 );
- bBigger:
-    sub128( bSig0, bSig1, aSig0, aSig1, &zSig0, &zSig1 );
-    zExp = bExp;
-    zSign ^= 1;
-    goto normalizeRoundAndPack;
- aExpBigger:
-    if ( aExp == 0x7FFF ) {
-        if ( aSig0 | aSig1 ) return propagateFloat128NaN( a, b );
-        return a;
-    }
-    if ( bExp == 0 ) {
-        --expDiff;
-    }
-    else {
-        bSig0 |= LIT64( 0x4000000000000000 );
-    }
-    shift128RightJamming( bSig0, bSig1, expDiff, &bSig0, &bSig1 );
-    aSig0 |= LIT64( 0x4000000000000000 );
- aBigger:
-    sub128( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1 );
-    zExp = aExp;
- normalizeRoundAndPack:
-    --zExp;
-    return normalizeRoundAndPackFloat128( zSign, zExp - 14, zSig0, zSig1 );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of adding the quadruple-precision floating-point values
-| `a' and `b'.  The operation is performed according to the IEC/IEEE Standard
-| for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-float128 float128_add( float128 a, float128 b )
-{
-    flag aSign, bSign;
-
-    aSign = extractFloat128Sign( a );
-    bSign = extractFloat128Sign( b );
-    if ( aSign == bSign ) {
-        return addFloat128Sigs( a, b, aSign );
-    }
-    else {
-        return subFloat128Sigs( a, b, aSign );
-    }
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of subtracting the quadruple-precision floating-point
-| values `a' and `b'.  The operation is performed according to the IEC/IEEE
-| Standard for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-float128 float128_sub( float128 a, float128 b )
-{
-    flag aSign, bSign;
-
-    aSign = extractFloat128Sign( a );
-    bSign = extractFloat128Sign( b );
-    if ( aSign == bSign ) {
-        return subFloat128Sigs( a, b, aSign );
-    }
-    else {
-        return addFloat128Sigs( a, b, aSign );
-    }
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of multiplying the quadruple-precision floating-point
-| values `a' and `b'.  The operation is performed according to the IEC/IEEE
-| Standard for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-float128 float128_mul( float128 a, float128 b )
-{
-    flag aSign, bSign, zSign;
-    int32 aExp, bExp, zExp;
-    bits64 aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2, zSig3;
-    float128 z;
-
-    aSig1 = extractFloat128Frac1( a );
-    aSig0 = extractFloat128Frac0( a );
-    aExp = extractFloat128Exp( a );
-    aSign = extractFloat128Sign( a );
-    bSig1 = extractFloat128Frac1( b );
-    bSig0 = extractFloat128Frac0( b );
-    bExp = extractFloat128Exp( b );
-    bSign = extractFloat128Sign( b );
-    zSign = aSign ^ bSign;
-    if ( aExp == 0x7FFF ) {
-        if (    ( aSig0 | aSig1 )
-             || ( ( bExp == 0x7FFF ) && ( bSig0 | bSig1 ) ) ) {
-            return propagateFloat128NaN( a, b );
-        }
-        if ( ( bExp | bSig0 | bSig1 ) == 0 ) goto invalid;
-        return packFloat128( zSign, 0x7FFF, 0, 0 );
-    }
-    if ( bExp == 0x7FFF ) {
-        if ( bSig0 | bSig1 ) return propagateFloat128NaN( a, b );
-        if ( ( aExp | aSig0 | aSig1 ) == 0 ) {
- invalid:
-            float_raise( float_flag_invalid );
-            z.low = float128_default_nan_low;
-            z.high = float128_default_nan_high;
-            return z;
-        }
-        return packFloat128( zSign, 0x7FFF, 0, 0 );
-    }
-    if ( aExp == 0 ) {
-        if ( ( aSig0 | aSig1 ) == 0 ) return packFloat128( zSign, 0, 0, 0 );
-        normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );
-    }
-    if ( bExp == 0 ) {
-        if ( ( bSig0 | bSig1 ) == 0 ) return packFloat128( zSign, 0, 0, 0 );
-        normalizeFloat128Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 );
-    }
-    zExp = aExp + bExp - 0x4000;
-    aSig0 |= LIT64( 0x0001000000000000 );
-    shortShift128Left( bSig0, bSig1, 16, &bSig0, &bSig1 );
-    mul128To256( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1, &zSig2, &zSig3 );
-    add128( zSig0, zSig1, aSig0, aSig1, &zSig0, &zSig1 );
-    zSig2 |= ( zSig3 != 0 );
-    if ( LIT64( 0x0002000000000000 ) <= zSig0 ) {
-        shift128ExtraRightJamming(
-            zSig0, zSig1, zSig2, 1, &zSig0, &zSig1, &zSig2 );
-        ++zExp;
-    }
-    return roundAndPackFloat128( zSign, zExp, zSig0, zSig1, zSig2 );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of dividing the quadruple-precision floating-point value
-| `a' by the corresponding value `b'.  The operation is performed according to
-| the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-float128 float128_div( float128 a, float128 b )
-{
-    flag aSign, bSign, zSign;
-    int32 aExp, bExp, zExp;
-    bits64 aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2;
-    bits64 rem0, rem1, rem2, rem3, term0, term1, term2, term3;
-    float128 z;
-
-    aSig1 = extractFloat128Frac1( a );
-    aSig0 = extractFloat128Frac0( a );
-    aExp = extractFloat128Exp( a );
-    aSign = extractFloat128Sign( a );
-    bSig1 = extractFloat128Frac1( b );
-    bSig0 = extractFloat128Frac0( b );
-    bExp = extractFloat128Exp( b );
-    bSign = extractFloat128Sign( b );
-    zSign = aSign ^ bSign;
-    if ( aExp == 0x7FFF ) {
-        if ( aSig0 | aSig1 ) return propagateFloat128NaN( a, b );
-        if ( bExp == 0x7FFF ) {
-            if ( bSig0 | bSig1 ) return propagateFloat128NaN( a, b );
-            goto invalid;
-        }
-        return packFloat128( zSign, 0x7FFF, 0, 0 );
-    }
-    if ( bExp == 0x7FFF ) {
-        if ( bSig0 | bSig1 ) return propagateFloat128NaN( a, b );
-        return packFloat128( zSign, 0, 0, 0 );
-    }
-    if ( bExp == 0 ) {
-        if ( ( bSig0 | bSig1 ) == 0 ) {
-            if ( ( aExp | aSig0 | aSig1 ) == 0 ) {
- invalid:
-                float_raise( float_flag_invalid );
-                z.low = float128_default_nan_low;
-                z.high = float128_default_nan_high;
-                return z;
-            }
-            float_raise( float_flag_divbyzero );
-            return packFloat128( zSign, 0x7FFF, 0, 0 );
-        }
-        normalizeFloat128Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 );
-    }
-    if ( aExp == 0 ) {
-        if ( ( aSig0 | aSig1 ) == 0 ) return packFloat128( zSign, 0, 0, 0 );
-        normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );
-    }
-    zExp = aExp - bExp + 0x3FFD;
-    shortShift128Left(
-        aSig0 | LIT64( 0x0001000000000000 ), aSig1, 15, &aSig0, &aSig1 );
-    shortShift128Left(
-        bSig0 | LIT64( 0x0001000000000000 ), bSig1, 15, &bSig0, &bSig1 );
-    if ( le128( bSig0, bSig1, aSig0, aSig1 ) ) {
-        shift128Right( aSig0, aSig1, 1, &aSig0, &aSig1 );
-        ++zExp;
-    }
-    zSig0 = estimateDiv128To64( aSig0, aSig1, bSig0 );
-    mul128By64To192( bSig0, bSig1, zSig0, &term0, &term1, &term2 );
-    sub192( aSig0, aSig1, 0, term0, term1, term2, &rem0, &rem1, &rem2 );
-    while ( (sbits64) rem0 < 0 ) {
-        --zSig0;
-        add192( rem0, rem1, rem2, 0, bSig0, bSig1, &rem0, &rem1, &rem2 );
-    }
-    zSig1 = estimateDiv128To64( rem1, rem2, bSig0 );
-    if ( ( zSig1 & 0x3FFF ) <= 4 ) {
-        mul128By64To192( bSig0, bSig1, zSig1, &term1, &term2, &term3 );
-        sub192( rem1, rem2, 0, term1, term2, term3, &rem1, &rem2, &rem3 );
-        while ( (sbits64) rem1 < 0 ) {
-            --zSig1;
-            add192( rem1, rem2, rem3, 0, bSig0, bSig1, &rem1, &rem2, &rem3 );
-        }
-        zSig1 |= ( ( rem1 | rem2 | rem3 ) != 0 );
-    }
-    shift128ExtraRightJamming( zSig0, zSig1, 0, 15, &zSig0, &zSig1, &zSig2 );
-    return roundAndPackFloat128( zSign, zExp, zSig0, zSig1, zSig2 );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the remainder of the quadruple-precision floating-point value `a'
-| with respect to the corresponding value `b'.  The operation is performed
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-float128 float128_rem( float128 a, float128 b )
-{
-    flag aSign, bSign, zSign;
-    int32 aExp, bExp, expDiff;
-    bits64 aSig0, aSig1, bSig0, bSig1, q, term0, term1, term2;
-    bits64 allZero, alternateASig0, alternateASig1, sigMean1;
-    sbits64 sigMean0;
-    float128 z;
-
-    aSig1 = extractFloat128Frac1( a );
-    aSig0 = extractFloat128Frac0( a );
-    aExp = extractFloat128Exp( a );
-    aSign = extractFloat128Sign( a );
-    bSig1 = extractFloat128Frac1( b );
-    bSig0 = extractFloat128Frac0( b );
-    bExp = extractFloat128Exp( b );
-    bSign = extractFloat128Sign( b );
-    if ( aExp == 0x7FFF ) {
-        if (    ( aSig0 | aSig1 )
-             || ( ( bExp == 0x7FFF ) && ( bSig0 | bSig1 ) ) ) {
-            return propagateFloat128NaN( a, b );
-        }
-        goto invalid;
-    }
-    if ( bExp == 0x7FFF ) {
-        if ( bSig0 | bSig1 ) return propagateFloat128NaN( a, b );
-        return a;
-    }
-    if ( bExp == 0 ) {
-        if ( ( bSig0 | bSig1 ) == 0 ) {
- invalid:
-            float_raise( float_flag_invalid );
-            z.low = float128_default_nan_low;
-            z.high = float128_default_nan_high;
-            return z;
-        }
-        normalizeFloat128Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 );
-    }
-    if ( aExp == 0 ) {
-        if ( ( aSig0 | aSig1 ) == 0 ) return a;
-        normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );
-    }
-    expDiff = aExp - bExp;
-    if ( expDiff < -1 ) return a;
-    shortShift128Left(
-        aSig0 | LIT64( 0x0001000000000000 ),
-        aSig1,
-        15 - ( expDiff < 0 ),
-        &aSig0,
-        &aSig1
-    );
-    shortShift128Left(
-        bSig0 | LIT64( 0x0001000000000000 ), bSig1, 15, &bSig0, &bSig1 );
-    q = le128( bSig0, bSig1, aSig0, aSig1 );
-    if ( q ) sub128( aSig0, aSig1, bSig0, bSig1, &aSig0, &aSig1 );
-    expDiff -= 64;
-    while ( 0 < expDiff ) {
-        q = estimateDiv128To64( aSig0, aSig1, bSig0 );
-        q = ( 4 < q ) ? q - 4 : 0;
-        mul128By64To192( bSig0, bSig1, q, &term0, &term1, &term2 );
-        shortShift192Left( term0, term1, term2, 61, &term1, &term2, &allZero );
-        shortShift128Left( aSig0, aSig1, 61, &aSig0, &allZero );
-        sub128( aSig0, 0, term1, term2, &aSig0, &aSig1 );
-        expDiff -= 61;
-    }
-    if ( -64 < expDiff ) {
-        q = estimateDiv128To64( aSig0, aSig1, bSig0 );
-        q = ( 4 < q ) ? q - 4 : 0;
-        q >>= - expDiff;
-        shift128Right( bSig0, bSig1, 12, &bSig0, &bSig1 );
-        expDiff += 52;
-        if ( expDiff < 0 ) {
-            shift128Right( aSig0, aSig1, - expDiff, &aSig0, &aSig1 );
-        }
-        else {
-            shortShift128Left( aSig0, aSig1, expDiff, &aSig0, &aSig1 );
-        }
-        mul128By64To192( bSig0, bSig1, q, &term0, &term1, &term2 );
-        sub128( aSig0, aSig1, term1, term2, &aSig0, &aSig1 );
-    }
-    else {
-        shift128Right( aSig0, aSig1, 12, &aSig0, &aSig1 );
-        shift128Right( bSig0, bSig1, 12, &bSig0, &bSig1 );
-    }
-    do {
-        alternateASig0 = aSig0;
-        alternateASig1 = aSig1;
-        ++q;
-        sub128( aSig0, aSig1, bSig0, bSig1, &aSig0, &aSig1 );
-    } while ( 0 <= (sbits64) aSig0 );
-    add128(
-        aSig0, aSig1, alternateASig0, alternateASig1, &sigMean0, &sigMean1 );
-    if (    ( sigMean0 < 0 )
-         || ( ( ( sigMean0 | sigMean1 ) == 0 ) && ( q & 1 ) ) ) {
-        aSig0 = alternateASig0;
-        aSig1 = alternateASig1;
-    }
-    zSign = ( (sbits64) aSig0 < 0 );
-    if ( zSign ) sub128( 0, 0, aSig0, aSig1, &aSig0, &aSig1 );
-    return
-        normalizeRoundAndPackFloat128( aSign ^ zSign, bExp - 4, aSig0, aSig1 );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the square root of the quadruple-precision floating-point value `a'.
-| The operation is performed according to the IEC/IEEE Standard for Binary
-| Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-float128 float128_sqrt( float128 a )
-{
-    flag aSign;
-    int32 aExp, zExp;
-    bits64 aSig0, aSig1, zSig0, zSig1, zSig2, doubleZSig0;
-    bits64 rem0, rem1, rem2, rem3, term0, term1, term2, term3;
-    float128 z;
-
-    aSig1 = extractFloat128Frac1( a );
-    aSig0 = extractFloat128Frac0( a );
-    aExp = extractFloat128Exp( a );
-    aSign = extractFloat128Sign( a );
-    if ( aExp == 0x7FFF ) {
-        if ( aSig0 | aSig1 ) return propagateFloat128NaN( a, a );
-        if ( ! aSign ) return a;
-        goto invalid;
-    }
-    if ( aSign ) {
-        if ( ( aExp | aSig0 | aSig1 ) == 0 ) return a;
- invalid:
-        float_raise( float_flag_invalid );
-        z.low = float128_default_nan_low;
-        z.high = float128_default_nan_high;
-        return z;
-    }
-    if ( aExp == 0 ) {
-        if ( ( aSig0 | aSig1 ) == 0 ) return packFloat128( 0, 0, 0, 0 );
-        normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );
-    }
-    zExp = ( ( aExp - 0x3FFF )>>1 ) + 0x3FFE;
-    aSig0 |= LIT64( 0x0001000000000000 );
-    zSig0 = estimateSqrt32( aExp, aSig0>>17 );
-    shortShift128Left( aSig0, aSig1, 13 - ( aExp & 1 ), &aSig0, &aSig1 );
-    zSig0 = estimateDiv128To64( aSig0, aSig1, zSig0<<32 ) + ( zSig0<<30 );
-    doubleZSig0 = zSig0<<1;
-    mul64To128( zSig0, zSig0, &term0, &term1 );
-    sub128( aSig0, aSig1, term0, term1, &rem0, &rem1 );
-    while ( (sbits64) rem0 < 0 ) {
-        --zSig0;
-        doubleZSig0 -= 2;
-        add128( rem0, rem1, zSig0>>63, doubleZSig0 | 1, &rem0, &rem1 );
-    }
-    zSig1 = estimateDiv128To64( rem1, 0, doubleZSig0 );
-    if ( ( zSig1 & 0x1FFF ) <= 5 ) {
-        if ( zSig1 == 0 ) zSig1 = 1;
-        mul64To128( doubleZSig0, zSig1, &term1, &term2 );
-        sub128( rem1, 0, term1, term2, &rem1, &rem2 );
-        mul64To128( zSig1, zSig1, &term2, &term3 );
-        sub192( rem1, rem2, 0, 0, term2, term3, &rem1, &rem2, &rem3 );
-        while ( (sbits64) rem1 < 0 ) {
-            --zSig1;
-            shortShift128Left( 0, zSig1, 1, &term2, &term3 );
-            term3 |= 1;
-            term2 |= doubleZSig0;
-            add192( rem1, rem2, rem3, 0, term2, term3, &rem1, &rem2, &rem3 );
-        }
-        zSig1 |= ( ( rem1 | rem2 | rem3 ) != 0 );
-    }
-    shift128ExtraRightJamming( zSig0, zSig1, 0, 14, &zSig0, &zSig1, &zSig2 );
-    return roundAndPackFloat128( 0, zExp, zSig0, zSig1, zSig2 );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the quadruple-precision floating-point value `a' is equal to
-| the corresponding value `b', and 0 otherwise.  The comparison is performed
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-flag float128_eq( float128 a, float128 b )
-{
-
-    if (    (    ( extractFloat128Exp( a ) == 0x7FFF )
-              && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) )
-         || (    ( extractFloat128Exp( b ) == 0x7FFF )
-              && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )
-       ) {
-        if (    float128_is_signaling_nan( a )
-             || float128_is_signaling_nan( b ) ) {
-            float_raise( float_flag_invalid );
-        }
-        return 0;
-    }
-    return
-           ( a.low == b.low )
-        && (    ( a.high == b.high )
-             || (    ( a.low == 0 )
-                  && ( (bits64) ( ( a.high | b.high )<<1 ) == 0 ) )
-           );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the quadruple-precision floating-point value `a' is less than
-| or equal to the corresponding value `b', and 0 otherwise.  The comparison
-| is performed according to the IEC/IEEE Standard for Binary Floating-Point
-| Arithmetic.
-*----------------------------------------------------------------------------*/
-
-flag float128_le( float128 a, float128 b )
-{
-    flag aSign, bSign;
-
-    if (    (    ( extractFloat128Exp( a ) == 0x7FFF )
-              && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) )
-         || (    ( extractFloat128Exp( b ) == 0x7FFF )
-              && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )
-       ) {
-        float_raise( float_flag_invalid );
-        return 0;
-    }
-    aSign = extractFloat128Sign( a );
-    bSign = extractFloat128Sign( b );
-    if ( aSign != bSign ) {
-        return
-               aSign
-            || (    ( ( (bits64) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )
-                 == 0 );
-    }
-    return
-          aSign ? le128( b.high, b.low, a.high, a.low )
-        : le128( a.high, a.low, b.high, b.low );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the quadruple-precision floating-point value `a' is less than
-| the corresponding value `b', and 0 otherwise.  The comparison is performed
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-flag float128_lt( float128 a, float128 b )
-{
-    flag aSign, bSign;
-
-    if (    (    ( extractFloat128Exp( a ) == 0x7FFF )
-              && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) )
-         || (    ( extractFloat128Exp( b ) == 0x7FFF )
-              && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )
-       ) {
-        float_raise( float_flag_invalid );
-        return 0;
-    }
-    aSign = extractFloat128Sign( a );
-    bSign = extractFloat128Sign( b );
-    if ( aSign != bSign ) {
-        return
-               aSign
-            && (    ( ( (bits64) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )
-                 != 0 );
-    }
-    return
-          aSign ? lt128( b.high, b.low, a.high, a.low )
-        : lt128( a.high, a.low, b.high, b.low );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the quadruple-precision floating-point value `a' is equal to
-| the corresponding value `b', and 0 otherwise.  The invalid exception is
-| raised if either operand is a NaN.  Otherwise, the comparison is performed
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-flag float128_eq_signaling( float128 a, float128 b )
-{
-
-    if (    (    ( extractFloat128Exp( a ) == 0x7FFF )
-              && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) )
-         || (    ( extractFloat128Exp( b ) == 0x7FFF )
-              && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )
-       ) {
-        float_raise( float_flag_invalid );
-        return 0;
-    }
-    return
-           ( a.low == b.low )
-        && (    ( a.high == b.high )
-             || (    ( a.low == 0 )
-                  && ( (bits64) ( ( a.high | b.high )<<1 ) == 0 ) )
-           );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the quadruple-precision floating-point value `a' is less than
-| or equal to the corresponding value `b', and 0 otherwise.  Quiet NaNs do not
-| cause an exception.  Otherwise, the comparison is performed according to the
-| IEC/IEEE Standard for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-flag float128_le_quiet( float128 a, float128 b )
-{
-    flag aSign, bSign;
-
-    if (    (    ( extractFloat128Exp( a ) == 0x7FFF )
-              && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) )
-         || (    ( extractFloat128Exp( b ) == 0x7FFF )
-              && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )
-       ) {
-        if (    float128_is_signaling_nan( a )
-             || float128_is_signaling_nan( b ) ) {
-            float_raise( float_flag_invalid );
-        }
-        return 0;
-    }
-    aSign = extractFloat128Sign( a );
-    bSign = extractFloat128Sign( b );
-    if ( aSign != bSign ) {
-        return
-               aSign
-            || (    ( ( (bits64) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )
-                 == 0 );
-    }
-    return
-          aSign ? le128( b.high, b.low, a.high, a.low )
-        : le128( a.high, a.low, b.high, b.low );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the quadruple-precision floating-point value `a' is less than
-| the corresponding value `b', and 0 otherwise.  Quiet NaNs do not cause an
-| exception.  Otherwise, the comparison is performed according to the IEC/IEEE
-| Standard for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-flag float128_lt_quiet( float128 a, float128 b )
-{
-    flag aSign, bSign;
-
-    if (    (    ( extractFloat128Exp( a ) == 0x7FFF )
-              && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) )
-         || (    ( extractFloat128Exp( b ) == 0x7FFF )
-              && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )
-       ) {
-        if (    float128_is_signaling_nan( a )
-             || float128_is_signaling_nan( b ) ) {
-            float_raise( float_flag_invalid );
-        }
-        return 0;
-    }
-    aSign = extractFloat128Sign( a );
-    bSign = extractFloat128Sign( b );
-    if ( aSign != bSign ) {
-        return
-               aSign
-            && (    ( ( (bits64) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )
-                 != 0 );
-    }
-    return
-          aSign ? lt128( b.high, b.low, a.high, a.low )
-        : lt128( a.high, a.low, b.high, b.low );
-
-}
-
-#endif
-

diff --git a/softfloat/SoftFloat-3/source/f32_add.c b/softfloat/SoftFloat-3/source/f32_add.c
deleted file mode 100755 (executable)
index dc53d68..0000000
--- a/softfloat/SoftFloat-3/source/f32_add.c
+++ /dev/null
@@ -1,29 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "softfloat.h"
-
-float32_t f32_add( float32_t a, float32_t b )
-{
-    union ui32_f32 uA;
-    uint_fast32_t uiA;
-    bool signA;
-    union ui32_f32 uB;
-    uint_fast32_t uiB;
-    bool signB;
-    float32_t ( *magsRoutine )( uint_fast32_t, uint_fast32_t, bool );
-
-    uA.f = a;
-    uiA = uA.ui;
-    signA = signF32UI( uiA );
-    uB.f = b;
-    uiB = uB.ui;
-    signB = signF32UI( uiB );
-    magsRoutine =
-        ( signA == signB ) ? softfloat_addMagsF32 : softfloat_subMagsF32;
-    return magsRoutine( uiA, uiB, signA );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/f32_div.c b/softfloat/SoftFloat-3/source/f32_div.c
deleted file mode 100755 (executable)
index 958b140..0000000
--- a/softfloat/SoftFloat-3/source/f32_div.c
+++ /dev/null
@@ -1,96 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "specialize.h"
-#include "softfloat.h"
-
-float32_t f32_div( float32_t a, float32_t b )
-{
-    union ui32_f32 uA;
-    uint_fast32_t uiA;
-    bool signA;
-    int_fast16_t expA;
-    uint_fast32_t sigA;
-    union ui32_f32 uB;
-    uint_fast32_t uiB;
-    bool signB;
-    int_fast16_t expB;
-    uint_fast32_t sigB;
-    bool signZ;
-    struct exp16_sig32 normExpSig;
-    int_fast16_t expZ;
-    uint_fast32_t sigZ;
-    uint_fast32_t uiZ;
-    union ui32_f32 uZ;
-
-    uA.f = a;
-    uiA = uA.ui;
-    signA = signF32UI( uiA );
-    expA = expF32UI( uiA );
-    sigA = fracF32UI( uiA );
-    uB.f = b;
-    uiB = uB.ui;
-    signB = signF32UI( uiB );
-    expB = expF32UI( uiB );
-    sigB = fracF32UI( uiB );
-    signZ = signA ^ signB;
-    if ( expA == 0xFF ) {
-        if ( sigA ) goto propagateNaN;
-        if ( expB == 0xFF ) {
-            if ( sigB ) goto propagateNaN;
-            goto invalid;
-        }
-        goto infinity;
-    }
-    if ( expB == 0xFF ) {
-        if ( sigB ) goto propagateNaN;
-        goto zero;
-    }
-    if ( ! expB ) {
-        if ( ! sigB ) {
-            if ( ! ( expA | sigA ) ) goto invalid;
-            softfloat_raiseFlags( softfloat_flag_infinity );
-            goto infinity;
-        }
-        normExpSig = softfloat_normSubnormalF32Sig( sigB );
-        expB = normExpSig.exp;
-        sigB = normExpSig.sig;
-    }
-    if ( ! expA ) {
-        if ( ! sigA ) goto zero;
-        normExpSig = softfloat_normSubnormalF32Sig( sigA );
-        expA = normExpSig.exp;
-        sigA = normExpSig.sig;
-    }
-    expZ = expA - expB + 0x7D;
-    sigA = ( sigA | 0x00800000 )<<7;
-    sigB = ( sigB | 0x00800000 )<<8;
-    if ( sigB <= ( sigA + sigA ) ) {
-        ++expZ;
-        sigA >>= 1;
-    }
-    sigZ = ( (uint_fast64_t) sigA<<32 ) / sigB;
-    if ( ! ( sigZ & 0x3F ) ) {
-        sigZ |= ( (uint_fast64_t) sigB * sigZ != (uint_fast64_t) sigA<<32 );
-    }
-    return softfloat_roundPackToF32( signZ, expZ, sigZ );
- propagateNaN:
-    uiZ = softfloat_propagateNaNF32UI( uiA, uiB );
-    goto uiZ;
- invalid:
-    softfloat_raiseFlags( softfloat_flag_invalid );
-    uiZ = defaultNaNF32UI;
-    goto uiZ;
- infinity:
-    uiZ = packToF32UI( signZ, 0xFF, 0 );
-    goto uiZ;
- zero:
-    uiZ = packToF32UI( signZ, 0, 0 );
- uiZ:
-    uZ.ui = uiZ;
-    return uZ.f;
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/f32_eq.c b/softfloat/SoftFloat-3/source/f32_eq.c
deleted file mode 100755 (executable)
index 8f2306b..0000000
--- a/softfloat/SoftFloat-3/source/f32_eq.c
+++ /dev/null
@@ -1,34 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "specialize.h"
-#include "softfloat.h"
-
-bool f32_eq( float32_t a, float32_t b )
-{
-    union ui32_f32 uA;
-    uint_fast32_t uiA;
-    union ui32_f32 uB;
-    uint_fast32_t uiB;
-
-    uA.f = a;
-    uiA = uA.ui;
-    uB.f = b;
-    uiB = uB.ui;
-    if (
-           ( ( expF32UI( uiA ) == 0xFF ) && fracF32UI( uiA ) )
-        || ( ( expF32UI( uiB ) == 0xFF ) && fracF32UI( uiB ) )
-    ) {
-        if (
-            softfloat_isSigNaNF32UI( uiA ) || softfloat_isSigNaNF32UI( uiB )
-        ) {
-            softfloat_raiseFlags( softfloat_flag_invalid );
-        }
-        return false;
-    }
-    return ( uiA == uiB ) || ! (uint32_t) ( ( uiA | uiB )<<1 );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/f32_eq_signaling.c b/softfloat/SoftFloat-3/source/f32_eq_signaling.c
deleted file mode 100755 (executable)
index bfba48a..0000000
--- a/softfloat/SoftFloat-3/source/f32_eq_signaling.c
+++ /dev/null
@@ -1,29 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "softfloat.h"
-
-bool f32_eq_signaling( float32_t a, float32_t b )
-{
-    union ui32_f32 uA;
-    uint_fast32_t uiA;
-    union ui32_f32 uB;
-    uint_fast32_t uiB;
-
-    uA.f = a;
-    uiA = uA.ui;
-    uB.f = b;
-    uiB = uB.ui;
-    if (
-           ( ( expF32UI( uiA ) == 0xFF ) && fracF32UI( uiA ) )
-        || ( ( expF32UI( uiB ) == 0xFF ) && fracF32UI( uiB ) )
-    ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
-        return false;
-    }
-    return ( uiA == uiB ) || ! (uint32_t) ( ( uiA | uiB )<<1 );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/f32_isSignalingNaN.c b/softfloat/SoftFloat-3/source/f32_isSignalingNaN.c
deleted file mode 100755 (executable)
index 09aaa82..0000000
--- a/softfloat/SoftFloat-3/source/f32_isSignalingNaN.c
+++ /dev/null
@@ -1,16 +0,0 @@
-
-#include <stdbool.h>
-#include "platform.h"
-#include "internals.h"
-#include "specialize.h"
-#include "softfloat.h"
-
-bool f32_isSignalingNaN( float32_t a )
-{
-    union ui32_f32 uA;
-
-    uA.f = a;
-    return softfloat_isSigNaNF32UI( uA.ui );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/f32_le.c b/softfloat/SoftFloat-3/source/f32_le.c
deleted file mode 100755 (executable)
index 5f47be5..0000000
--- a/softfloat/SoftFloat-3/source/f32_le.c
+++ /dev/null
@@ -1,34 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "softfloat.h"
-
-bool f32_le( float32_t a, float32_t b )
-{
-    union ui32_f32 uA;
-    uint_fast32_t uiA;
-    union ui32_f32 uB;
-    uint_fast32_t uiB;
-    bool signA, signB;
-
-    uA.f = a;
-    uiA = uA.ui;
-    uB.f = b;
-    uiB = uB.ui;
-    if (
-           ( ( expF32UI( uiA ) == 0xFF ) && fracF32UI( uiA ) )
-        || ( ( expF32UI( uiB ) == 0xFF ) && fracF32UI( uiB ) )
-    ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
-        return false;
-    }
-    signA = signF32UI( uiA );
-    signB = signF32UI( uiB );
-    return
-        ( signA != signB ) ? signA || ! (uint32_t) ( ( uiA | uiB )<<1 )
-            : ( uiA == uiB ) || ( signA ^ ( uiA < uiB ) );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/f32_le_quiet.c b/softfloat/SoftFloat-3/source/f32_le_quiet.c
deleted file mode 100755 (executable)
index 2b541da..0000000
--- a/softfloat/SoftFloat-3/source/f32_le_quiet.c
+++ /dev/null
@@ -1,39 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "specialize.h"
-#include "softfloat.h"
-
-bool f32_le_quiet( float32_t a, float32_t b )
-{
-    union ui32_f32 uA;
-    uint_fast32_t uiA;
-    union ui32_f32 uB;
-    uint_fast32_t uiB;
-    bool signA, signB;
-
-    uA.f = a;
-    uiA = uA.ui;
-    uB.f = b;
-    uiB = uB.ui;
-    if (
-           ( ( expF32UI( uiA ) == 0xFF ) && fracF32UI( uiA ) )
-        || ( ( expF32UI( uiB ) == 0xFF ) && fracF32UI( uiB ) )
-    ) {
-        if (
-            softfloat_isSigNaNF32UI( uiA ) || softfloat_isSigNaNF32UI( uiB )
-        ) {
-            softfloat_raiseFlags( softfloat_flag_invalid );
-        }
-        return false;
-    }
-    signA = signF32UI( uiA );
-    signB = signF32UI( uiB );
-    return
-        ( signA != signB ) ? signA || ! (uint32_t) ( ( uiA | uiB )<<1 )
-            : ( uiA == uiB ) || ( signA ^ ( uiA < uiB ) );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/f32_lt.c b/softfloat/SoftFloat-3/source/f32_lt.c
deleted file mode 100755 (executable)
index 753b28a..0000000
--- a/softfloat/SoftFloat-3/source/f32_lt.c
+++ /dev/null
@@ -1,34 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "softfloat.h"
-
-bool f32_lt( float32_t a, float32_t b )
-{
-    union ui32_f32 uA;
-    uint_fast32_t uiA;
-    union ui32_f32 uB;
-    uint_fast32_t uiB;
-    bool signA, signB;
-
-    uA.f = a;
-    uiA = uA.ui;
-    uB.f = b;
-    uiB = uB.ui;
-    if (
-           ( ( expF32UI( uiA ) == 0xFF ) && fracF32UI( uiA ) )
-        || ( ( expF32UI( uiB ) == 0xFF ) && fracF32UI( uiB ) )
-    ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
-        return false;
-    }
-    signA = signF32UI( uiA );
-    signB = signF32UI( uiB );
-    return
-        ( signA != signB ) ? signA && ( (uint32_t) ( ( uiA | uiB )<<1 ) != 0 )
-            : ( uiA != uiB ) && ( signA ^ ( uiA < uiB ) );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/f32_lt_quiet.c b/softfloat/SoftFloat-3/source/f32_lt_quiet.c
deleted file mode 100755 (executable)
index ecd90bf..0000000
--- a/softfloat/SoftFloat-3/source/f32_lt_quiet.c
+++ /dev/null
@@ -1,39 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "specialize.h"
-#include "softfloat.h"
-
-bool f32_lt_quiet( float32_t a, float32_t b )
-{
-    union ui32_f32 uA;
-    uint_fast32_t uiA;
-    union ui32_f32 uB;
-    uint_fast32_t uiB;
-    bool signA, signB;
-
-    uA.f = a;
-    uiA = uA.ui;
-    uB.f = b;
-    uiB = uB.ui;
-    if (
-           ( ( expF32UI( uiA ) == 0xFF ) && fracF32UI( uiA ) )
-        || ( ( expF32UI( uiB ) == 0xFF ) && fracF32UI( uiB ) )
-    ) {
-        if (
-            softfloat_isSigNaNF32UI( uiA ) || softfloat_isSigNaNF32UI( uiB )
-        ) {
-            softfloat_raiseFlags( softfloat_flag_invalid );
-        }
-        return false;
-    }
-    signA = signF32UI( uiA );
-    signB = signF32UI( uiB );
-    return
-        ( signA != signB ) ? signA && ( (uint32_t) ( ( uiA | uiB )<<1 ) != 0 )
-            : ( uiA != uiB ) && ( signA ^ ( uiA < uiB ) );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/f32_mul.c b/softfloat/SoftFloat-3/source/f32_mul.c
deleted file mode 100755 (executable)
index d49c1dd..0000000
--- a/softfloat/SoftFloat-3/source/f32_mul.c
+++ /dev/null
@@ -1,89 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-#include "specialize.h"\r
-#include "softfloat.h"\r
-\r
-float32_t f32_mul( float32_t a, float32_t b )\r
-{\r
-    union ui32_f32 uA;\r
-    uint_fast32_t uiA;\r
-    bool signA;\r
-    int_fast16_t expA;\r
-    uint_fast32_t sigA;\r
-    union ui32_f32 uB;\r
-    uint_fast32_t uiB;\r
-    bool signB;\r
-    int_fast16_t expB;\r
-    uint_fast32_t sigB;\r
-    bool signZ;\r
-    uint_fast32_t magBits;\r
-    struct exp16_sig32 normExpSig;\r
-    int_fast16_t expZ;\r
-    uint_fast32_t sigZ, uiZ;\r
-    union ui32_f32 uZ;\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    signA = signF32UI( uiA );\r
-    expA = expF32UI( uiA );\r
-    sigA = fracF32UI( uiA );\r
-    uB.f = b;\r
-    uiB = uB.ui;\r
-    signB = signF32UI( uiB );\r
-    expB = expF32UI( uiB );\r
-    sigB = fracF32UI( uiB );\r
-    signZ = signA ^ signB;\r
-    if ( expA == 0xFF ) {\r
-        if ( sigA || ( ( expB == 0xFF ) && sigB ) ) goto propagateNaN;\r
-        magBits = expB | sigB;\r
-        goto infArg;\r
-    }\r
-    if ( expB == 0xFF ) {\r
-        if ( sigB ) goto propagateNaN;\r
-        magBits = expA | sigA;\r
-        goto infArg;\r
-    }\r
-    if ( ! expA ) {\r
-        if ( ! sigA ) goto zero;\r
-        normExpSig = softfloat_normSubnormalF32Sig( sigA );\r
-        expA = normExpSig.exp;\r
-        sigA = normExpSig.sig;\r
-    }\r
-    if ( ! expB ) {\r
-        if ( ! sigB ) goto zero;\r
-        normExpSig = softfloat_normSubnormalF32Sig( sigB );\r
-        expB = normExpSig.exp;\r
-        sigB = normExpSig.sig;\r
-    }\r
-    expZ = expA + expB - 0x7F;\r
-    sigA = ( sigA | 0x00800000 )<<7;\r
-    sigB = ( sigB | 0x00800000 )<<8;\r
-    sigZ = softfloat_shortShift64RightJam( (uint_fast64_t) sigA * sigB, 32 );\r
-    if ( sigZ < 0x40000000 ) {\r
-        --expZ;\r
-        sigZ <<= 1;\r
-    }\r
-    return softfloat_roundPackToF32( signZ, expZ, sigZ );\r
- propagateNaN:\r
-    uiZ = softfloat_propagateNaNF32UI( uiA, uiB );\r
-    goto uiZ;\r
- infArg:\r
-    if ( ! magBits ) {\r
-        softfloat_raiseFlags( softfloat_flag_invalid );\r
-        uiZ = defaultNaNF32UI;\r
-    } else {\r
-        uiZ = packToF32UI( signZ, 0xFF, 0 );\r
-    }\r
-    goto uiZ;\r
- zero:\r
-    uiZ = packToF32UI( signZ, 0, 0 );\r
- uiZ:\r
-    uZ.ui = uiZ;\r
-    return uZ.f;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/f32_mulAdd.c b/softfloat/SoftFloat-3/source/f32_mulAdd.c
deleted file mode 100755 (executable)
index 3d4cee9..0000000
--- a/softfloat/SoftFloat-3/source/f32_mulAdd.c
+++ /dev/null
@@ -1,25 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-float32_t f32_mulAdd( float32_t a, float32_t b, float32_t c )\r
-{\r
-    union ui32_f32 uA;\r
-    uint_fast32_t uiA;\r
-    union ui32_f32 uB;\r
-    uint_fast32_t uiB;\r
-    union ui32_f32 uC;\r
-    uint_fast32_t uiC;\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    uB.f = b;\r
-    uiB = uB.ui;\r
-    uC.f = c;\r
-    uiC = uC.ui;\r
-    return softfloat_mulAddF32( 0, uiA, uiB, uiC );\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/f32_rem.c b/softfloat/SoftFloat-3/source/f32_rem.c
deleted file mode 100755 (executable)
index d29b840..0000000
--- a/softfloat/SoftFloat-3/source/f32_rem.c
+++ /dev/null
@@ -1,124 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "primitives.h"
-#include "internals.h"
-#include "specialize.h"
-#include "softfloat.h"
-
-float32_t f32_rem( float32_t a, float32_t b )
-{
-    union ui32_f32 uA;
-    uint_fast32_t uiA;
-    bool signA;
-    int_fast16_t expA;
-    uint_fast32_t sigA;
-    union ui32_f32 uB;
-    uint_fast32_t uiB;
-    bool signB;
-    int_fast16_t expB;
-    uint_fast32_t sigB;
-    struct exp16_sig32 normExpSig;
-    int_fast16_t expDiff;
-    uint_fast32_t q;
-    uint_fast64_t sigA64, sigB64, q64;
-    uint_fast32_t alternateSigA;
-    uint32_t sigMean;
-    bool signZ;
-    uint_fast32_t uiZ;
-    union ui32_f32 uZ;
-
-    uA.f = a;
-    uiA = uA.ui;
-    signA = signF32UI( uiA );
-    expA = expF32UI( uiA );
-    sigA = fracF32UI( uiA );
-    uB.f = b;
-    uiB = uB.ui;
-    signB = signF32UI( uiB );
-    expB = expF32UI( uiB );
-    sigB = fracF32UI( uiB );
-    if ( expA == 0xFF ) {
-        if ( sigA || ( ( expB == 0xFF ) && sigB ) ) goto propagateNaN;
-        goto invalid;
-    }
-    if ( expB == 0xFF ) {
-        if ( sigB ) goto propagateNaN;
-        return a;
-    }
-    if ( ! expB ) {
-        if ( ! sigB ) goto invalid;
-        normExpSig = softfloat_normSubnormalF32Sig( sigB );
-        expB = normExpSig.exp;
-        sigB = normExpSig.sig;
-    }
-    if ( ! expA ) {
-        if ( ! sigA ) return a;
-        normExpSig = softfloat_normSubnormalF32Sig( sigA );
-        expA = normExpSig.exp;
-        sigA = normExpSig.sig;
-    }
-    expDiff = expA - expB;
-    sigA |= 0x00800000;
-    sigB |= 0x00800000;
-    if ( expDiff < 32 ) {
-        sigA <<= 8;
-        sigB <<= 8;
-        if ( expDiff < 0 ) {
-            if ( expDiff < -1 ) return a;
-            sigA >>= 1;
-        }
-        q = ( sigB <= sigA );
-        if ( q ) sigA -= sigB;
-        if ( 0 < expDiff ) {
-            q = ( (uint_fast64_t) sigA<<32 ) / sigB;
-            q >>= 32 - expDiff;
-            sigB >>= 2;
-            sigA = ( ( sigA>>1 )<<( expDiff - 1 ) ) - sigB * q;
-        } else {
-            sigA >>= 2;
-            sigB >>= 2;
-        }
-    } else {
-        if ( sigB <= sigA ) sigA -= sigB;
-        sigA64 = (uint_fast64_t) sigA<<40;
-        sigB64 = (uint_fast64_t) sigB<<40;
-        expDiff -= 64;
-        while ( 0 < expDiff ) {
-            q64 = softfloat_estimateDiv128To64( sigA64, 0, sigB64 );
-            q64 = ( 2 < q64 ) ? q64 - 2 : 0;
-            sigA64 = - ( ( sigB * q64 )<<38 );
-            expDiff -= 62;
-        }
-        expDiff += 64;
-        q64 = softfloat_estimateDiv128To64( sigA64, 0, sigB64 );
-        q64 = ( 2 < q64 ) ? q64 - 2 : 0;
-        q = q64>>( 64 - expDiff );
-        sigB <<= 6;
-        sigA = ( ( sigA64>>33 )<<( expDiff - 1 ) ) - sigB * q;
-    }
-    do {
-        alternateSigA = sigA;
-        ++q;
-        sigA -= sigB;
-    } while ( sigA < 0x80000000 );
-    sigMean = sigA + alternateSigA;
-    if ( ( 0x80000000 <= sigMean ) || ( ! sigMean && ( q & 1 ) ) ) {
-        sigA = alternateSigA;
-    }
-    signZ = ( 0x80000000 <= sigA );
-    if ( signZ ) sigA = - sigA;
-    return softfloat_normRoundPackToF32( signA ^ signZ, expB, sigA );
- propagateNaN:
-    uiZ = softfloat_propagateNaNF32UI( uiA, uiB );
-    goto uiZ;
- invalid:
-    softfloat_raiseFlags( softfloat_flag_invalid );
-    uiZ = defaultNaNF32UI;
- uiZ:
-    uZ.ui = uiZ;
-    return uZ.f;
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/f32_roundToInt.c b/softfloat/SoftFloat-3/source/f32_roundToInt.c
deleted file mode 100755 (executable)
index f8f9114..0000000
--- a/softfloat/SoftFloat-3/source/f32_roundToInt.c
+++ /dev/null
@@ -1,78 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "specialize.h"
-#include "softfloat.h"
-
-float32_t f32_roundToInt( float32_t a, int_fast8_t roundingMode, bool exact )
-{
-    union ui32_f32 uA;
-    uint_fast32_t uiA;
-    int_fast16_t expA;
-    uint_fast32_t uiZ;
-    bool signA;
-    uint_fast32_t lastBitMask, roundBitsMask;
-    union ui32_f32 uZ;
-
-    uA.f = a;
-    uiA = uA.ui;
-    expA = expF32UI( uiA );
-    if ( 0x96 <= expA ) {
-        if ( ( expA == 0xFF ) && fracF32UI( uiA ) ) {
-            uiZ = softfloat_propagateNaNF32UI( uiA, 0 );
-            goto uiZ;
-        }
-        return a;
-    }
-    if ( expA <= 0x7E ) {
-        if ( ! (uint32_t) ( uiA<<1 ) ) return a;
-        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
-        signA = signF32UI( uiA );
-        switch ( roundingMode ) {
-         case softfloat_round_nearest_even:
-            if ( ( expA == 0x7E ) && fracF32UI( uiA ) ) {
-                uiZ = packToF32UI( signA, 0x7F, 0 );
-                goto uiZ;
-            }
-            break;
-         case softfloat_round_min:
-            uiZ = signA ? 0xBF800000 : 0;
-            goto uiZ;
-         case softfloat_round_max:
-            uiZ = signA ? 0x80000000 : 0x3F800000;
-            goto uiZ;
-         case softfloat_round_nearest_maxMag:
-            if ( expA == 0x7E ) {
-                uiZ = packToF32UI( signA, 0x7F, 0 );
-                goto uiZ;
-            }
-            break;
-        }
-        uiZ = packToF32UI( signA, 0, 0 );
-        goto uiZ;
-    }
-    lastBitMask = (uint_fast32_t) 1<<( 0x96 - expA );
-    roundBitsMask = lastBitMask - 1;
-    uiZ = uiA;
-    if ( roundingMode == softfloat_round_nearest_maxMag ) {
-        uiZ += lastBitMask>>1;
-    } else if ( roundingMode == softfloat_round_nearest_even ) {
-        uiZ += lastBitMask>>1;
-        if ( ! ( uiZ & roundBitsMask ) ) uiZ &= ~ lastBitMask;
-    } else if ( roundingMode != softfloat_round_minMag ) {
-        if ( signF32UI( uiZ ) ^ ( roundingMode == softfloat_round_max ) ) {
-            uiZ += roundBitsMask;
-        }
-    }
-    uiZ &= ~ roundBitsMask;
-    if ( exact && ( uiZ != uiA ) ) {
-        softfloat_exceptionFlags |= softfloat_flag_inexact;
-    }
- uiZ:
-    uZ.ui = uiZ;
-    return uZ.f;
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/f32_sqrt.c b/softfloat/SoftFloat-3/source/f32_sqrt.c
deleted file mode 100755 (executable)
index c9eb907..0000000
--- a/softfloat/SoftFloat-3/source/f32_sqrt.c
+++ /dev/null
@@ -1,74 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-#include "specialize.h"\r
-#include "softfloat.h"\r
-\r
-float32_t f32_sqrt( float32_t a )\r
-{\r
-    union ui32_f32 uA;\r
-    uint_fast32_t uiA;\r
-    bool signA;\r
-    int_fast16_t expA;\r
-    uint_fast32_t sigA, uiZ;\r
-    struct exp16_sig32 normExpSig;\r
-    int_fast16_t expZ;\r
-    uint_fast32_t sigZ;\r
-    uint_fast64_t term, rem;\r
-    union ui32_f32 uZ;\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    signA = signF32UI( uiA );\r
-    expA = expF32UI( uiA );\r
-    sigA = fracF32UI( uiA );\r
-    if ( expA == 0xFF ) {\r
-        if ( sigA ) {\r
-            uiZ = softfloat_propagateNaNF32UI( uiA, 0 );\r
-            goto uiZ;\r
-        }\r
-        if ( ! signA ) return a;\r
-        goto invalid;\r
-    }\r
-    if ( signA ) {\r
-        if ( ! ( expA | sigA ) ) return a;\r
-        goto invalid;\r
-    }\r
-    if ( ! expA ) {\r
-        if ( ! sigA ) return a;\r
-        normExpSig = softfloat_normSubnormalF32Sig( sigA );\r
-        expA = normExpSig.exp;\r
-        sigA = normExpSig.sig;\r
-    }\r
-    expZ = ( ( expA - 0x7F )>>1 ) + 0x7E;\r
-    sigA = ( sigA | 0x00800000 )<<8;\r
-    sigZ = softfloat_estimateSqrt32( expA, sigA ) + 2;\r
-    if ( ( sigZ & 0x7F ) <= 5 ) {\r
-        if ( sigZ < 2 ) {\r
-            sigZ = 0x7FFFFFFF;\r
-            goto roundPack;\r
-        }\r
-        sigA >>= expA & 1;\r
-        term = (uint_fast64_t) sigZ * sigZ;\r
-        rem = ( (uint_fast64_t) sigA<<32 ) - term;\r
-        while ( UINT64_C( 0x8000000000000000 ) <= rem ) {\r
-            --sigZ;\r
-            rem += ( (uint_fast64_t) sigZ<<1 ) | 1;\r
-        }\r
-        sigZ |= ( rem != 0 );\r
-    }\r
-    sigZ = softfloat_shortShift32Right1Jam( sigZ );\r
- roundPack:\r
-    return softfloat_roundPackToF32( 0, expZ, sigZ );\r
- invalid:\r
-    softfloat_raiseFlags( softfloat_flag_invalid );\r
-    uiZ = defaultNaNF32UI;\r
- uiZ:\r
-    uZ.ui = uiZ;\r
-    return uZ.f;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/f32_sub.c b/softfloat/SoftFloat-3/source/f32_sub.c
deleted file mode 100755 (executable)
index c64df8e..0000000
--- a/softfloat/SoftFloat-3/source/f32_sub.c
+++ /dev/null
@@ -1,29 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-float32_t f32_sub( float32_t a, float32_t b )\r
-{\r
-    union ui32_f32 uA;\r
-    uint_fast32_t uiA;\r
-    bool signA;\r
-    union ui32_f32 uB;\r
-    uint_fast32_t uiB;\r
-    bool signB;\r
-    float32_t ( *magsRoutine )( uint_fast32_t, uint_fast32_t, bool );\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    signA = signF32UI( uiA );\r
-    uB.f = b;\r
-    uiB = uB.ui;\r
-    signB = signF32UI( uiB );\r
-    magsRoutine =\r
-        ( signA == signB ) ? softfloat_subMagsF32 : softfloat_addMagsF32;\r
-    return magsRoutine( uiA, uiB ^ 0x80000000, signA );\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/f32_to_f64.c b/softfloat/SoftFloat-3/source/f32_to_f64.c
deleted file mode 100755 (executable)
index 9f0ae5c..0000000
--- a/softfloat/SoftFloat-3/source/f32_to_f64.c
+++ /dev/null
@@ -1,47 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "internals.h"\r
-#include "specialize.h"\r
-#include "softfloat.h"\r
-\r
-float64_t f32_to_f64( float32_t a )\r
-{\r
-    union ui32_f32 uA;\r
-    uint_fast32_t uiA;\r
-    bool sign;\r
-    int_fast16_t exp;\r
-    uint_fast32_t sig;\r
-    uint_fast64_t uiZ;\r
-    struct exp16_sig32 normExpSig;\r
-    union ui64_f64 uZ;\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    sign = signF32UI( uiA );\r
-    exp = expF32UI( uiA );\r
-    sig = fracF32UI( uiA );\r
-    if ( exp == 0xFF ) {\r
-        uiZ =\r
-            sig ? softfloat_commonNaNToF64UI(\r
-                      softfloat_f32UIToCommonNaN( uiA ) )\r
-                : packToF64UI( sign, 0x7FF, 0 );\r
-        goto uiZ;\r
-    }\r
-    if ( ! exp ) {\r
-        if ( ! sig ) {\r
-            uiZ = packToF64UI( sign, 0, 0 );\r
-            goto uiZ;\r
-        }\r
-        normExpSig = softfloat_normSubnormalF32Sig( sig );\r
-        exp = normExpSig.exp - 1;\r
-        sig = normExpSig.sig;\r
-    }\r
-    uiZ = packToF64UI( sign, exp + 0x380, (uint_fast64_t) sig<<29 );\r
- uiZ:\r
-    uZ.ui = uiZ;\r
-    return uZ.f;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/f32_to_i32.c b/softfloat/SoftFloat-3/source/f32_to_i32.c
deleted file mode 100755 (executable)
index bbbaee0..0000000
--- a/softfloat/SoftFloat-3/source/f32_to_i32.c
+++ /dev/null
@@ -1,34 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-int_fast32_t f32_to_i32( float32_t a, int_fast8_t roundingMode, bool exact )\r
-{\r
-    union ui32_f32 uA;\r
-    uint_fast32_t uiA;\r
-    bool sign;\r
-    int_fast16_t exp;\r
-    uint_fast32_t sig;\r
-    uint_fast64_t sig64;\r
-    int_fast16_t shiftCount;\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    sign = signF32UI( uiA );\r
-    exp = expF32UI( uiA );\r
-    sig = fracF32UI( uiA );\r
-    if ( ( exp == 0xFF ) && sig ) sign = 0;\r
-    if ( exp ) sig |= 0x00800000;\r
-    sig64 = (uint_fast64_t) sig<<32;\r
-    shiftCount = 0xAF - exp;\r
-    if ( 0 < shiftCount ) {\r
-        sig64 = softfloat_shift64RightJam( sig64, shiftCount );\r
-    }\r
-    return softfloat_roundPackToI32( sign, sig64, roundingMode, exact );\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/f32_to_i32_r_minMag.c b/softfloat/SoftFloat-3/source/f32_to_i32_r_minMag.c
deleted file mode 100755 (executable)
index 63ff1e2..0000000
--- a/softfloat/SoftFloat-3/source/f32_to_i32_r_minMag.c
+++ /dev/null
@@ -1,45 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-int_fast32_t f32_to_i32_r_minMag( float32_t a, bool exact )\r
-{\r
-    union ui32_f32 uA;\r
-    uint_fast32_t uiA;\r
-    int_fast16_t exp;\r
-    uint_fast32_t sig;\r
-    bool sign;\r
-    int_fast16_t shiftCount;\r
-    int_fast32_t absZ;\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    exp = expF32UI( uiA );\r
-    sig = fracF32UI( uiA );\r
-    if ( exp < 0x7F ) {\r
-        if ( exact && ( exp | sig ) ) {\r
-            softfloat_exceptionFlags |= softfloat_flag_inexact;\r
-        }\r
-        return 0;\r
-    }\r
-    sign = signF32UI( uiA );\r
-    shiftCount = 0x9E - exp;\r
-    if ( shiftCount <= 0 ) {\r
-        if ( uiA != packToF32UI( 1, 0x9E, 0 ) ) {\r
-            softfloat_raiseFlags( softfloat_flag_invalid );\r
-            if ( ! sign || ( ( exp == 0xFF ) && sig ) ) return 0x7FFFFFFF;\r
-        }\r
-        return -0x7FFFFFFF - 1;\r
-    }\r
-    sig = ( sig | 0x00800000 )<<8;\r
-    absZ = sig>>shiftCount;\r
-    if ( exact && (uint32_t) ( sig<<( ( - shiftCount ) & 31 ) ) ) {\r
-        softfloat_exceptionFlags |= softfloat_flag_inexact;\r
-    }\r
-    return sign ? - absZ : absZ;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/f32_to_i64.c b/softfloat/SoftFloat-3/source/f32_to_i64.c
deleted file mode 100755 (executable)
index c0b8981..0000000
--- a/softfloat/SoftFloat-3/source/f32_to_i64.c
+++ /dev/null
@@ -1,44 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-int_fast64_t f32_to_i64( float32_t a, int_fast8_t roundingMode, bool exact )\r
-{\r
-    union ui32_f32 uA;\r
-    uint_fast32_t uiA;\r
-    bool sign;\r
-    int_fast16_t exp;\r
-    uint_fast32_t sig;\r
-    int_fast16_t shiftCount;\r
-    uint_fast64_t sig64, extra;\r
-    struct uint64_extra sig64Extra;\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    sign = signF32UI( uiA );\r
-    exp = expF32UI( uiA );\r
-    sig = fracF32UI( uiA );\r
-    shiftCount = 0xBE - exp;\r
-    if ( shiftCount < 0 ) {\r
-        softfloat_raiseFlags( softfloat_flag_invalid );\r
-        if ( ! sign || ( ( exp == 0xFF ) && sig ) ) {\r
-            return INT64_C( 0x7FFFFFFFFFFFFFFF );\r
-        }\r
-        return - INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1;\r
-    }\r
-    if ( exp ) sig |= 0x00800000;\r
-    sig64 = (uint_fast64_t) sig<<40;\r
-    extra = 0;\r
-    if ( shiftCount ) {\r
-        sig64Extra = softfloat_shift64ExtraRightJam( sig64, 0, shiftCount );\r
-        sig64 = sig64Extra.v;\r
-        extra = sig64Extra.extra;\r
-    }\r
-    return softfloat_roundPackToI64( sign, sig64, extra, roundingMode, exact );\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/f32_to_i64_r_minMag.c b/softfloat/SoftFloat-3/source/f32_to_i64_r_minMag.c
deleted file mode 100755 (executable)
index 33bff93..0000000
--- a/softfloat/SoftFloat-3/source/f32_to_i64_r_minMag.c
+++ /dev/null
@@ -1,52 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-int_fast64_t f32_to_i64_r_minMag( float32_t a, bool exact )\r
-{\r
-    union ui32_f32 uA;\r
-    uint_fast32_t uiA;\r
-    int_fast16_t exp;\r
-    uint_fast32_t sig;\r
-    bool sign;\r
-    int_fast16_t shiftCount;\r
-    uint_fast64_t sig64;\r
-    int_fast64_t absZ;\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    exp = expF32UI( uiA );\r
-    sig = fracF32UI( uiA );\r
-    if ( exp < 0x7F ) {\r
-        if ( exact && ( exp | sig ) ) {\r
-            softfloat_exceptionFlags |= softfloat_flag_inexact;\r
-        }\r
-        return 0;\r
-    }\r
-    sign = signF32UI( uiA );\r
-    shiftCount = 0xBE - exp;\r
-    if ( shiftCount <= 0 ) {\r
-        if ( uiA != packToF32UI( 1, 0xBE, 0 ) ) {\r
-            softfloat_raiseFlags( softfloat_flag_invalid );\r
-            if ( ! sign || ( ( exp == 0xFF ) && sig ) ) {\r
-                return INT64_C( 0x7FFFFFFFFFFFFFFF );\r
-            }\r
-        }\r
-        return - INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1;\r
-    }\r
-    sig |= 0x00800000;\r
-    sig64 = (uint_fast64_t) sig<<40;\r
-    absZ = sig64>>shiftCount;\r
-    shiftCount = 40 - shiftCount;\r
-    if (\r
-        exact && ( shiftCount < 0 ) && (uint32_t) ( sig<<( shiftCount & 31 ) )\r
-    ) {\r
-        softfloat_exceptionFlags |= softfloat_flag_inexact;\r
-    }\r
-    return sign ? - absZ : absZ;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/f32_to_ui32.c b/softfloat/SoftFloat-3/source/f32_to_ui32.c
deleted file mode 100755 (executable)
index 3501db8..0000000
--- a/softfloat/SoftFloat-3/source/f32_to_ui32.c
+++ /dev/null
@@ -1,33 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-uint_fast32_t f32_to_ui32( float32_t a, int_fast8_t roundingMode, bool exact )\r
-{\r
-    union ui32_f32 uA;\r
-    uint_fast32_t uiA;\r
-    bool sign;\r
-    int_fast16_t exp;\r
-    uint_fast32_t sig;\r
-    uint_fast64_t sig64;\r
-    int_fast16_t shiftCount;\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    sign = signF32UI( uiA );\r
-    exp = expF32UI( uiA );\r
-    sig = fracF32UI( uiA );\r
-    if ( exp ) sig |= 0x00800000;\r
-    sig64 = (uint_fast64_t) sig<<32;\r
-    shiftCount = 0xAF - exp;\r
-    if ( 0 < shiftCount ) {\r
-        sig64 = softfloat_shift64RightJam( sig64, shiftCount );\r
-    }\r
-    return softfloat_roundPackToUI32( sign, sig64, roundingMode, exact );\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/f32_to_ui32_r_minMag.c b/softfloat/SoftFloat-3/source/f32_to_ui32_r_minMag.c
deleted file mode 100755 (executable)
index edd858d..0000000
--- a/softfloat/SoftFloat-3/source/f32_to_ui32_r_minMag.c
+++ /dev/null
@@ -1,41 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-uint_fast32_t f32_to_ui32_r_minMag( float32_t a, bool exact )\r
-{\r
-    union ui32_f32 uA;\r
-    uint_fast32_t uiA;\r
-    int_fast16_t exp;\r
-    uint_fast32_t sig;\r
-    int_fast16_t shiftCount;\r
-    uint_fast32_t z;\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    exp = expF32UI( uiA );\r
-    sig = fracF32UI( uiA );\r
-    if ( exp < 0x7F ) {\r
-        if ( exact && ( exp | sig ) ) {\r
-            softfloat_exceptionFlags |= softfloat_flag_inexact;\r
-        }\r
-        return 0;\r
-    }\r
-    if ( signF32UI( uiA ) ) goto invalid;\r
-    shiftCount = 0x9E - exp;\r
-    if ( shiftCount < 0 ) goto invalid;\r
-    sig = ( sig | 0x00800000 )<<8;\r
-    z = sig>>shiftCount;\r
-    if ( exact && ( sig & ( ( (uint_fast32_t) 1<<shiftCount ) - 1 ) ) ) {\r
-        softfloat_exceptionFlags |= softfloat_flag_inexact;\r
-    }\r
-    return z;\r
- invalid:\r
-    softfloat_raiseFlags( softfloat_flag_invalid );\r
-    return 0xFFFFFFFF;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/f32_to_ui64.c b/softfloat/SoftFloat-3/source/f32_to_ui64.c
deleted file mode 100755 (executable)
index 6cdcf74..0000000
--- a/softfloat/SoftFloat-3/source/f32_to_ui64.c
+++ /dev/null
@@ -1,42 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-uint_fast64_t f32_to_ui64( float32_t a, int_fast8_t roundingMode, bool exact )\r
-{\r
-    union ui32_f32 uA;\r
-    uint_fast32_t uiA;\r
-    bool sign;\r
-    int_fast16_t exp;\r
-    uint_fast32_t sig;\r
-    int_fast16_t shiftCount;\r
-    uint_fast64_t sig64, extra;\r
-    struct uint64_extra sig64Extra;\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    sign = signF32UI( uiA );\r
-    exp = expF32UI( uiA );\r
-    sig = fracF32UI( uiA );\r
-    shiftCount = 0xBE - exp;\r
-    if ( shiftCount < 0 ) {\r
-        softfloat_raiseFlags( softfloat_flag_invalid );\r
-        return UINT64_C( 0xFFFFFFFFFFFFFFFF );\r
-    }\r
-    if ( exp ) sig |= 0x00800000;\r
-    sig64 = (uint_fast64_t) sig<<40;\r
-    extra = 0;\r
-    if ( shiftCount ) {\r
-        sig64Extra = softfloat_shift64ExtraRightJam( sig64, 0, shiftCount );\r
-        sig64 = sig64Extra.v;\r
-        extra = sig64Extra.extra;\r
-    }\r
-    return\r
-        softfloat_roundPackToUI64( sign, sig64, extra, roundingMode, exact );\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/f32_to_ui64_r_minMag.c b/softfloat/SoftFloat-3/source/f32_to_ui64_r_minMag.c
deleted file mode 100755 (executable)
index 738d6b1..0000000
--- a/softfloat/SoftFloat-3/source/f32_to_ui64_r_minMag.c
+++ /dev/null
@@ -1,45 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-uint_fast64_t f32_to_ui64_r_minMag( float32_t a, bool exact )\r
-{\r
-    union ui32_f32 uA;\r
-    uint_fast32_t uiA;\r
-    int_fast16_t exp;\r
-    uint_fast32_t sig;\r
-    int_fast16_t shiftCount;\r
-    uint_fast64_t sig64, z;\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    exp = expF32UI( uiA );\r
-    sig = fracF32UI( uiA );\r
-    if ( exp < 0x7F ) {\r
-        if ( exact && ( exp | sig ) ) {\r
-            softfloat_exceptionFlags |= softfloat_flag_inexact;\r
-        }\r
-        return 0;\r
-    }\r
-    if ( signF32UI( uiA ) ) goto invalid;\r
-    shiftCount = 0xBE - exp;\r
-    if ( shiftCount < 0 ) goto invalid;\r
-    sig |= 0x00800000;\r
-    sig64 = (uint_fast64_t) sig<<40;\r
-    z = sig64>>shiftCount;\r
-    shiftCount = 40 - shiftCount;\r
-    if (\r
-        exact && ( shiftCount < 0 ) && (uint32_t) ( sig<<( shiftCount & 31 ) )\r
-    ) {\r
-        softfloat_exceptionFlags |= softfloat_flag_inexact;\r
-    }\r
-    return z;\r
- invalid:\r
-    softfloat_raiseFlags( softfloat_flag_invalid );\r
-    return UINT64_C( 0xFFFFFFFFFFFFFFFF );\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/f64_add.c b/softfloat/SoftFloat-3/source/f64_add.c
deleted file mode 100755 (executable)
index 9ec4b5f..0000000
--- a/softfloat/SoftFloat-3/source/f64_add.c
+++ /dev/null
@@ -1,29 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "softfloat.h"
-
-float64_t f64_add( float64_t a, float64_t b )
-{
-    union ui64_f64 uA;
-    uint_fast64_t uiA;
-    bool signA;
-    union ui64_f64 uB;
-    uint_fast64_t uiB;
-    bool signB;
-    float64_t ( *magsRoutine )( uint_fast64_t, uint_fast64_t, bool );
-
-    uA.f = a;
-    uiA = uA.ui;
-    signA = signF64UI( uiA );
-    uB.f = b;
-    uiB = uB.ui;
-    signB = signF64UI( uiB );
-    magsRoutine =
-        ( signA == signB ) ? softfloat_addMagsF64 : softfloat_subMagsF64;
-    return magsRoutine( uiA, uiB, signA );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/f64_div.c b/softfloat/SoftFloat-3/source/f64_div.c
deleted file mode 100755 (executable)
index 9bc72b3..0000000
--- a/softfloat/SoftFloat-3/source/f64_div.c
+++ /dev/null
@@ -1,104 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "primitives.h"
-#include "internals.h"
-#include "specialize.h"
-#include "softfloat.h"
-
-float64_t f64_div( float64_t a, float64_t b )
-{
-    union ui64_f64 uA;
-    uint_fast64_t uiA;
-    bool signA;
-    int_fast16_t expA;
-    uint_fast64_t sigA;
-    union ui64_f64 uB;
-    uint_fast64_t uiB;
-    bool signB;
-    int_fast16_t expB;
-    uint_fast64_t sigB;
-    bool signZ;
-    struct exp16_sig64 normExpSig;
-    int_fast16_t expZ;
-    uint_fast64_t sigZ;
-    struct uint128 term, rem;
-    uint_fast64_t uiZ;
-    union ui64_f64 uZ;
-
-    uA.f = a;
-    uiA = uA.ui;
-    signA = signF64UI( uiA );
-    expA = expF64UI( uiA );
-    sigA = fracF64UI( uiA );
-    uB.f = b;
-    uiB = uB.ui;
-    signB = signF64UI( uiB );
-    expB = expF64UI( uiB );
-    sigB = fracF64UI( uiB );
-    signZ = signA ^ signB;
-    if ( expA == 0x7FF ) {
-        if ( sigA ) goto propagateNaN;
-        if ( expB == 0x7FF ) {
-            if ( sigB ) goto propagateNaN;
-            goto invalid;
-        }
-        goto infinity;
-    }
-    if ( expB == 0x7FF ) {
-        if ( sigB ) goto propagateNaN;
-        goto zero;
-    }
-    if ( ! expB ) {
-        if ( ! sigB ) {
-            if ( ! ( expA | sigA ) ) goto invalid;
-            softfloat_raiseFlags( softfloat_flag_infinity );
-            goto infinity;
-        }
-        normExpSig = softfloat_normSubnormalF64Sig( sigB );
-        expB = normExpSig.exp;
-        sigB = normExpSig.sig;
-    }
-    if ( ! expA ) {
-        if ( ! sigA ) goto zero;
-        normExpSig = softfloat_normSubnormalF64Sig( sigA );
-        expA = normExpSig.exp;
-        sigA = normExpSig.sig;
-    }
-    expZ = expA - expB + 0x3FD;
-    sigA = ( sigA | UINT64_C( 0x0010000000000000 ) )<<10;
-    sigB = ( sigB | UINT64_C( 0x0010000000000000 ) )<<11;
-    if ( sigB <= ( sigA + sigA ) ) {
-        ++expZ;
-        sigA >>= 1;
-    }
-    sigZ = softfloat_estimateDiv128To64( sigA, 0, sigB );
-    if ( ( sigZ & 0x1FF ) <= 2 ) {
-        term = softfloat_mul64To128( sigB, sigZ );
-        rem = softfloat_sub128( sigA, 0, term.v64, term.v0 );
-        while ( UINT64_C( 0x8000000000000000 ) <= rem.v64 ) {
-            --sigZ;
-            rem = softfloat_add128( rem.v64, rem.v0, 0, sigB );
-        }
-        sigZ |= ( rem.v0 != 0 );
-    }
-    return softfloat_roundPackToF64( signZ, expZ, sigZ );
- propagateNaN:
-    uiZ = softfloat_propagateNaNF64UI( uiA, uiB );
-    goto uiZ;
- invalid:
-    softfloat_raiseFlags( softfloat_flag_invalid );
-    uiZ = defaultNaNF64UI;
-    goto uiZ;
- infinity:
-    uiZ = packToF64UI( signZ, 0x7FF, 0 );
-    goto uiZ;
- zero:
-    uiZ = packToF64UI( signZ, 0, 0 );
- uiZ:
-    uZ.ui = uiZ;
-    return uZ.f;
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/f64_eq.c b/softfloat/SoftFloat-3/source/f64_eq.c
deleted file mode 100755 (executable)
index 925aabc..0000000
--- a/softfloat/SoftFloat-3/source/f64_eq.c
+++ /dev/null
@@ -1,35 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "specialize.h"
-#include "softfloat.h"
-
-bool f64_eq( float64_t a, float64_t b )
-{
-    union ui64_f64 uA;
-    uint_fast64_t uiA;
-    union ui64_f64 uB;
-    uint_fast64_t uiB;
-
-    uA.f = a;
-    uiA = uA.ui;
-    uB.f = b;
-    uiB = uB.ui;
-    if (
-           ( ( expF64UI( uiA ) == 0x7FF ) && fracF64UI( uiA ) )
-        || ( ( expF64UI( uiB ) == 0x7FF ) && fracF64UI( uiB ) )
-    ) {
-        if (
-            softfloat_isSigNaNF64UI( uiA ) || softfloat_isSigNaNF64UI( uiB )
-        ) {
-            softfloat_raiseFlags( softfloat_flag_invalid );
-        }
-        return false;
-    }
-    return
-        ( uiA == uiB ) || ! ( ( uiA | uiB ) & UINT64_C( 0x7FFFFFFFFFFFFFFF ) );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/f64_eq_signaling.c b/softfloat/SoftFloat-3/source/f64_eq_signaling.c
deleted file mode 100755 (executable)
index 7a54dc1..0000000
--- a/softfloat/SoftFloat-3/source/f64_eq_signaling.c
+++ /dev/null
@@ -1,30 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "softfloat.h"
-
-bool f64_eq_signaling( float64_t a, float64_t b )
-{
-    union ui64_f64 uA;
-    uint_fast64_t uiA;
-    union ui64_f64 uB;
-    uint_fast64_t uiB;
-
-    uA.f = a;
-    uiA = uA.ui;
-    uB.f = b;
-    uiB = uB.ui;
-    if (
-           ( ( expF64UI( uiA ) == 0x7FF ) && fracF64UI( uiA ) )
-        || ( ( expF64UI( uiB ) == 0x7FF ) && fracF64UI( uiB ) )
-    ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
-        return false;
-    }
-    return
-        ( uiA == uiB ) || ! ( ( uiA | uiB ) & UINT64_C( 0x7FFFFFFFFFFFFFFF ) );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/f64_isSignalingNaN.c b/softfloat/SoftFloat-3/source/f64_isSignalingNaN.c
deleted file mode 100755 (executable)
index d720ac1..0000000
--- a/softfloat/SoftFloat-3/source/f64_isSignalingNaN.c
+++ /dev/null
@@ -1,16 +0,0 @@
-
-#include <stdbool.h>
-#include "platform.h"
-#include "internals.h"
-#include "specialize.h"
-#include "softfloat.h"
-
-bool f64_isSignalingNaN( float64_t a )
-{
-    union ui64_f64 uA;
-
-    uA.f = a;
-    return softfloat_isSigNaNF64UI( uA.ui );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/f64_le.c b/softfloat/SoftFloat-3/source/f64_le.c
deleted file mode 100755 (executable)
index e6c5caf..0000000
--- a/softfloat/SoftFloat-3/source/f64_le.c
+++ /dev/null
@@ -1,35 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "softfloat.h"
-
-bool f64_le( float64_t a, float64_t b )
-{
-    union ui64_f64 uA;
-    uint_fast64_t uiA;
-    union ui64_f64 uB;
-    uint_fast64_t uiB;
-    bool signA, signB;
-
-    uA.f = a;
-    uiA = uA.ui;
-    uB.f = b;
-    uiB = uB.ui;
-    if (
-           ( ( expF64UI( uiA ) == 0x7FF ) && fracF64UI( uiA ) )
-        || ( ( expF64UI( uiB ) == 0x7FF ) && fracF64UI( uiB ) )
-    ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
-        return false;
-    }
-    signA = signF64UI( uiA );
-    signB = signF64UI( uiB );
-    return
-        ( signA != signB )
-            ? signA || ! ( ( uiA | uiB ) & UINT64_C( 0x7FFFFFFFFFFFFFFF ) )
-            : ( uiA == uiB ) || ( signA ^ ( uiA < uiB ) );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/f64_le_quiet.c b/softfloat/SoftFloat-3/source/f64_le_quiet.c
deleted file mode 100755 (executable)
index e9b7ede..0000000
--- a/softfloat/SoftFloat-3/source/f64_le_quiet.c
+++ /dev/null
@@ -1,40 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "specialize.h"
-#include "softfloat.h"
-
-bool f64_le_quiet( float64_t a, float64_t b )
-{
-    union ui64_f64 uA;
-    uint_fast64_t uiA;
-    union ui64_f64 uB;
-    uint_fast64_t uiB;
-    bool signA, signB;
-
-    uA.f = a;
-    uiA = uA.ui;
-    uB.f = b;
-    uiB = uB.ui;
-    if (
-           ( ( expF64UI( uiA ) == 0x7FF ) && fracF64UI( uiA ) )
-        || ( ( expF64UI( uiB ) == 0x7FF ) && fracF64UI( uiB ) )
-    ) {
-        if (
-            softfloat_isSigNaNF64UI( uiA ) || softfloat_isSigNaNF64UI( uiB )
-        ) {
-            softfloat_raiseFlags( softfloat_flag_invalid );
-        }
-        return false;
-    }
-    signA = signF64UI( uiA );
-    signB = signF64UI( uiB );
-    return
-        ( signA != signB )
-            ? signA || ! ( ( uiA | uiB ) & UINT64_C( 0x7FFFFFFFFFFFFFFF ) )
-            : ( uiA == uiB ) || ( signA ^ ( uiA < uiB ) );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/f64_lt.c b/softfloat/SoftFloat-3/source/f64_lt.c
deleted file mode 100755 (executable)
index 1b2f696..0000000
--- a/softfloat/SoftFloat-3/source/f64_lt.c
+++ /dev/null
@@ -1,35 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "softfloat.h"
-
-bool f64_lt( float64_t a, float64_t b )
-{
-    union ui64_f64 uA;
-    uint_fast64_t uiA;
-    union ui64_f64 uB;
-    uint_fast64_t uiB;
-    bool signA, signB;
-
-    uA.f = a;
-    uiA = uA.ui;
-    uB.f = b;
-    uiB = uB.ui;
-    if (
-           ( ( expF64UI( uiA ) == 0x7FF ) && fracF64UI( uiA ) )
-        || ( ( expF64UI( uiB ) == 0x7FF ) && fracF64UI( uiB ) )
-    ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
-        return false;
-    }
-    signA = signF64UI( uiA );
-    signB = signF64UI( uiB );
-    return
-        ( signA != signB )
-            ? signA && ( ( uiA | uiB ) & UINT64_C( 0x7FFFFFFFFFFFFFFF ) )
-            : ( uiA != uiB ) && ( signA ^ ( uiA < uiB ) );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/f64_lt_quiet.c b/softfloat/SoftFloat-3/source/f64_lt_quiet.c
deleted file mode 100755 (executable)
index f27e6da..0000000
--- a/softfloat/SoftFloat-3/source/f64_lt_quiet.c
+++ /dev/null
@@ -1,40 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "specialize.h"
-#include "softfloat.h"
-
-bool f64_lt_quiet( float64_t a, float64_t b )
-{
-    union ui64_f64 uA;
-    uint_fast64_t uiA;
-    union ui64_f64 uB;
-    uint_fast64_t uiB;
-    bool signA, signB;
-
-    uA.f = a;
-    uiA = uA.ui;
-    uB.f = b;
-    uiB = uB.ui;
-    if (
-           ( ( expF64UI( uiA ) == 0x7FF ) && fracF64UI( uiA ) )
-        || ( ( expF64UI( uiB ) == 0x7FF ) && fracF64UI( uiB ) )
-    ) {
-        if (
-            softfloat_isSigNaNF64UI( uiA ) || softfloat_isSigNaNF64UI( uiB )
-        ) {
-            softfloat_raiseFlags( softfloat_flag_invalid );
-        }
-        return false;
-    }
-    signA = signF64UI( uiA );
-    signB = signF64UI( uiB );
-    return
-        ( signA != signB )
-            ? signA && ( ( uiA | uiB ) & UINT64_C( 0x7FFFFFFFFFFFFFFF ) )
-            : ( uiA != uiB ) && ( signA ^ ( uiA < uiB ) );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/f64_mul.c b/softfloat/SoftFloat-3/source/f64_mul.c
deleted file mode 100755 (executable)
index 4b5dc4e..0000000
--- a/softfloat/SoftFloat-3/source/f64_mul.c
+++ /dev/null
@@ -1,91 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-#include "specialize.h"\r
-#include "softfloat.h"\r
-\r
-float64_t f64_mul( float64_t a, float64_t b )\r
-{\r
-    union ui64_f64 uA;\r
-    uint_fast64_t uiA;\r
-    bool signA;\r
-    int_fast16_t expA;\r
-    uint_fast64_t sigA;\r
-    union ui64_f64 uB;\r
-    uint_fast64_t uiB;\r
-    bool signB;\r
-    int_fast16_t expB;\r
-    uint_fast64_t sigB;\r
-    bool signZ;\r
-    uint_fast64_t magBits;\r
-    struct exp16_sig64 normExpSig;\r
-    int_fast16_t expZ;\r
-    struct uint128 sigZ128;\r
-    uint_fast64_t sigZ, uiZ;\r
-    union ui64_f64 uZ;\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    signA = signF64UI( uiA );\r
-    expA = expF64UI( uiA );\r
-    sigA = fracF64UI( uiA );\r
-    uB.f = b;\r
-    uiB = uB.ui;\r
-    signB = signF64UI( uiB );\r
-    expB = expF64UI( uiB );\r
-    sigB = fracF64UI( uiB );\r
-    signZ = signA ^ signB;\r
-    if ( expA == 0x7FF ) {\r
-        if ( sigA || ( ( expB == 0x7FF ) && sigB ) ) goto propagateNaN;\r
-        magBits = expB | sigB;\r
-        goto infArg;\r
-    }\r
-    if ( expB == 0x7FF ) {\r
-        if ( sigB ) goto propagateNaN;\r
-        magBits = expA | sigA;\r
-        goto infArg;\r
-    }\r
-    if ( ! expA ) {\r
-        if ( ! sigA ) goto zero;\r
-        normExpSig = softfloat_normSubnormalF64Sig( sigA );\r
-        expA = normExpSig.exp;\r
-        sigA = normExpSig.sig;\r
-    }\r
-    if ( ! expB ) {\r
-        if ( ! sigB ) goto zero;\r
-        normExpSig = softfloat_normSubnormalF64Sig( sigB );\r
-        expB = normExpSig.exp;\r
-        sigB = normExpSig.sig;\r
-    }\r
-    expZ = expA + expB - 0x3FF;\r
-    sigA = ( sigA | UINT64_C( 0x0010000000000000 ) )<<10;\r
-    sigB = ( sigB | UINT64_C( 0x0010000000000000 ) )<<11;\r
-    sigZ128 = softfloat_mul64To128( sigA, sigB );\r
-    sigZ = sigZ128.v64 | ( sigZ128.v0 != 0 );\r
-    if ( sigZ < UINT64_C( 0x4000000000000000 ) ) {\r
-        --expZ;\r
-        sigZ <<= 1;\r
-    }\r
-    return softfloat_roundPackToF64( signZ, expZ, sigZ );\r
- propagateNaN:\r
-    uiZ = softfloat_propagateNaNF64UI( uiA, uiB );\r
-    goto uiZ;\r
- infArg:\r
-    if ( ! magBits ) {\r
-        softfloat_raiseFlags( softfloat_flag_invalid );\r
-        uiZ = defaultNaNF64UI;\r
-    } else {\r
-        uiZ = packToF64UI( signZ, 0x7FF, 0 );\r
-    }\r
-    goto uiZ;\r
- zero:\r
-    uiZ = packToF64UI( signZ, 0, 0 );\r
- uiZ:\r
-    uZ.ui = uiZ;\r
-    return uZ.f;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/f64_mulAdd.c b/softfloat/SoftFloat-3/source/f64_mulAdd.c
deleted file mode 100755 (executable)
index fa1669a..0000000
--- a/softfloat/SoftFloat-3/source/f64_mulAdd.c
+++ /dev/null
@@ -1,25 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-float64_t f64_mulAdd( float64_t a, float64_t b, float64_t c )\r
-{\r
-    union ui64_f64 uA;\r
-    uint_fast64_t uiA;\r
-    union ui64_f64 uB;\r
-    uint_fast64_t uiB;\r
-    union ui64_f64 uC;\r
-    uint_fast64_t uiC;\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    uB.f = b;\r
-    uiB = uB.ui;\r
-    uC.f = c;\r
-    uiC = uC.ui;\r
-    return softfloat_mulAddF64( 0, uiA, uiB, uiC );\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/f64_rem.c b/softfloat/SoftFloat-3/source/f64_rem.c
deleted file mode 100755 (executable)
index 08fcd78..0000000
--- a/softfloat/SoftFloat-3/source/f64_rem.c
+++ /dev/null
@@ -1,113 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "primitives.h"
-#include "internals.h"
-#include "specialize.h"
-#include "softfloat.h"
-
-float64_t f64_rem( float64_t a, float64_t b )
-{
-    union ui64_f64 uA;
-    uint_fast64_t uiA;
-    bool signA;
-    int_fast16_t expA;
-    uint_fast64_t sigA;
-    union ui64_f64 uB;
-    uint_fast64_t uiB;
-    bool signB;
-    int_fast16_t expB;
-    uint_fast64_t sigB;
-    struct exp16_sig64 normExpSig;
-    int_fast16_t expDiff;
-    uint_fast64_t q, alternateSigA;
-    uint64_t sigMean;
-    bool signZ;
-    uint_fast64_t uiZ;
-    union ui64_f64 uZ;
-
-    uA.f = a;
-    uiA = uA.ui;
-    signA = signF64UI( uiA );
-    expA = expF64UI( uiA );
-    sigA = fracF64UI( uiA );
-    uB.f = b;
-    uiB = uB.ui;
-    signB = signF64UI( uiB );
-    expB = expF64UI( uiB );
-    sigB = fracF64UI( uiB );
-    if ( expA == 0x7FF ) {
-        if ( sigA || ( ( expB == 0x7FF ) && sigB ) ) goto propagateNaN;
-        goto invalid;
-    }
-    if ( expB == 0x7FF ) {
-        if ( sigB ) goto propagateNaN;
-        return a;
-    }
-    if ( ! expB ) {
-        if ( ! sigB ) goto invalid;
-        normExpSig = softfloat_normSubnormalF64Sig( sigB );
-        expB = normExpSig.exp;
-        sigB = normExpSig.sig;
-    }
-    if ( ! expA ) {
-        if ( ! sigA ) return a;
-        normExpSig = softfloat_normSubnormalF64Sig( sigA );
-        expA = normExpSig.exp;
-        sigA = normExpSig.sig;
-    }
-    expDiff = expA - expB;
-    sigA = ( sigA | UINT64_C( 0x0010000000000000 ) )<<11;
-    sigB = ( sigB | UINT64_C( 0x0010000000000000 ) )<<11;
-    if ( expDiff < 0 ) {
-        if ( expDiff < -1 ) return a;
-        sigA >>= 1;
-    }
-    q = ( sigB <= sigA );
-    if ( q ) sigA -= sigB;
-    expDiff -= 64;
-    while ( 0 < expDiff ) {
-        q = softfloat_estimateDiv128To64( sigA, 0, sigB );
-        q = ( 2 < q ) ? q - 2 : 0;
-        sigA = - ( ( sigB>>2 ) * q );
-        expDiff -= 62;
-    }
-    expDiff += 64;
-    if ( 0 < expDiff ) {
-        q = softfloat_estimateDiv128To64( sigA, 0, sigB );
-        q = ( 2 < q ) ? q - 2 : 0;
-        q >>= 64 - expDiff;
-        sigB >>= 2;
-        sigA = ( ( sigA>>1 )<<( expDiff - 1 ) ) - sigB * q;
-    } else {
-        sigA >>= 2;
-        sigB >>= 2;
-    }
-    do {
-        alternateSigA = sigA;
-        ++q;
-        sigA -= sigB;
-    } while ( sigA < UINT64_C( 0x8000000000000000 ) );
-    sigMean = sigA + alternateSigA;
-    if (
-        ( UINT64_C( 0x8000000000000000 ) <= sigMean )
-            || ( ! sigMean && ( q & 1 ) )
-    ) {
-        sigA = alternateSigA;
-    }
-    signZ = ( UINT64_C( 0x8000000000000000 ) <= sigA );
-    if ( signZ ) sigA = - sigA;
-    return softfloat_normRoundPackToF64( signA ^ signZ, expB, sigA );
- propagateNaN:
-    uiZ = softfloat_propagateNaNF64UI( uiA, uiB );
-    goto uiZ;
- invalid:
-    softfloat_raiseFlags( softfloat_flag_invalid );
-    uiZ = defaultNaNF64UI;
- uiZ:
-    uZ.ui = uiZ;
-    return uZ.f;
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/f64_roundToInt.c b/softfloat/SoftFloat-3/source/f64_roundToInt.c
deleted file mode 100755 (executable)
index ef16dfa..0000000
--- a/softfloat/SoftFloat-3/source/f64_roundToInt.c
+++ /dev/null
@@ -1,80 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "specialize.h"
-#include "softfloat.h"
-
-float64_t f64_roundToInt( float64_t a, int_fast8_t roundingMode, bool exact )
-{
-    union ui64_f64 uA;
-    uint_fast64_t uiA;
-    int_fast16_t expA;
-    uint_fast64_t uiZ;
-    bool signA;
-    uint_fast64_t lastBitMask, roundBitsMask;
-    union ui64_f64 uZ;
-
-    uA.f = a;
-    uiA = uA.ui;
-    expA = expF64UI( uiA );
-    if ( 0x433 <= expA ) {
-        if ( ( expA == 0x7FF ) && fracF64UI( uiA ) ) {
-            uiZ = softfloat_propagateNaNF64UI( uiA, 0 );
-            goto uiZ;
-        }
-        return a;
-    }
-    if ( expA <= 0x3FE ) {
-        if ( ! ( uiA & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) ) return a;
-        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
-        signA = signF64UI( uiA );
-        switch ( roundingMode ) {
-         case softfloat_round_nearest_even:
-            if ( ( expA == 0x3FE ) && fracF64UI( uiA ) ) {
-                uiZ = packToF64UI( signA, 0x3FF, 0 );
-                goto uiZ;
-            }
-            break;
-         case softfloat_round_min:
-            uiZ = signA ? UINT64_C( 0xBFF0000000000000 ) : 0;
-            goto uiZ;
-         case softfloat_round_max:
-            uiZ =
-                signA ? UINT64_C( 0x8000000000000000 )
-                    : UINT64_C( 0x3FF0000000000000 );
-            goto uiZ;
-         case softfloat_round_nearest_maxMag:
-            if ( expA == 0x3FE ) {
-                uiZ = packToF64UI( signA, 0x3FF, 0 );
-                goto uiZ;
-            }
-            break;
-        }
-        uiZ = packToF64UI( signA, 0, 0 );
-        goto uiZ;
-    }
-    lastBitMask = (uint_fast64_t) 1<<( 0x433 - expA );
-    roundBitsMask = lastBitMask - 1;
-    uiZ = uiA;
-    if ( roundingMode == softfloat_round_nearest_maxMag ) {
-        uiZ += lastBitMask>>1;
-    } else if ( roundingMode == softfloat_round_nearest_even ) {
-        uiZ += lastBitMask>>1;
-        if ( ! ( uiZ & roundBitsMask ) ) uiZ &= ~ lastBitMask;
-    } else if ( roundingMode != softfloat_round_minMag ) {
-        if ( signF64UI( uiZ ) ^ ( roundingMode == softfloat_round_max ) ) {
-            uiZ += roundBitsMask;
-        }
-    }
-    uiZ &= ~ roundBitsMask;
-    if ( exact && ( uiZ != uiA ) ) {
-        softfloat_exceptionFlags |= softfloat_flag_inexact;
-    }
- uiZ:
-    uZ.ui = uiZ;
-    return uZ.f;
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/f64_sqrt.c b/softfloat/SoftFloat-3/source/f64_sqrt.c
deleted file mode 100755 (executable)
index cd91010..0000000
--- a/softfloat/SoftFloat-3/source/f64_sqrt.c
+++ /dev/null
@@ -1,74 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-#include "specialize.h"\r
-#include "softfloat.h"\r
-\r
-float64_t f64_sqrt( float64_t a )\r
-{\r
-    union ui64_f64 uA;\r
-    uint_fast64_t uiA;\r
-    bool signA;\r
-    int_fast16_t expA;\r
-    uint_fast64_t sigA, uiZ;\r
-    struct exp16_sig64 normExpSig;\r
-    int_fast16_t expZ;\r
-    uint_fast32_t sigZ32;\r
-    uint_fast64_t sigZ;\r
-    struct uint128 term, rem;\r
-    union ui64_f64 uZ;\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    signA = signF64UI( uiA );\r
-    expA = expF64UI( uiA );\r
-    sigA = fracF64UI( uiA );\r
-    if ( expA == 0x7FF ) {\r
-        if ( sigA ) {\r
-            uiZ = softfloat_propagateNaNF64UI( uiA, 0 );\r
-            goto uiZ;\r
-        }\r
-        if ( ! signA ) return a;\r
-        goto invalid;\r
-    }\r
-    if ( signA ) {\r
-        if ( ! ( expA | sigA ) ) return a;\r
-        goto invalid;\r
-    }\r
-    if ( ! expA ) {\r
-        if ( ! sigA ) return a;\r
-        normExpSig = softfloat_normSubnormalF64Sig( sigA );\r
-        expA = normExpSig.exp;\r
-        sigA = normExpSig.sig;\r
-    }\r
-    expZ = ( ( expA - 0x3FF )>>1 ) + 0x3FE;\r
-    sigA |= UINT64_C( 0x0010000000000000 );\r
-    sigZ32 = softfloat_estimateSqrt32( expA, sigA>>21 );\r
-    sigA <<= 9 - ( expA & 1 );\r
-    sigZ =\r
-        softfloat_estimateDiv128To64( sigA, 0, (uint_fast64_t) sigZ32<<32 )\r
-            + ( (uint_fast64_t) sigZ32<<30 );\r
-    if ( ( sigZ & 0x1FF ) <= 5 ) {\r
-        term = softfloat_mul64To128( sigZ, sigZ );\r
-        rem = softfloat_sub128( sigA, 0, term.v64, term.v0 );\r
-        while ( UINT64_C( 0x8000000000000000 ) <= rem.v64 ) {\r
-            --sigZ;\r
-            rem =\r
-                softfloat_add128(\r
-                    rem.v64, rem.v0, sigZ>>63, (uint64_t) ( sigZ<<1 ) );\r
-        }\r
-        sigZ |= ( ( rem.v64 | rem.v0 ) != 0 );\r
-    }\r
-    return softfloat_roundPackToF64( 0, expZ, sigZ );\r
- invalid:\r
-    softfloat_raiseFlags( softfloat_flag_invalid );\r
-    uiZ = defaultNaNF64UI;\r
- uiZ:\r
-    uZ.ui = uiZ;\r
-    return uZ.f;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/f64_sub.c b/softfloat/SoftFloat-3/source/f64_sub.c
deleted file mode 100755 (executable)
index 38bd574..0000000
--- a/softfloat/SoftFloat-3/source/f64_sub.c
+++ /dev/null
@@ -1,29 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "softfloat.h"
-
-float64_t f64_sub( float64_t a, float64_t b )
-{
-    union ui64_f64 uA;
-    uint_fast64_t uiA;
-    bool signA;
-    union ui64_f64 uB;
-    uint_fast64_t uiB;
-    bool signB;
-    float64_t ( *magsRoutine )( uint_fast64_t, uint_fast64_t, bool );
-
-    uA.f = a;
-    uiA = uA.ui;
-    signA = signF64UI( uiA );
-    uB.f = b;
-    uiB = uB.ui;
-    signB = signF64UI( uiB );
-    magsRoutine =
-        ( signA == signB ) ? softfloat_subMagsF64 : softfloat_addMagsF64;
-    return magsRoutine( uiA, uiB, signA );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/f64_to_f32.c b/softfloat/SoftFloat-3/source/f64_to_f32.c
deleted file mode 100755 (executable)
index 395d6c6..0000000
--- a/softfloat/SoftFloat-3/source/f64_to_f32.c
+++ /dev/null
@@ -1,43 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-#include "specialize.h"\r
-#include "softfloat.h"\r
-\r
-float32_t f64_to_f32( float64_t a )\r
-{\r
-    union ui64_f64 uA;\r
-    uint_fast64_t uiA;\r
-    bool sign;\r
-    int_fast16_t exp;\r
-    uint_fast64_t sig;\r
-    uint_fast32_t uiZ, sig32;\r
-    union ui32_f32 uZ;\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    sign = signF64UI( uiA );\r
-    exp = expF64UI( uiA );\r
-    sig = fracF64UI( uiA );\r
-    if ( exp == 0x7FF ) {\r
-        uiZ =\r
-            sig ? softfloat_commonNaNToF32UI(\r
-                      softfloat_f64UIToCommonNaN( uiA ) )\r
-                : packToF32UI( sign, 0xFF, 0 );\r
-        goto uiZ;\r
-    }\r
-    sig32 = softfloat_shortShift64RightJam( sig, 22 );\r
-    if ( ! ( exp | sig32 ) ) {\r
-        uiZ = packToF32UI( sign, 0, 0 );\r
-        goto uiZ;\r
-    }\r
-    return softfloat_roundPackToF32( sign, exp - 0x381, sig32 | 0x40000000 );\r
- uiZ:\r
-    uZ.ui = uiZ;\r
-    return uZ.f;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/f64_to_i32.c b/softfloat/SoftFloat-3/source/f64_to_i32.c
deleted file mode 100755 (executable)
index 0778a86..0000000
--- a/softfloat/SoftFloat-3/source/f64_to_i32.c
+++ /dev/null
@@ -1,30 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-int_fast32_t f64_to_i32( float64_t a, int_fast8_t roundingMode, bool exact )\r
-{\r
-    union ui64_f64 uA;\r
-    uint_fast64_t uiA;\r
-    bool sign;\r
-    int_fast16_t exp;\r
-    uint_fast64_t sig;\r
-    int_fast16_t shiftCount;\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    sign = signF64UI( uiA );\r
-    exp = expF64UI( uiA );\r
-    sig = fracF64UI( uiA );\r
-    if ( ( exp == 0x7FF ) && sig ) sign = 0;\r
-    if ( exp ) sig |= UINT64_C( 0x0010000000000000 );\r
-    shiftCount = 0x42C - exp;\r
-    if ( 0 < shiftCount ) sig = softfloat_shift64RightJam( sig, shiftCount );\r
-    return softfloat_roundPackToI32( sign, sig, roundingMode, exact );\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/f64_to_i32_r_minMag.c b/softfloat/SoftFloat-3/source/f64_to_i32_r_minMag.c
deleted file mode 100755 (executable)
index 39246c2..0000000
--- a/softfloat/SoftFloat-3/source/f64_to_i32_r_minMag.c
+++ /dev/null
@@ -1,50 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-int_fast32_t f64_to_i32_r_minMag( float64_t a, bool exact )\r
-{\r
-    union ui64_f64 uA;\r
-    uint_fast64_t uiA;\r
-    int_fast16_t exp;\r
-    uint_fast64_t sig;\r
-    bool sign;\r
-    int_fast16_t shiftCount;\r
-    uint_fast32_t absZ;\r
-    union { uint32_t ui; int32_t i; } uZ;\r
-    int_fast32_t z;\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    exp = expF64UI( uiA );\r
-    sig = fracF64UI( uiA );\r
-    if ( exp < 0x3FF ) {\r
-        if ( exact && ( exp | sig ) ) {\r
-            softfloat_exceptionFlags |= softfloat_flag_inexact;\r
-        }\r
-        return 0;\r
-    }\r
-    sign = signF64UI( uiA );\r
-    if ( 0x41E < exp ) {\r
-        if ( ( exp == 0x7FF ) && sig ) sign = 0;\r
-        goto invalid;\r
-    }\r
-    sig |= UINT64_C( 0x0010000000000000 );\r
-    shiftCount = 0x433 - exp;\r
-    absZ = sig>>shiftCount;\r
-    uZ.ui = sign ? - absZ : absZ;\r
-    z = uZ.i;\r
-    if ( ( z < 0 ) != sign ) goto invalid;\r
-    if ( exact && ( (uint_fast64_t) absZ<<shiftCount != sig ) ) {\r
-        softfloat_exceptionFlags |= softfloat_flag_inexact;\r
-    }\r
-    return z;\r
- invalid:\r
-    softfloat_raiseFlags( softfloat_flag_invalid );\r
-    return sign ? -0x7FFFFFFF - 1 : 0x7FFFFFFF;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/f64_to_i64.c b/softfloat/SoftFloat-3/source/f64_to_i64.c
deleted file mode 100755 (executable)
index 89663ee..0000000
--- a/softfloat/SoftFloat-3/source/f64_to_i64.c
+++ /dev/null
@@ -1,46 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-int_fast64_t f64_to_i64( float64_t a, int_fast8_t roundingMode, bool exact )\r
-{\r
-    union ui64_f64 uA;\r
-    uint_fast64_t uiA;\r
-    bool sign;\r
-    int_fast16_t exp;\r
-    uint_fast64_t sig;\r
-    int_fast16_t shiftCount;\r
-    struct uint64_extra sigExtra;\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    sign = signF64UI( uiA );\r
-    exp = expF64UI( uiA );\r
-    sig = fracF64UI( uiA );\r
-    if ( exp ) sig |= UINT64_C( 0x0010000000000000 );\r
-    shiftCount = 0x433 - exp;\r
-    if ( shiftCount <= 0 ) {\r
-        if ( 0x43E < exp ) {\r
-            softfloat_raiseFlags( softfloat_flag_invalid );\r
-            return\r
-                ! sign\r
-                    || ( ( exp == 0x7FF )\r
-                             && ( sig != UINT64_C( 0x0010000000000000 ) ) )\r
-                    ? INT64_C( 0x7FFFFFFFFFFFFFFF )\r
-                    : - INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1;\r
-        }\r
-        sigExtra.v = sig<<( - shiftCount );\r
-        sigExtra.extra = 0;\r
-    } else {\r
-        sigExtra = softfloat_shift64ExtraRightJam( sig, 0, shiftCount );\r
-    }\r
-    return\r
-        softfloat_roundPackToI64(\r
-            sign, sigExtra.v, sigExtra.extra, roundingMode, exact );\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/f64_to_i64_r_minMag.c b/softfloat/SoftFloat-3/source/f64_to_i64_r_minMag.c
deleted file mode 100755 (executable)
index 525705b..0000000
--- a/softfloat/SoftFloat-3/source/f64_to_i64_r_minMag.c
+++ /dev/null
@@ -1,52 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-int_fast64_t f64_to_i64_r_minMag( float64_t a, bool exact )\r
-{\r
-    union ui64_f64 uA;\r
-    uint_fast64_t uiA;\r
-    bool sign;\r
-    int_fast16_t exp;\r
-    uint_fast64_t sig;\r
-    int_fast16_t shiftCount;\r
-    int_fast64_t absZ;\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    sign = signF64UI( uiA );\r
-    exp = expF64UI( uiA );\r
-    sig = fracF64UI( uiA );\r
-    shiftCount = exp - 0x433;\r
-    if ( 0 <= shiftCount ) {\r
-        if ( 0x43E <= exp ) {\r
-            if ( uiA != packToF64UI( 1, 0x43E, 0 ) ) {\r
-                softfloat_raiseFlags( softfloat_flag_invalid );\r
-                if ( ! sign || ( ( exp == 0x7FF ) && sig ) ) {\r
-                    return INT64_C( 0x7FFFFFFFFFFFFFFF );\r
-                }\r
-            }\r
-            return - INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1;\r
-        }\r
-        sig |= UINT64_C( 0x0010000000000000 );\r
-        absZ = sig<<shiftCount;\r
-    } else {\r
-        if ( exp < 0x3FF ) {\r
-            if ( exact && ( exp | sig ) ) {\r
-                softfloat_exceptionFlags |= softfloat_flag_inexact;\r
-            }\r
-            return 0;\r
-        }\r
-        sig |= UINT64_C( 0x0010000000000000 );\r
-        absZ = sig>>( - shiftCount );\r
-        if ( exact && (uint64_t) ( sig<<( shiftCount & 63 ) ) ) {\r
-            softfloat_exceptionFlags |= softfloat_flag_inexact;\r
-        }\r
-    }\r
-    return sign ? - absZ : absZ;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/f64_to_ui32.c b/softfloat/SoftFloat-3/source/f64_to_ui32.c
deleted file mode 100755 (executable)
index b186605..0000000
--- a/softfloat/SoftFloat-3/source/f64_to_ui32.c
+++ /dev/null
@@ -1,29 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-uint_fast32_t f64_to_ui32( float64_t a, int_fast8_t roundingMode, bool exact )\r
-{\r
-    union ui64_f64 uA;\r
-    uint_fast64_t uiA;\r
-    bool sign;\r
-    int_fast16_t exp;\r
-    uint_fast64_t sig;\r
-    int_fast16_t shiftCount;\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    sign = signF64UI( uiA );\r
-    exp = expF64UI( uiA );\r
-    sig = fracF64UI( uiA );\r
-    if ( exp ) sig |= UINT64_C( 0x0010000000000000 );\r
-    shiftCount = 0x42C - exp;\r
-    if ( 0 < shiftCount ) sig = softfloat_shift64RightJam( sig, shiftCount );\r
-    return softfloat_roundPackToUI32( sign, sig, roundingMode, exact );\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/f64_to_ui32_r_minMag.c b/softfloat/SoftFloat-3/source/f64_to_ui32_r_minMag.c
deleted file mode 100755 (executable)
index 9f1dd4d..0000000
--- a/softfloat/SoftFloat-3/source/f64_to_ui32_r_minMag.c
+++ /dev/null
@@ -1,40 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-uint_fast32_t f64_to_ui32_r_minMag( float64_t a, bool exact )\r
-{\r
-    union ui64_f64 uA;\r
-    uint_fast64_t uiA;\r
-    int_fast16_t exp;\r
-    uint_fast64_t sig;\r
-    int_fast16_t shiftCount;\r
-    uint_fast32_t z;\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    exp = expF64UI( uiA );\r
-    sig = fracF64UI( uiA );\r
-    if ( exp < 0x3FF ) {\r
-        if ( exact && ( exp | sig ) ) {\r
-            softfloat_exceptionFlags |= softfloat_flag_inexact;\r
-        }\r
-        return 0;\r
-    }\r
-    if ( signF64UI( uiA ) || ( 0x41E < exp ) ) {\r
-        softfloat_raiseFlags( softfloat_flag_invalid );\r
-        return 0xFFFFFFFF;\r
-    }\r
-    sig |= UINT64_C( 0x0010000000000000 );\r
-    shiftCount = 0x433 - exp;\r
-    z = sig>>shiftCount;\r
-    if ( exact && ( (uint_fast64_t) z<<shiftCount != sig ) ) {\r
-        softfloat_exceptionFlags |= softfloat_flag_inexact;\r
-    }\r
-    return z;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/f64_to_ui64.c b/softfloat/SoftFloat-3/source/f64_to_ui64.c
deleted file mode 100755 (executable)
index 9afebd7..0000000
--- a/softfloat/SoftFloat-3/source/f64_to_ui64.c
+++ /dev/null
@@ -1,41 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-uint_fast64_t f64_to_ui64( float64_t a, int_fast8_t roundingMode, bool exact )\r
-{\r
-    union ui64_f64 uA;\r
-    uint_fast64_t uiA;\r
-    bool sign;\r
-    int_fast16_t exp;\r
-    uint_fast64_t sig;\r
-    int_fast16_t shiftCount;\r
-    struct uint64_extra sigExtra;\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    sign = signF64UI( uiA );\r
-    exp = expF64UI( uiA );\r
-    sig = fracF64UI( uiA );\r
-    if ( exp ) sig |= UINT64_C( 0x0010000000000000 );\r
-    shiftCount = 0x433 - exp;\r
-    if ( shiftCount <= 0 ) {\r
-        if ( 0x43E < exp ) {\r
-            softfloat_raiseFlags( softfloat_flag_invalid );\r
-            return UINT64_C( 0xFFFFFFFFFFFFFFFF );\r
-        }\r
-        sigExtra.v = sig<<( - shiftCount );\r
-        sigExtra.extra = 0;\r
-    } else {\r
-        sigExtra = softfloat_shift64ExtraRightJam( sig, 0, shiftCount );\r
-    }\r
-    return\r
-        softfloat_roundPackToUI64(\r
-            sign, sigExtra.v, sigExtra.extra, roundingMode, exact );\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/f64_to_ui64_r_minMag.c b/softfloat/SoftFloat-3/source/f64_to_ui64_r_minMag.c
deleted file mode 100755 (executable)
index a66d3ff..0000000
--- a/softfloat/SoftFloat-3/source/f64_to_ui64_r_minMag.c
+++ /dev/null
@@ -1,45 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-uint_fast64_t f64_to_ui64_r_minMag( float64_t a, bool exact )\r
-{\r
-    union ui64_f64 uA;\r
-    uint_fast64_t uiA;\r
-    int_fast16_t exp;\r
-    uint_fast64_t sig;\r
-    int_fast16_t shiftCount;\r
-    uint_fast64_t z;\r
-\r
-    uA.f = a;\r
-    uiA = uA.ui;\r
-    exp = expF64UI( uiA );\r
-    sig = fracF64UI( uiA );\r
-    if ( exp < 0x3FF ) {\r
-        if ( exact && ( exp | sig ) ) {\r
-            softfloat_exceptionFlags |= softfloat_flag_inexact;\r
-        }\r
-        return 0;\r
-    }\r
-    if ( signF64UI( uiA ) ) goto invalid;\r
-    shiftCount = exp - 0x433;\r
-    if ( 0 <= shiftCount ) {\r
-        if ( 0x43E < exp ) goto invalid;\r
-        z = ( sig | UINT64_C( 0x0010000000000000 ) )<<shiftCount;\r
-    } else {\r
-        sig |= UINT64_C( 0x0010000000000000 );\r
-        z = sig>>( - shiftCount );\r
-        if ( exact && (uint64_t) ( sig<<( shiftCount & 63 ) ) ) {\r
-            softfloat_exceptionFlags |= softfloat_flag_inexact;\r
-        }\r
-    }\r
-    return z;\r
- invalid:\r
-    softfloat_raiseFlags( softfloat_flag_invalid );\r
-    return UINT64_C( 0xFFFFFFFFFFFFFFFF );\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/i32_to_f32.c b/softfloat/SoftFloat-3/source/i32_to_f32.c
deleted file mode 100755 (executable)
index f51facd..0000000
--- a/softfloat/SoftFloat-3/source/i32_to_f32.c
+++ /dev/null
@@ -1,21 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-float32_t i32_to_f32( int_fast32_t a )\r
-{\r
-    bool sign;\r
-    union ui32_f32 uZ;\r
-\r
-    sign = ( a < 0 );\r
-    if ( ! ( a & 0x7FFFFFFF ) ) {\r
-        uZ.ui = sign ? packToF32UI( 1, 0x9E, 0 ) : 0;\r
-        return uZ.f;\r
-    }\r
-    return softfloat_normRoundPackToF32( sign, 0x9C, sign ? - a : a );\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/i32_to_f64.c b/softfloat/SoftFloat-3/source/i32_to_f64.c
deleted file mode 100755 (executable)
index d42cbe8..0000000
--- a/softfloat/SoftFloat-3/source/i32_to_f64.c
+++ /dev/null
@@ -1,31 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-float64_t i32_to_f64( int_fast32_t a )\r
-{\r
-    uint_fast64_t uiZ;\r
-    bool sign;\r
-    uint_fast32_t absA;\r
-    int shiftCount;\r
-    union ui64_f64 uZ;\r
-\r
-    if ( ! a ) {\r
-        uiZ = 0;\r
-    } else {\r
-        sign = ( a < 0 );\r
-        absA = sign ? - a : a;\r
-        shiftCount = softfloat_countLeadingZeros32( absA ) + 21;\r
-        uiZ =\r
-            packToF64UI(\r
-                sign, 0x432 - shiftCount, (uint_fast64_t) absA<<shiftCount );\r
-    }\r
-    uZ.ui = uiZ;\r
-    return uZ.f;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/i64_to_f32.c b/softfloat/SoftFloat-3/source/i64_to_f32.c
deleted file mode 100755 (executable)
index 4fecbb9..0000000
--- a/softfloat/SoftFloat-3/source/i64_to_f32.c
+++ /dev/null
@@ -1,36 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-float32_t i64_to_f32( int_fast64_t a )\r
-{\r
-    bool sign;\r
-    uint_fast64_t absA;\r
-    int shiftCount;\r
-    union ui32_f32 u;\r
-    uint_fast32_t sig;\r
-\r
-    sign = ( a < 0 );\r
-    absA = sign ? - (uint_fast64_t) a : a;\r
-    shiftCount = softfloat_countLeadingZeros64( absA ) - 40;\r
-    if ( 0 <= shiftCount ) {\r
-        u.ui =\r
-            a ? packToF32UI(\r
-                    sign, 0x95 - shiftCount, (uint_fast32_t) absA<<shiftCount )\r
-                : 0;\r
-        return u.f;\r
-    } else {\r
-        shiftCount += 7;\r
-        sig =\r
-            ( shiftCount < 0 )\r
-                ? softfloat_shortShift64RightJam( absA, - shiftCount )\r
-                : (uint_fast32_t) absA<<shiftCount;\r
-        return softfloat_roundPackToF32( sign, 0x9C - shiftCount, sig );\r
-    }\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/i64_to_f64.c b/softfloat/SoftFloat-3/source/i64_to_f64.c
deleted file mode 100755 (executable)
index 1add960..0000000
--- a/softfloat/SoftFloat-3/source/i64_to_f64.c
+++ /dev/null
@@ -1,21 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-float64_t i64_to_f64( int_fast64_t a )\r
-{\r
-    bool sign;\r
-    union ui64_f64 uZ;\r
-\r
-    sign = ( a < 0 );\r
-    if ( ! ( a & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) ) {\r
-        uZ.ui = sign ? packToF64UI( 1, 0x43E, 0 ) : 0;\r
-        return uZ.f;\r
-    }\r
-    return softfloat_normRoundPackToF64( sign, 0x43C, sign ? - a : a );\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/internals.h b/softfloat/SoftFloat-3/source/internals.h
deleted file mode 100755 (executable)
index cac0561..0000000
--- a/softfloat/SoftFloat-3/source/internals.h
+++ /dev/null
@@ -1,232 +0,0 @@
-\r
-/*** UPDATE COMMENTS. ***/\r
-\r
-#include "softfloat_types.h"\r
-\r
-union ui32_f32 { uint32_t ui; float32_t f; };\r
-union ui64_f64 { uint64_t ui; float64_t f; };\r
-#ifdef LITTLEENDIAN\r
-union ui128_f128 { uint64_t ui0, ui64; float128_t f; };\r
-#else\r
-union ui128_f128 { uint64_t ui64, ui0; float128_t f; };\r
-#endif\r
-\r
-enum {\r
-    softfloat_mulAdd_subC    = 1,\r
-    softfloat_mulAdd_subProd = 2\r
-};\r
-\r
-uint_fast32_t\r
- softfloat_roundPackToUI32( bool, uint_fast64_t, int_fast8_t, bool );\r
-uint_fast64_t\r
- softfloat_roundPackToUI64(\r
-     bool, uint_fast64_t, uint_fast64_t, int_fast8_t, bool );\r
-/*----------------------------------------------------------------------------\r
-| Takes a 64-bit fixed-point value `absZ' with binary point between bits 6\r
-| and 7, and returns the properly rounded 32-bit integer corresponding to the\r
-| input.  If `zSign' is 1, the input is negated before being converted to an\r
-| integer.  Bit 63 of `absZ' must be zero.  Ordinarily, the fixed-point input\r
-| is simply rounded to an integer, with the inexact exception raised if the\r
-| input cannot be represented exactly as an integer.  However, if the fixed-\r
-| point input is too large, the invalid exception is raised and the largest\r
-| positive or negative integer is returned.\r
-*----------------------------------------------------------------------------*/\r
-int_fast32_t\r
- softfloat_roundPackToI32( bool, uint_fast64_t, int_fast8_t, bool );\r
-/*----------------------------------------------------------------------------\r
-| Takes the 128-bit fixed-point value formed by concatenating `absZ0' and\r
-| `absZ1', with binary point between bits 63 and 64 (between the input words),\r
-| and returns the properly rounded 64-bit integer corresponding to the input.\r
-| If `zSign' is 1, the input is negated before being converted to an integer.\r
-| Ordinarily, the fixed-point input is simply rounded to an integer, with\r
-| the inexact exception raised if the input cannot be represented exactly as\r
-| an integer.  However, if the fixed-point input is too large, the invalid\r
-| exception is raised and the largest positive or negative integer is\r
-| returned.\r
-*----------------------------------------------------------------------------*/\r
-int_fast64_t\r
- softfloat_roundPackToI64(\r
-     bool, uint_fast64_t, uint_fast64_t, int_fast8_t, bool );\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the single-precision floating-point value `a' is a NaN;\r
-| otherwise, returns 0.\r
-*----------------------------------------------------------------------------*/\r
-#define isNaNF32UI( ui ) (0xFF000000<(uint32_t)((uint_fast32_t)(ui)<<1))\r
-/*----------------------------------------------------------------------------\r
-| Returns the sign bit of the single-precision floating-point value `a'.\r
-*----------------------------------------------------------------------------*/\r
-#define signF32UI( a ) ((bool)((uint32_t)(a)>>31))\r
-/*----------------------------------------------------------------------------\r
-| Returns the exponent bits of the single-precision floating-point value `a'.\r
-*----------------------------------------------------------------------------*/\r
-#define expF32UI( a ) ((int_fast16_t)((a)>>23)&0xFF)\r
-/*----------------------------------------------------------------------------\r
-| Returns the fraction bits of the single-precision floating-point value `a'.\r
-*----------------------------------------------------------------------------*/\r
-#define fracF32UI( a ) ((a)&0x007FFFFF)\r
-/*----------------------------------------------------------------------------\r
-| Packs the sign `zSign', exponent `zExp', and significand `zSig' into a\r
-| single-precision floating-point value, returning the result.  After being\r
-| shifted into the proper positions, the three fields are simply added\r
-| together to form the result.  This means that any integer portion of `zSig'\r
-| will be added into the exponent.  Since a properly normalized significand\r
-| will have an integer portion equal to 1, the `zExp' input should be 1 less\r
-| than the desired result exponent whenever `zSig' is a complete, normalized\r
-| significand.\r
-*----------------------------------------------------------------------------*/\r
-#define packToF32UI( sign, exp, sig ) (((uint32_t)(sign)<<31)+((uint32_t)(exp)<<23)+(sig))\r
-\r
-/*----------------------------------------------------------------------------\r
-| Normalizes the subnormal single-precision floating-point value represented\r
-| by the denormalized significand `aSig'.  The normalized exponent and\r
-| significand are stored at the locations pointed to by `zExpPtr' and\r
-| `zSigPtr', respectively.\r
-*----------------------------------------------------------------------------*/\r
-struct exp16_sig32 { int_fast16_t exp; uint_fast32_t sig; }\r
- softfloat_normSubnormalF32Sig( uint_fast32_t );\r
-\r
-/*----------------------------------------------------------------------------\r
-| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
-| and significand `zSig', and returns the proper single-precision floating-\r
-| point value corresponding to the abstract input.  Ordinarily, the abstract\r
-| value is simply rounded and packed into the single-precision format, with\r
-| the inexact exception raised if the abstract input cannot be represented\r
-| exactly.  However, if the abstract value is too large, the overflow and\r
-| inexact exceptions are raised and an infinity or maximal finite value is\r
-| returned.  If the abstract value is too small, the input value is rounded to\r
-| a subnormal number, and the underflow and inexact exceptions are raised if\r
-| the abstract input cannot be represented exactly as a subnormal single-\r
-| precision floating-point number.\r
-|     The input significand `zSig' has its binary point between bits 30\r
-| and 29, which is 7 bits to the left of the usual location.  This shifted\r
-| significand must be normalized or smaller.  If `zSig' is not normalized,\r
-| `zExp' must be 0; in that case, the result returned is a subnormal number,\r
-| and it must not require rounding.  In the usual case that `zSig' is\r
-| normalized, `zExp' must be 1 less than the ``true'' floating-point exponent.\r
-| The handling of underflow and overflow follows the IEC/IEEE Standard for\r
-| Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-float32_t softfloat_roundPackToF32( bool, int_fast16_t, uint_fast32_t );\r
-/*----------------------------------------------------------------------------\r
-| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
-| and significand `zSig', and returns the proper single-precision floating-\r
-| point value corresponding to the abstract input.  This routine is just like\r
-| `roundAndPackFloat32' except that `zSig' does not have to be normalized.\r
-| Bit 31 of `zSig' must be zero, and `zExp' must be 1 less than the ``true''\r
-| floating-point exponent.\r
-*----------------------------------------------------------------------------*/\r
-float32_t softfloat_normRoundPackToF32( bool, int_fast16_t, uint_fast32_t );\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of adding the absolute values of the single-precision\r
-| floating-point values `a' and `b'.  If `zSign' is 1, the sum is negated\r
-| before being returned.  `zSign' is ignored if the result is a NaN.\r
-| The addition is performed according to the IEC/IEEE Standard for Binary\r
-| Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-float32_t softfloat_addMagsF32( uint_fast32_t, uint_fast32_t, bool );\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of subtracting the absolute values of the single-\r
-| precision floating-point values `a' and `b'.  If `zSign' is 1, the\r
-| difference is negated before being returned.  `zSign' is ignored if the\r
-| result is a NaN.  The subtraction is performed according to the IEC/IEEE\r
-| Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-float32_t softfloat_subMagsF32( uint_fast32_t, uint_fast32_t, bool );\r
-/*----------------------------------------------------------------------------\r
-*----------------------------------------------------------------------------*/\r
-float32_t\r
- softfloat_mulAddF32( int, uint_fast32_t, uint_fast32_t, uint_fast32_t );\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the double-precision floating-point value `a' is a NaN;\r
-| otherwise, returns 0.\r
-*----------------------------------------------------------------------------*/\r
-#define isNaNF64UI( ui ) (UINT64_C(0xFFE0000000000000)<(uint64_t)((uint_fast64_t)(ui)<<1))\r
-/*----------------------------------------------------------------------------\r
-| Returns the sign bit of the double-precision floating-point value `a'.\r
-*----------------------------------------------------------------------------*/\r
-#define signF64UI( a ) ((bool)((uint64_t)(a)>>63))\r
-/*----------------------------------------------------------------------------\r
-| Returns the exponent bits of the double-precision floating-point value `a'.\r
-*----------------------------------------------------------------------------*/\r
-#define expF64UI( a ) ((int_fast16_t)((a)>>52)&0x7FF)\r
-/*----------------------------------------------------------------------------\r
-| Returns the fraction bits of the double-precision floating-point value `a'.\r
-*----------------------------------------------------------------------------*/\r
-#define fracF64UI( a ) ((a)&UINT64_C(0x000FFFFFFFFFFFFF))\r
-/*----------------------------------------------------------------------------\r
-| Packs the sign `zSign', exponent `zExp', and significand `zSig' into a\r
-| double-precision floating-point value, returning the result.  After being\r
-| shifted into the proper positions, the three fields are simply added\r
-| together to form the result.  This means that any integer portion of `zSig'\r
-| will be added into the exponent.  Since a properly normalized significand\r
-| will have an integer portion equal to 1, the `zExp' input should be 1 less\r
-| than the desired result exponent whenever `zSig' is a complete, normalized\r
-| significand.\r
-*----------------------------------------------------------------------------*/\r
-#define packToF64UI( sign, exp, sig ) (((uint64_t)(sign)<<63)+((uint64_t)(exp)<<52)+(sig))\r
-\r
-/*----------------------------------------------------------------------------\r
-| Normalizes the subnormal double-precision floating-point value represented\r
-| by the denormalized significand `aSig'.  The normalized exponent and\r
-| significand are stored at the locations pointed to by `zExpPtr' and\r
-| `zSigPtr', respectively.\r
-*----------------------------------------------------------------------------*/\r
-struct exp16_sig64 { int_fast16_t exp; uint_fast64_t sig; }\r
- softfloat_normSubnormalF64Sig( uint_fast64_t );\r
-\r
-/*----------------------------------------------------------------------------\r
-| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
-| and significand `zSig', and returns the proper double-precision floating-\r
-| point value corresponding to the abstract input.  Ordinarily, the abstract\r
-| value is simply rounded and packed into the double-precision format, with\r
-| the inexact exception raised if the abstract input cannot be represented\r
-| exactly.  However, if the abstract value is too large, the overflow and\r
-| inexact exceptions are raised and an infinity or maximal finite value is\r
-| returned.  If the abstract value is too small, the input value is rounded\r
-| to a subnormal number, and the underflow and inexact exceptions are raised\r
-| if the abstract input cannot be represented exactly as a subnormal double-\r
-| precision floating-point number.\r
-|     The input significand `zSig' has its binary point between bits 62\r
-| and 61, which is 10 bits to the left of the usual location.  This shifted\r
-| significand must be normalized or smaller.  If `zSig' is not normalized,\r
-| `zExp' must be 0; in that case, the result returned is a subnormal number,\r
-| and it must not require rounding.  In the usual case that `zSig' is\r
-| normalized, `zExp' must be 1 less than the ``true'' floating-point exponent.\r
-| The handling of underflow and overflow follows the IEC/IEEE Standard for\r
-| Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-float64_t softfloat_roundPackToF64( bool, int_fast16_t, uint_fast64_t );\r
-/*----------------------------------------------------------------------------\r
-| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
-| and significand `zSig', and returns the proper double-precision floating-\r
-| point value corresponding to the abstract input.  This routine is just like\r
-| `roundAndPackFloat64' except that `zSig' does not have to be normalized.\r
-| Bit 63 of `zSig' must be zero, and `zExp' must be 1 less than the ``true''\r
-| floating-point exponent.\r
-*----------------------------------------------------------------------------*/\r
-float64_t softfloat_normRoundPackToF64( bool, int_fast16_t, uint_fast64_t );\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of adding the absolute values of the double-precision\r
-| floating-point values `a' and `b'.  If `zSign' is 1, the sum is negated\r
-| before being returned.  `zSign' is ignored if the result is a NaN.\r
-| The addition is performed according to the IEC/IEEE Standard for Binary\r
-| Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-float64_t softfloat_addMagsF64( uint_fast64_t, uint_fast64_t, bool );\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of subtracting the absolute values of the double-\r
-| precision floating-point values `a' and `b'.  If `zSign' is 1, the\r
-| difference is negated before being returned.  `zSign' is ignored if the\r
-| result is a NaN.  The subtraction is performed according to the IEC/IEEE\r
-| Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-float64_t softfloat_subMagsF64( uint_fast64_t, uint_fast64_t, bool );\r
-/*----------------------------------------------------------------------------\r
-*----------------------------------------------------------------------------*/\r
-float64_t\r
- softfloat_mulAddF64( int, uint_fast64_t, uint_fast64_t, uint_fast64_t );\r
-\r

diff --git a/softfloat/SoftFloat-3/source/primitives.h b/softfloat/SoftFloat-3/source/primitives.h
deleted file mode 100755 (executable)
index 71038ea..0000000
--- a/softfloat/SoftFloat-3/source/primitives.h
+++ /dev/null
@@ -1,628 +0,0 @@
-
-/*============================================================================
-
-This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
-Arithmetic Package, Release 3.
-
-*** UPDATE
-
-Written by John R. Hauser.  This work was made possible in part by the
-International Computer Science Institute, located at Suite 600, 1947 Center
-Street, Berkeley, California 94704.  Funding was partially provided by the
-National Science Foundation under grant MIP-9311980.  The original version
-of this code was written as part of a project to build a fixed-point vector
-processor in collaboration with the University of California at Berkeley,
-overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
-is available through the Web page `http://www.cs.berkeley.edu/~jhauser/
-arithmetic/SoftFloat.html'.
-
-THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has
-been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
-RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
-AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
-COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
-EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
-INSTITUTE (possibly via similar legal notice) AGAINST ALL LOSSES, COSTS, OR
-OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
-
-Derivative works are acceptable, even for commercial purposes, so long as
-(1) the source code for the derivative work includes prominent notice that
-the work is derivative, and (2) the source code includes prominent notice with
-these four paragraphs for those parts of this code that are retained.
-
-=============================================================================*/
-
-#include <stdbool.h>
-#include <stdint.h>
-
-/*** CHANGE TO USE `fast' INTEGER TYPES? ***/
-/*** ADD 80-BIT FUNCTIONS? ***/
-
-#ifdef LITTLEENDIAN
-struct uintx80 { uint64_t v0; uint16_t v64; };
-struct uint128 { uint64_t v0, v64; };
-struct uint192 { uint64_t v0, v64, v128; };
-struct uint256 { uint64_t v0, v64, v128, v192; };
-#else
-struct uintx80 { uint16_t v64; uint64_t v0; };
-struct uint128 { uint64_t v64, v0; };
-struct uint192 { uint64_t v128, v64, v0; };
-struct uint256 { uint64_t v256, v128, v64, v0; };
-#endif
-
-struct uint64_extra { uint64_t v, extra; };
-struct uint128_extra { uint64_t v64; uint64_t v0; uint64_t extra; };
-
-
-/*** SHIFT COUNTS CANNOT BE ZERO.  MUST CHECK BEFORE CALLING! ***/
-
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the 128-bit value formed by concatenating `a0' and `a1'
-| is equal to the 128-bit value formed by concatenating `b0' and `b1'.
-| Otherwise, returns 0.
-*----------------------------------------------------------------------------*/
-#if defined INLINE_LEVEL && ( 1 <= INLINE_LEVEL )
-INLINE bool
- softfloat_eq128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
-    { return ( a64 == b64 ) && ( a0 == b0 ); }
-#else
-bool softfloat_eq128( uint64_t, uint64_t, uint64_t, uint64_t );
-#endif
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' is less
-| than or equal to the 128-bit value formed by concatenating `b0' and `b1'.
-| Otherwise, returns 0.
-*----------------------------------------------------------------------------*/
-#if defined INLINE_LEVEL && ( 1 <= INLINE_LEVEL )
-INLINE bool
- softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
-    { return ( a64 < b64 ) || ( ( a64 == b64 ) && ( a0 <= b0 ) ); }
-#else
-bool softfloat_le128( uint64_t, uint64_t, uint64_t, uint64_t );
-#endif
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' is less
-| than the 128-bit value formed by concatenating `b0' and `b1'.  Otherwise,
-| returns 0.
-*----------------------------------------------------------------------------*/
-#if defined INLINE_LEVEL && ( 1 <= INLINE_LEVEL )
-INLINE bool
- softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
-    { return ( a64 < b64 ) || ( ( a64 == b64 ) && ( a0 < b0 ) ); }
-#else
-bool softfloat_lt128( uint64_t, uint64_t, uint64_t, uint64_t );
-#endif
-
-/*----------------------------------------------------------------------------
-| Shifts the 128-bit value formed by concatenating `a0' and `a1' left by the
-| number of bits given in `count'.  Any bits shifted off are lost.  The value
-| of `count' must be less than 64.  The result is broken into two 64-bit
-| pieces which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
-*----------------------------------------------------------------------------*/
-#if defined INLINE_LEVEL && ( 2 <= INLINE_LEVEL )
-INLINE struct uint128
- softfloat_shortShift128Left( uint64_t a64, uint64_t a0, unsigned int count )
-{
-    struct uint128 z;
-    z.v64 = a64<<count | a0>>( ( - count ) & 63 );
-    z.v0 = a0<<count;
-    return z;
-}
-#else
-struct uint128 softfloat_shortShift128Left( uint64_t, uint64_t, unsigned int );
-#endif
-
-/*----------------------------------------------------------------------------
-| Shifts the 192-bit value formed by concatenating `a0', `a1', and `a2' left
-| by the number of bits given in `count'.  Any bits shifted off are lost.
-| The value of `count' must be less than 64.  The result is broken into three
-| 64-bit pieces which are stored at the locations pointed to by `z0Ptr',
-| `z1Ptr', and `z2Ptr'.
-*----------------------------------------------------------------------------*/
-#if defined INLINE_LEVEL && ( 3 <= INLINE_LEVEL )
-INLINE struct uint192
- softfloat_shortShift192Left(
-     uint64_t a128, uint64_t a64, uint64_t a0, unsigned int count )
-{
-    unsigned int negCount = - count;
-    struct uint192 z;
-    z.v128 = a128<<count | a64>>( negCount & 63 );
-    z.v64 = a64<<count | a0>>( negCount & 63 );
-    z.v0 = a0<<count;
-    return z;
-}
-#else
-struct uint192
- softfloat_shortShift192Left( uint64_t, uint64_t, uint64_t, unsigned int );
-#endif
-
-/*----------------------------------------------------------------------------
-| Shifts `a' right by the number of bits given in `count'.  If any nonzero
-| bits are shifted off, they are ``jammed'' into the least significant bit of
-| the result by setting the least significant bit to 1.  The value of `count'
-| can be arbitrarily large; in particular, if `count' is greater than 32, the
-| result will be either 0 or 1, depending on whether `a' is zero or nonzero.
-| The result is stored in the location pointed to by `zPtr'.
-*----------------------------------------------------------------------------*/
-#if defined INLINE_LEVEL && ( 2 <= INLINE_LEVEL )
-INLINE uint32_t softfloat_shift32RightJam( uint32_t a, unsigned int count )
-{
-    return
-        ( count < 32 )
-            ? a>>count | ( (uint32_t) ( a<<( ( - count ) & 31 ) ) != 0 )
-            : ( a != 0 );
-}
-#else
-uint32_t softfloat_shift32RightJam( uint32_t, unsigned int );
-#endif
-
-/*----------------------------------------------------------------------------
-| Shift count is less than 32.
-*----------------------------------------------------------------------------*/
-#if defined INLINE
-INLINE uint32_t softfloat_shortShift32Right1Jam( uint32_t a )
-    { return a>>1 | ( a & 1 ); }
-#else
-uint32_t softfloat_shortShift32Right1Jam( uint32_t );
-#endif
-
-/*----------------------------------------------------------------------------
-| Shifts `a' right by the number of bits given in `count'.  If any nonzero
-| bits are shifted off, they are ``jammed'' into the least significant bit of
-| the result by setting the least significant bit to 1.  The value of `count'
-| can be arbitrarily large; in particular, if `count' is greater than 64, the
-| result will be either 0 or 1, depending on whether `a' is zero or nonzero.
-| The result is stored in the location pointed to by `zPtr'.
-*----------------------------------------------------------------------------*/
-#if defined INLINE_LEVEL && ( 3 <= INLINE_LEVEL )
-INLINE uint64_t softfloat_shift64RightJam( uint64_t a, unsigned int count )
-{
-    return
-        ( count < 64 )
-            ? a>>count | ( (uint64_t) ( a<<( ( - count ) & 63 ) ) != 0 )
-            : ( a != 0 );
-}
-#else
-uint64_t softfloat_shift64RightJam( uint64_t, unsigned int );
-#endif
-
-/*----------------------------------------------------------------------------
-| Shift count is less than 64.
-*----------------------------------------------------------------------------*/
-#if defined INLINE_LEVEL && ( 2 <= INLINE_LEVEL )
-INLINE uint64_t
- softfloat_shortShift64RightJam( uint64_t a, unsigned int count )
-    { return a>>count | ( ( a & ( ( (uint64_t) 1<<count ) - 1 ) ) != 0 ); }
-#else
-uint64_t softfloat_shortShift64RightJam( uint64_t, unsigned int );
-#endif
-
-/*----------------------------------------------------------------------------
-| Shifts the 128-bit value formed by concatenating `a0' and `a1' right by 64
-| _plus_ the number of bits given in `count'.  The shifted result is at most
-| 64 nonzero bits; this is stored at the location pointed to by `z0Ptr'.  The
-| bits shifted off form a second 64-bit result as follows:  The _last_ bit
-| shifted off is the most-significant bit of the extra result, and the other
-| 63 bits of the extra result are all zero if and only if _all_but_the_last_
-| bits shifted off were all zero.  This extra result is stored in the location
-| pointed to by `z1Ptr'.  The value of `count' can be arbitrarily large.
-|     (This routine makes more sense if `a0' and `a1' are considered to form
-| a fixed-point value with binary point between `a0' and `a1'.  This fixed-
-| point value is shifted right by the number of bits given in `count', and
-| the integer part of the result is returned at the location pointed to by
-| `z0Ptr'.  The fractional part of the result may be slightly corrupted as
-| described above, and is returned at the location pointed to by `z1Ptr'.)
-*----------------------------------------------------------------------------*/
-#if defined INLINE_LEVEL && ( 3 <= INLINE_LEVEL )
-INLINE struct uint64_extra
- softfloat_shift64ExtraRightJam(
-     uint64_t a, uint64_t extra, unsigned int count )
-{
-    struct uint64_extra z;
-    if ( count < 64 ) {
-        z.v = a>>count;
-        z.extra = a<<( ( - count ) & 63 );
-    } else {
-        z.v = 0;
-        z.extra = ( count == 64 ) ? a : ( a != 0 );
-    }
-    z.extra |= ( extra != 0 );
-    return z;
-}
-#else
-struct uint64_extra
- softfloat_shift64ExtraRightJam( uint64_t, uint64_t, unsigned int );
-#endif
-
-/*----------------------------------------------------------------------------
-| Shift count is less than 64.
-*----------------------------------------------------------------------------*/
-#if defined INLINE_LEVEL && ( 2 <= INLINE_LEVEL )
-INLINE struct uint64_extra
- softfloat_shortShift64ExtraRightJam(
-     uint64_t a, uint64_t extra, unsigned int count )
-{
-    struct uint64_extra z;
-    z.v = a>>count;
-    z.extra = a<<( ( - count ) & 63 ) | ( extra != 0 );
-    return z;
-}
-#else
-struct uint64_extra
- softfloat_shortShift64ExtraRightJam( uint64_t, uint64_t, unsigned int );
-#endif
-
-/*----------------------------------------------------------------------------
-| Shifts the 128-bit value formed by concatenating `a0' and `a1' right by the
-| number of bits given in `count'.  Any bits shifted off are lost.  The value
-| of `count' can be arbitrarily large; in particular, if `count' is greater
-| than 128, the result will be 0.  The result is broken into two 64-bit pieces
-| which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
-*----------------------------------------------------------------------------*/
-/*----------------------------------------------------------------------------
-| Shift count is less than 64.
-*----------------------------------------------------------------------------*/
-#if defined INLINE_LEVEL && ( 2 <= INLINE_LEVEL )
-INLINE struct uint128
- softfloat_shortShift128Right( uint64_t a64, uint64_t a0, unsigned int count )
-{
-    struct uint128 z;
-    z.v64 = a64>>count;
-    z.v0 = a64<<( ( - count ) & 63 ) | a0>>count;
-    return z;
-}
-#else
-struct uint128
- softfloat_shortShift128Right( uint64_t, uint64_t, unsigned int );
-#endif
-
-/*----------------------------------------------------------------------------
-| Shifts the 128-bit value formed by concatenating `a0' and `a1' right by the
-| number of bits given in `count'.  If any nonzero bits are shifted off, they
-| are ``jammed'' into the least significant bit of the result by setting the
-| least significant bit to 1.  The value of `count' can be arbitrarily large;
-| in particular, if `count' is greater than 128, the result will be either
-| 0 or 1, depending on whether the concatenation of `a0' and `a1' is zero or
-| nonzero.  The result is broken into two 64-bit pieces which are stored at
-| the locations pointed to by `z0Ptr' and `z1Ptr'.
-*----------------------------------------------------------------------------*/
-#if defined INLINE_LEVEL && ( 4 <= INLINE_LEVEL )
-INLINE struct uint128
- softfloat_shift128RightJam( uint64_t a64, uint64_t a0, unsigned int count )
-{
-    unsigned int negCount;
-    struct uint128 z;
-    if ( count < 64 ) {
-        negCount = - count;
-        z.v64 = a64>>( count & 63 );
-        z.v0 =
-            a64<<( negCount & 63 ) | a0>>count
-                | ( (uint64_t) ( a0<<( negCount & 63 ) ) != 0 );
-    } else {
-        z.v64 = 0;
-        z.v0 =
-            ( count < 128 )
-                ? a64>>( count & 63 )
-                      | ( ( ( a64 & ( ( (uint64_t) 1<<( count & 63 ) ) - 1 ) )
-                                | a0 )
-                              != 0 )
-                : ( ( a64 | a0 ) != 0 );
-    }
-    return z;
-}
-#else
-struct uint128
- softfloat_shift128RightJam( uint64_t, uint64_t, unsigned int );
-#endif
-
-/*----------------------------------------------------------------------------
-| Shifts the 192-bit value formed by concatenating `a0', `a1', and `a2' right
-| by 64 _plus_ the number of bits given in `count'.  The shifted result is
-| at most 128 nonzero bits; these are broken into two 64-bit pieces which are
-| stored at the locations pointed to by `z0Ptr' and `z1Ptr'.  The bits shifted
-| off form a third 64-bit result as follows:  The _last_ bit shifted off is
-| the most-significant bit of the extra result, and the other 63 bits of the
-| extra result are all zero if and only if _all_but_the_last_ bits shifted off
-| were all zero.  This extra result is stored in the location pointed to by
-| `z2Ptr'.  The value of `count' can be arbitrarily large.
-|     (This routine makes more sense if `a0', `a1', and `a2' are considered
-| to form a fixed-point value with binary point between `a1' and `a2'.  This
-| fixed-point value is shifted right by the number of bits given in `count',
-| and the integer part of the result is returned at the locations pointed to
-| by `z0Ptr' and `z1Ptr'.  The fractional part of the result may be slightly
-| corrupted as described above, and is returned at the location pointed to by
-| `z2Ptr'.)
-*----------------------------------------------------------------------------*/
-#if defined INLINE_LEVEL && ( 5 <= INLINE_LEVEL )
-INLINE struct uint128_extra
- softfloat_shift128ExtraRightJam(
-     uint64_t a64, uint64_t a0, uint64_t extra, unsigned int count )
-{
-    unsigned int negCount = - count;
-    struct uint128_extra z;
-    if ( count < 64 ) {
-        z.v64 = a64>>count;
-        z.v0 = a64<<( negCount & 63 ) | a0>>count;
-        z.extra = a0<<( negCount & 63 );
-    } else {
-        z.v64 = 0;
-        if ( count == 64 ) {
-            z.v0 = a64;
-            z.extra = a0;
-        } else {
-            extra |= a0;
-            if ( count < 128 ) {
-                z.v0 = a64>>( count & 63 );
-                z.extra = a64<<( negCount & 63 );
-            } else {
-                z.v0 = 0;
-                z.extra = ( count == 128 ) ? a64 : ( a64 != 0 );
-            }
-        }
-    }
-    z.extra |= ( extra != 0 );
-    return z;
-}
-#else
-struct uint128_extra
- softfloat_shift128ExtraRightJam( uint64_t, uint64_t, uint64_t, unsigned int );
-#endif
-
-/*----------------------------------------------------------------------------
-| Shift count is less than 64.
-*----------------------------------------------------------------------------*/
-#if defined INLINE_LEVEL && ( 3 <= INLINE_LEVEL )
-INLINE struct uint128_extra
- softfloat_shortShift128ExtraRightJam(
-     uint64_t a64, uint64_t a0, uint64_t extra, unsigned int count )
-{
-    unsigned int negCount = - count;
-    struct uint128_extra z;
-    z.v64 = a64>>count;
-    z.v0 = a64<<( negCount & 63 ) | a0>>count;
-    z.extra = a0<<( negCount & 63 ) | ( extra != 0 );
-    return z;
-}
-#else
-struct uint128_extra
- softfloat_shortShift128ExtraRightJam(
-     uint64_t, uint64_t, uint64_t, unsigned int );
-#endif
-
-extern const uint8_t softfloat_countLeadingZeros8[ 256 ];
-
-/*----------------------------------------------------------------------------
-| Returns the number of leading 0 bits before the most-significant 1 bit of
-| `a'.  If `a' is zero, 32 is returned.
-*----------------------------------------------------------------------------*/
-#if defined INLINE_LEVEL && ( 2 <= INLINE_LEVEL )
-INLINE int softfloat_countLeadingZeros32( uint32_t a )
-{
-    int count = 0;
-    if ( a < 0x10000 ) {
-        count = 16;
-        a <<= 16;
-    }
-    if ( a < 0x1000000 ) {
-        count += 8;
-        a <<= 8;
-    }
-    count += softfloat_countLeadingZeros8[ a>>24 ];
-    return count;
-}
-#else
-int softfloat_countLeadingZeros32( uint32_t );
-#endif
-
-/*----------------------------------------------------------------------------
-| Returns the number of leading 0 bits before the most-significant 1 bit of
-| `a'.  If `a' is zero, 64 is returned.
-*----------------------------------------------------------------------------*/
-#if defined INLINE_LEVEL && ( 4 <= INLINE_LEVEL )
-INLINE int softfloat_countLeadingZeros64( uint64_t a )
-{
-    int count = 32;
-    uint32_t a32 = a;
-    if ( UINT64_C( 0x100000000 ) <= a ) {
-        count = 0;
-        a32 = a>>32;
-    }
-    /*------------------------------------------------------------------------
-    | From here, result is current count + count leading zeros of `a32'.
-    *------------------------------------------------------------------------*/
-    if ( a32 < 0x10000 ) {
-        count += 16;
-        a32 <<= 16;
-    }
-    if ( a32 < 0x1000000 ) {
-        count += 8;
-        a32 <<= 8;
-    }
-    count += softfloat_countLeadingZeros8[ a32>>24 ];
-    return count;
-}
-#else
-int softfloat_countLeadingZeros64( uint64_t );
-#endif
-
-/*----------------------------------------------------------------------------
-| Adds the 128-bit value formed by concatenating `a0' and `a1' to the 128-bit
-| value formed by concatenating `b0' and `b1'.  Addition is modulo 2^128, so
-| any carry out is lost.  The result is broken into two 64-bit pieces which
-| are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
-*----------------------------------------------------------------------------*/
-#if defined INLINE_LEVEL && ( 2 <= INLINE_LEVEL )
-INLINE struct uint128
- softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
-{
-    struct uint128 z;
-    z.v0 = a0 + b0;
-    z.v64 = a64 + b64;
-    z.v64 += ( z.v0 < a0 );
-    return z;
-}
-#else
-struct uint128 softfloat_add128( uint64_t, uint64_t, uint64_t, uint64_t );
-#endif
-
-/*----------------------------------------------------------------------------
-| Adds the 192-bit value formed by concatenating `a0', `a1', and `a2' to the
-| 192-bit value formed by concatenating `b0', `b1', and `b2'.  Addition is
-| modulo 2^192, so any carry out is lost.  The result is broken into three
-| 64-bit pieces which are stored at the locations pointed to by `z0Ptr',
-| `z1Ptr', and `z2Ptr'.
-*----------------------------------------------------------------------------*/
-#if defined INLINE_LEVEL && ( 3 <= INLINE_LEVEL )
-INLINE struct uint192
- softfloat_add192(
-     uint64_t a128,
-     uint64_t a64,
-     uint64_t a0,
-     uint64_t b128,
-     uint64_t b64,
-     uint64_t b0
- )
-{
-    struct uint192 z;
-    unsigned int carry64, carry128;
-    z.v0 = a0 + b0;
-    carry64 = ( z.v0 < a0 );
-    z.v64 = a64 + b64;
-    carry128 = ( z.v64 < a64 );
-    z.v128 = a128 + b128;
-    z.v64 += carry64;
-    carry128 += ( z.v64 < carry64 );
-    z.v128 += carry128;
-    return z;
-}
-#else
-struct uint192
- softfloat_add192(
-     uint64_t, uint64_t, uint64_t, uint64_t, uint64_t, uint64_t );
-#endif
-
-/*----------------------------------------------------------------------------
-| Subtracts the 128-bit value formed by concatenating `b0' and `b1' from the
-| 128-bit value formed by concatenating `a0' and `a1'.  Subtraction is modulo
-| 2^128, so any borrow out (carry out) is lost.  The result is broken into two
-| 64-bit pieces which are stored at the locations pointed to by `z0Ptr' and
-| `z1Ptr'.
-*----------------------------------------------------------------------------*/
-#if defined INLINE_LEVEL && ( 2 <= INLINE_LEVEL )
-INLINE struct uint128
- softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
-{
-    struct uint128 z;
-    z.v0 = a0 - b0;
-    z.v64 = a64 - b64;
-    z.v64 -= ( a0 < b0 );
-    return z;
-}
-#else
-struct uint128 softfloat_sub128( uint64_t, uint64_t, uint64_t, uint64_t );
-#endif
-
-/*----------------------------------------------------------------------------
-| Subtracts the 192-bit value formed by concatenating `b0', `b1', and `b2'
-| from the 192-bit value formed by concatenating `a0', `a1', and `a2'.
-| Subtraction is modulo 2^192, so any borrow out (carry out) is lost.  The
-| result is broken into three 64-bit pieces which are stored at the locations
-| pointed to by `z0Ptr', `z1Ptr', and `z2Ptr'.
-*----------------------------------------------------------------------------*/
-#if defined INLINE_LEVEL && ( 3 <= INLINE_LEVEL )
-INLINE struct uint192
- softfloat_sub192(
-     uint64_t a128,
-     uint64_t a64,
-     uint64_t a0,
-     uint64_t b128,
-     uint64_t b64,
-     uint64_t b0
- )
-{
-    struct uint192 z;
-    unsigned int borrow64, borrow128;
-    z.v0 = a0 - b0;
-    borrow64 = ( a0 < b0 );
-    z.v64 = a64 - b64;
-    borrow128 = ( a64 < b64 );
-    z.v128 = a128 - b128;
-    borrow128 += ( z.v64 < borrow64 );
-    z.v64 -= borrow64;
-    z.v128 -= borrow128;
-    return z;
-}
-#else
-struct uint192
- softfloat_sub192(
-     uint64_t, uint64_t, uint64_t, uint64_t, uint64_t, uint64_t );
-#endif
-
-/*----------------------------------------------------------------------------
-| Multiplies `a' by `b' to obtain a 128-bit product.  The product is broken
-| into two 64-bit pieces which are stored at the locations pointed to by
-| `z0Ptr' and `z1Ptr'.
-*----------------------------------------------------------------------------*/
-#if defined INLINE_LEVEL && ( 4 <= INLINE_LEVEL )
-INLINE struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b )
-{
-    uint32_t a32 = a>>32;
-    uint32_t a0 = a;
-    uint32_t b32 = b>>32;
-    uint32_t b0 = b;
-    struct uint128 z;
-    uint64_t mid1, mid2, mid;
-    z.v0 = (uint64_t) a0 * b0;
-    mid1 = (uint64_t) a32 * b0;
-    mid2 = (uint64_t) a0 * b32;
-    z.v64 = (uint64_t) a32 * b32;
-    mid = mid1 + mid2;
-    z.v64 += ( (uint64_t) ( mid < mid1 ) )<<32 | mid>>32;
-    mid <<= 32;
-    z.v0 += mid;
-    z.v64 += ( z.v0 < mid );
-    return z;
-}
-#else
-struct uint128 softfloat_mul64To128( uint64_t, uint64_t );
-#endif
-
-/*----------------------------------------------------------------------------
-| Multiplies the 128-bit value formed by concatenating `a0' and `a1' by
-| `b' to obtain a 192-bit product.  The product is broken into three 64-bit
-| pieces which are stored at the locations pointed to by `z0Ptr', `z1Ptr', and
-| `z2Ptr'.
-*----------------------------------------------------------------------------*/
-struct uint192 softfloat_mul128By64To192( uint64_t, uint64_t, uint64_t );
-/*----------------------------------------------------------------------------
-| Multiplies the 128-bit value formed by concatenating `a0' and `a1' to the
-| 128-bit value formed by concatenating `b0' and `b1' to obtain a 256-bit
-| product.  The product is broken into four 64-bit pieces which are stored at
-| the locations pointed to by `z0Ptr', `z1Ptr', `z2Ptr', and `z3Ptr'.
-*----------------------------------------------------------------------------*/
-struct uint256 softfloat_mul128To256( uint64_t, uint64_t, uint64_t, uint64_t );
-
-/*----------------------------------------------------------------------------
-| Returns an approximation to the 64-bit integer quotient obtained by dividing
-| `b' into the 128-bit value formed by concatenating `a0' and `a1'.  The
-| divisor `b' must be at least 2^63.  If q is the exact quotient truncated
-| toward zero, the approximation returned lies between q and q + 2 inclusive.
-| If the exact quotient q is larger than 64 bits, the maximum positive 64-bit
-| unsigned integer is returned.
-*----------------------------------------------------------------------------*/
-uint64_t softfloat_estimateDiv128To64( uint64_t, uint64_t, uint64_t );
-
-/*----------------------------------------------------------------------------
-| Returns an approximation to the square root of the 32-bit significand given
-| by `a'.  Considered as an integer, `a' must be at least 2^31.  If bit 0 of
-| `aExp' (the least significant bit) is 1, the integer returned approximates
-| 2^31*sqrt(`a'/2^31), where `a' is considered an integer.  If bit 0 of `aExp'
-| is 0, the integer returned approximates 2^31*sqrt(`a'/2^30).  In either
-| case, the approximation returned lies strictly within +/-2 of the exact
-| value.
-*----------------------------------------------------------------------------*/
-uint32_t softfloat_estimateSqrt32( unsigned int, uint32_t );
-

diff --git a/softfloat/SoftFloat-3/source/riscv/platform.h b/softfloat/SoftFloat-3/source/riscv/platform.h
deleted file mode 100755 (executable)
index 9355edf..0000000
--- a/softfloat/SoftFloat-3/source/riscv/platform.h
+++ /dev/null
@@ -1,38 +0,0 @@
-
-/*============================================================================
-
-*** FIX.
-
-This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
-Arithmetic Package, Release 2b.
-
-Written by John R. Hauser.  This work was made possible in part by the
-International Computer Science Institute, located at Suite 600, 1947 Center
-Street, Berkeley, California 94704.  Funding was partially provided by the
-National Science Foundation under grant MIP-9311980.  The original version
-of this code was written as part of a project to build a fixed-point vector
-processor in collaboration with the University of California at Berkeley,
-overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
-is available through the Web page `http://www.cs.berkeley.edu/~jhauser/
-arithmetic/SoftFloat.html'.
-
-THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has
-been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
-RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
-AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
-COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
-EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
-INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR
-OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
-
-Derivative works are acceptable, even for commercial purposes, so long as
-(1) the source code for the derivative work includes prominent notice that
-the work is derivative, and (2) the source code includes prominent notice with
-these four paragraphs for those parts of this code that are retained.
-
-=============================================================================*/
-
-/*----------------------------------------------------------------------------
-*----------------------------------------------------------------------------*/
-#define LITTLEENDIAN
-

diff --git a/softfloat/SoftFloat-3/source/riscv/s_commonNaNToF32UI.c b/softfloat/SoftFloat-3/source/riscv/s_commonNaNToF32UI.c
deleted file mode 100755 (executable)
index 61f2735..0000000
--- a/softfloat/SoftFloat-3/source/riscv/s_commonNaNToF32UI.c
+++ /dev/null
@@ -1,17 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "specialize.h"\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the canonical NaN `a' to the single-\r
-| precision floating-point format.\r
-*----------------------------------------------------------------------------*/\r
-\r
-uint_fast32_t softfloat_commonNaNToF32UI( struct commonNaN a )\r
-{\r
-\r
-    return (uint_fast32_t) a.sign<<31 | 0x7FFFFFFF;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/riscv/s_commonNaNToF64UI.c b/softfloat/SoftFloat-3/source/riscv/s_commonNaNToF64UI.c
deleted file mode 100755 (executable)
index da36c04..0000000
--- a/softfloat/SoftFloat-3/source/riscv/s_commonNaNToF64UI.c
+++ /dev/null
@@ -1,18 +0,0 @@
-
-#include <stdint.h>
-#include "platform.h"
-#include "specialize.h"
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the canonical NaN `a' to the double-
-| precision floating-point format.
-*----------------------------------------------------------------------------*/
-
-uint_fast64_t softfloat_commonNaNToF64UI( struct commonNaN a )
-{
-
-    return
-        (uint_fast64_t) a.sign<<63 | UINT64_C( 0x7FFFFFFFFFFFFFFF );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/riscv/s_f32UIToCommonNaN.c b/softfloat/SoftFloat-3/source/riscv/s_f32UIToCommonNaN.c
deleted file mode 100755 (executable)
index 9ee0db9..0000000
--- a/softfloat/SoftFloat-3/source/riscv/s_f32UIToCommonNaN.c
+++ /dev/null
@@ -1,25 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "specialize.h"\r
-#include "softfloat.h"\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the single-precision floating-point NaN\r
-| `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid\r
-| exception is raised.\r
-*----------------------------------------------------------------------------*/\r
-struct commonNaN softfloat_f32UIToCommonNaN( uint_fast32_t uiA )\r
-{\r
-    struct commonNaN z;\r
-\r
-    if ( softfloat_isSigNaNF32UI( uiA ) ) {\r
-        softfloat_raiseFlags( softfloat_flag_invalid );\r
-    }\r
-    z.sign = uiA>>31;\r
-    z.v64 = (uint_fast64_t) 0x7FFFF <<41;\r
-    z.v0 = 0;\r
-    return z;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/riscv/s_f64UIToCommonNaN.c b/softfloat/SoftFloat-3/source/riscv/s_f64UIToCommonNaN.c
deleted file mode 100755 (executable)
index 84d8ca0..0000000
--- a/softfloat/SoftFloat-3/source/riscv/s_f64UIToCommonNaN.c
+++ /dev/null
@@ -1,25 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "specialize.h"\r
-#include "softfloat.h"\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the double-precision floating-point NaN\r
-| `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid\r
-| exception is raised.\r
-*----------------------------------------------------------------------------*/\r
-struct commonNaN softfloat_f64UIToCommonNaN( uint_fast64_t uiA )\r
-{\r
-    struct commonNaN z;\r
-\r
-    if ( softfloat_isSigNaNF64UI( uiA ) ) {\r
-        softfloat_raiseFlags( softfloat_flag_invalid );\r
-    }\r
-    z.sign = uiA>>63;\r
-    z.v64 = (uint_fast64_t) 0xFFFFFFFFFFFFF <<12;\r
-    z.v0 = 0;\r
-    return z;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/riscv/s_isSigNaNF32UI.c b/softfloat/SoftFloat-3/source/riscv/s_isSigNaNF32UI.c
deleted file mode 100755 (executable)
index 0a9c33f..0000000
--- a/softfloat/SoftFloat-3/source/riscv/s_isSigNaNF32UI.c
+++ /dev/null
@@ -1,13 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "specialize.h"
-
-bool softfloat_isSigNaNF32UI( uint_fast32_t ui )
-{
-
-    return ( ( ui>>22 & 0x1FF ) == 0x1FE ) && ( ui & 0x003FFFFF );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/riscv/s_isSigNaNF64UI.c b/softfloat/SoftFloat-3/source/riscv/s_isSigNaNF64UI.c
deleted file mode 100755 (executable)
index d255213..0000000
--- a/softfloat/SoftFloat-3/source/riscv/s_isSigNaNF64UI.c
+++ /dev/null
@@ -1,15 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "specialize.h"
-
-bool softfloat_isSigNaNF64UI( uint_fast64_t ui )
-{
-
-    return
-        ( ( ui>>51 & 0xFFF ) == 0xFFE )
-            && ( ui & UINT64_C( 0x0007FFFFFFFFFFFF ) );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/riscv/s_propagateNaNF32UI.c b/softfloat/SoftFloat-3/source/riscv/s_propagateNaNF32UI.c
deleted file mode 100755 (executable)
index 07774e8..0000000
--- a/softfloat/SoftFloat-3/source/riscv/s_propagateNaNF32UI.c
+++ /dev/null
@@ -1,55 +0,0 @@
-\r
-/*** UPDATE COMMENTS. ***/\r
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "internals.h"\r
-#include "specialize.h"\r
-#include "softfloat.h"\r
-\r
-/*----------------------------------------------------------------------------\r
-| Takes two single-precision floating-point values `a' and `b', one of which\r
-| is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a\r
-| signaling NaN, the invalid exception is raised.\r
-*----------------------------------------------------------------------------*/\r
-\r
-uint_fast32_t\r
- softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB )\r
-{\r
-    bool isNaNA, isSigNaNA, isNaNB, isSigNaNB;\r
-    uint_fast32_t uiMagA, uiMagB;\r
-\r
-    /*------------------------------------------------------------------------\r
-    *------------------------------------------------------------------------*/\r
-    isNaNA = isNaNF32UI( uiA );\r
-    isSigNaNA = softfloat_isSigNaNF32UI( uiA );\r
-    isNaNB = isNaNF32UI( uiB );\r
-    isSigNaNB = softfloat_isSigNaNF32UI( uiB );\r
-    /*------------------------------------------------------------------------\r
-    | Make NaNs non-signaling.\r
-    *------------------------------------------------------------------------*/\r
-    uiA |= 0x00400000;\r
-    uiB |= 0x00400000;\r
-    /*------------------------------------------------------------------------\r
-    *------------------------------------------------------------------------*/\r
-    if ( isSigNaNA | isSigNaNB ) {\r
-        softfloat_raiseFlags( softfloat_flag_invalid );\r
-    }\r
-    if ( isSigNaNA ) {\r
-        if ( isSigNaNB ) goto returnLargerSignificand;\r
-        return isNaNB ? uiB : uiA;\r
-    } else if ( isNaNA ) {\r
-        if ( isSigNaNB || ! isNaNB ) return uiA;\r
- returnLargerSignificand:\r
-        uiMagA = uiA<<1;\r
-        uiMagB = uiB<<1;\r
-        if ( uiMagA < uiMagB ) return uiB;\r
-        if ( uiMagB < uiMagA ) return uiA;\r
-        return ( uiA < uiB ) ? uiA : uiB;\r
-    } else {\r
-        return uiB;\r
-    }\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/riscv/s_propagateNaNF64UI.c b/softfloat/SoftFloat-3/source/riscv/s_propagateNaNF64UI.c
deleted file mode 100755 (executable)
index 0ff6446..0000000
--- a/softfloat/SoftFloat-3/source/riscv/s_propagateNaNF64UI.c
+++ /dev/null
@@ -1,55 +0,0 @@
-
-/*** UPDATE COMMENTS. ***/
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "specialize.h"
-#include "softfloat.h"
-
-/*----------------------------------------------------------------------------
-| Takes two double-precision floating-point values `a' and `b', one of which
-| is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a
-| signaling NaN, the invalid exception is raised.
-*----------------------------------------------------------------------------*/
-
-uint_fast64_t
- softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB )
-{
-    bool isNaNA, isSigNaNA, isNaNB, isSigNaNB;
-    uint_fast64_t uiMagA, uiMagB;
-
-    /*------------------------------------------------------------------------
-    *------------------------------------------------------------------------*/
-    isNaNA = isNaNF64UI( uiA );
-    isSigNaNA = softfloat_isSigNaNF64UI( uiA );
-    isNaNB = isNaNF64UI( uiB );
-    isSigNaNB = softfloat_isSigNaNF64UI( uiB );
-    /*------------------------------------------------------------------------
-    | Make NaNs non-signaling.
-    *------------------------------------------------------------------------*/
-    uiA |= UINT64_C( 0x0008000000000000 );
-    uiB |= UINT64_C( 0x0008000000000000 );
-    /*------------------------------------------------------------------------
-    *------------------------------------------------------------------------*/
-    if ( isSigNaNA | isSigNaNB ) {
-        softfloat_raiseFlags( softfloat_flag_invalid );
-    }
-    if ( isSigNaNA ) {
-        if ( isSigNaNB ) goto returnLargerSignificand;
-        return isNaNB ? uiB : uiA;
-    } else if ( isNaNA ) {
-        if ( isSigNaNB || ! isNaNB ) return uiA;
- returnLargerSignificand:
-        uiMagA = uiA & UINT64_C( 0x7FFFFFFFFFFFFFFF );
-        uiMagB = uiB & UINT64_C( 0x7FFFFFFFFFFFFFFF );
-        if ( uiMagA < uiMagB ) return uiB;
-        if ( uiMagB < uiMagA ) return uiA;
-        return ( uiA < uiB ) ? uiA : uiB;
-    } else {
-        return uiB;
-    }
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/riscv/softfloat_raiseFlags.c b/softfloat/SoftFloat-3/source/riscv/softfloat_raiseFlags.c
deleted file mode 100755 (executable)
index c0c0dc8..0000000
--- a/softfloat/SoftFloat-3/source/riscv/softfloat_raiseFlags.c
+++ /dev/null
@@ -1,51 +0,0 @@
-
-/*============================================================================
-
-*** FIX.
-
-This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
-Arithmetic Package, Release 2b.
-
-Written by John R. Hauser.  This work was made possible in part by the
-International Computer Science Institute, located at Suite 600, 1947 Center
-Street, Berkeley, California 94704.  Funding was partially provided by the
-National Science Foundation under grant MIP-9311980.  The original version
-of this code was written as part of a project to build a fixed-point vector
-processor in collaboration with the University of California at Berkeley,
-overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
-is available through the Web page `http://www.cs.berkeley.edu/~jhauser/
-arithmetic/SoftFloat.html'.
-
-THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has
-been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
-RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
-AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
-COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
-EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
-INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR
-OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
-
-Derivative works are acceptable, even for commercial purposes, so long as
-(1) the source code for the derivative work includes prominent notice that
-the work is derivative, and (2) the source code includes prominent notice with
-these four paragraphs for those parts of this code that are retained.
-
-=============================================================================*/
-
-#include "platform.h"
-#include "softfloat.h"
-
-/*----------------------------------------------------------------------------
-| Raises the exceptions specified by `flags'.  Floating-point traps can be
-| defined here if desired.  It is currently not possible for such a trap
-| to substitute a result value.  If traps are not implemented, this routine
-| should be simply `float_exception_flags |= flags;'.
-*----------------------------------------------------------------------------*/
-
-void softfloat_raiseFlags( int_fast8_t flags )
-{
-
-    softfloat_exceptionFlags |= flags;
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/riscv/softfloat_types.h b/softfloat/SoftFloat-3/source/riscv/softfloat_types.h
deleted file mode 100755 (executable)
index b5c1828..0000000
--- a/softfloat/SoftFloat-3/source/riscv/softfloat_types.h
+++ /dev/null
@@ -1,16 +0,0 @@
-
-#ifndef softfloat_types_h
-#define softfloat_types_h
-
-/*** COMMENTS. ***/
-
-#include <stdbool.h>
-#include <stdint.h>
-
-typedef struct { uint32_t v; } float32_t;
-typedef struct { uint64_t v; } float64_t;
-typedef struct { uint64_t v; uint16_t x; } floatx80_t;
-typedef struct { uint64_t v[ 2 ]; } float128_t;
-
-#endif
-

diff --git a/softfloat/SoftFloat-3/source/riscv/specialize.h b/softfloat/SoftFloat-3/source/riscv/specialize.h
deleted file mode 100755 (executable)
index bf57bc9..0000000
--- a/softfloat/SoftFloat-3/source/riscv/specialize.h
+++ /dev/null
@@ -1,113 +0,0 @@
-\r
-/*============================================================================\r
-\r
-*** FIX.\r
-\r
-This C source fragment is part of the SoftFloat IEC/IEEE Floating-point\r
-Arithmetic Package, Release 2b.\r
-\r
-Written by John R. Hauser.  This work was made possible in part by the\r
-International Computer Science Institute, located at Suite 600, 1947 Center\r
-Street, Berkeley, California 94704.  Funding was partially provided by the\r
-National Science Foundation under grant MIP-9311980.  The original version\r
-of this code was written as part of a project to build a fixed-point vector\r
-processor in collaboration with the University of California at Berkeley,\r
-overseen by Profs. Nelson Morgan and John Wawrzynek.  More information\r
-is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
-arithmetic/SoftFloat.html'.\r
-\r
-THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has\r
-been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
-RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
-AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
-COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
-EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
-INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
-OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
-\r
-Derivative works are acceptable, even for commercial purposes, so long as\r
-(1) the source code for the derivative work includes prominent notice that\r
-the work is derivative, and (2) the source code includes prominent notice with\r
-these four paragraphs for those parts of this code that are retained.\r
-\r
-=============================================================================*/\r
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-\r
-/*----------------------------------------------------------------------------\r
-*----------------------------------------------------------------------------*/\r
-#define init_detectTininess softfloat_tininess_beforeRounding;\r
-\r
-/*----------------------------------------------------------------------------\r
-| Structure used to transfer NaN representations from one format to another.\r
-*----------------------------------------------------------------------------*/\r
-struct commonNaN {\r
-    bool sign;\r
-    uint64_t v64, v0;\r
-};\r
-\r
-/*----------------------------------------------------------------------------\r
-| The pattern for a default generated single-precision NaN.\r
-*----------------------------------------------------------------------------*/\r
-#define defaultNaNF32UI 0xFFFFFFFF\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the single-precision floating-point value `a' is a signaling\r
-| NaN; otherwise, returns 0.\r
-*----------------------------------------------------------------------------*/\r
-#if defined INLINE_LEVEL && ( 1 <= INLINE_LEVEL )\r
-INLINE bool softfloat_isSigNaNF32UI( uint_fast32_t ui )\r
-    { return ( ( ui>>22 & 0x1FF ) == 0x1FE ) && ( ui & 0x003FFFFF ); }\r
-#else\r
-bool softfloat_isSigNaNF32UI( uint_fast32_t );\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------\r
-*----------------------------------------------------------------------------*/\r
-struct commonNaN softfloat_f32UIToCommonNaN( uint_fast32_t );\r
-#if defined INLINE_LEVEL && ( 1 <= INLINE_LEVEL )\r
-INLINE uint_fast32_t softfloat_commonNaNToF32UI( struct commonNaN a )\r
-    { return (uint_fast32_t) a.sign<<31 | 0x7FFFFFFF; }\r
-#else\r
-uint_fast32_t softfloat_commonNaNToF32UI( struct commonNaN );\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------\r
-| Takes two single-precision floating-point values `a' and `b', one of which\r
-| is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a\r
-| signaling NaN, the invalid exception is raised.\r
-*----------------------------------------------------------------------------*/\r
-uint_fast32_t softfloat_propagateNaNF32UI( uint_fast32_t, uint_fast32_t );\r
-\r
-/*----------------------------------------------------------------------------\r
-| The pattern for a default generated double-precision NaN.\r
-*----------------------------------------------------------------------------*/\r
-#define defaultNaNF64UI UINT64_C(0xFFF8000000000000)\r
-\r
-/*----------------------------------------------------------------------------\r
-*----------------------------------------------------------------------------*/\r
-#if defined INLINE_LEVEL && ( 1 <= INLINE_LEVEL )\r
-INLINE bool softfloat_isSigNaNF64UI( uint_fast64_t ui )\r
-{\r
-    return\r
-        ( ( ui>>51 & 0xFFF ) == 0xFFE )\r
-            && ( ui & UINT64_C( 0x0007FFFFFFFFFFFF ) );\r
-}\r
-#else\r
-bool softfloat_isSigNaNF64UI( uint_fast64_t );\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------\r
-*----------------------------------------------------------------------------*/\r
-/*** MIGHT BE INLINE'D. ***/\r
-struct commonNaN softfloat_f64UIToCommonNaN( uint_fast64_t );\r
-uint_fast64_t softfloat_commonNaNToF64UI( struct commonNaN );\r
-\r
-/*----------------------------------------------------------------------------\r
-| Takes two double-precision floating-point values `a' and `b', one of which\r
-| is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a\r
-| signaling NaN, the invalid exception is raised.\r
-*----------------------------------------------------------------------------*/\r
-uint_fast64_t softfloat_propagateNaNF64UI( uint_fast64_t, uint_fast64_t );\r
-\r

diff --git a/softfloat/SoftFloat-3/source/s_add128.c b/softfloat/SoftFloat-3/source/s_add128.c
deleted file mode 100755 (executable)
index 59c0348..0000000
--- a/softfloat/SoftFloat-3/source/s_add128.c
+++ /dev/null
@@ -1,17 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-\r
-struct uint128\r
- softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )\r
-{\r
-    struct uint128 z;\r
-\r
-    z.v0 = a0 + b0;\r
-    z.v64 = a64 + b64;\r
-    z.v64 += ( z.v0 < a0 );\r
-    return z;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/s_add192.c b/softfloat/SoftFloat-3/source/s_add192.c
deleted file mode 100755 (executable)
index 543eb5d..0000000
--- a/softfloat/SoftFloat-3/source/s_add192.c
+++ /dev/null
@@ -1,30 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-\r
-struct uint192\r
- softfloat_add192(\r
-     uint64_t a128,\r
-     uint64_t a64,\r
-     uint64_t a0,\r
-     uint64_t b128,\r
-     uint64_t b64,\r
-     uint64_t b0\r
- )\r
-{\r
-    struct uint192 z;\r
-    unsigned int carry64, carry128;\r
-\r
-    z.v0 = a0 + b0;\r
-    carry64 = ( z.v0 < a0 );\r
-    z.v64 = a64 + b64;\r
-    carry128 = ( z.v64 < a64 );\r
-    z.v128 = a128 + b128;\r
-    z.v64 += carry64;\r
-    carry128 += ( z.v64 < carry64 );\r
-    z.v128 += carry128;\r
-    return z;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/s_addMagsF32.c b/softfloat/SoftFloat-3/source/s_addMagsF32.c
deleted file mode 100755 (executable)
index f361e2b..0000000
--- a/softfloat/SoftFloat-3/source/s_addMagsF32.c
+++ /dev/null
@@ -1,75 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-#include "specialize.h"\r
-\r
-float32_t\r
- softfloat_addMagsF32( uint_fast32_t uiA, uint_fast32_t uiB, bool signZ )\r
-{\r
-    int_fast16_t expA;\r
-    uint_fast32_t sigA;\r
-    int_fast16_t expB;\r
-    uint_fast32_t sigB;\r
-    int_fast16_t expDiff;\r
-    uint_fast32_t uiZ;\r
-    int_fast16_t expZ;\r
-    uint_fast32_t sigZ;\r
-    union ui32_f32 uZ;\r
-\r
-    expA = expF32UI( uiA );\r
-    sigA = fracF32UI( uiA );\r
-    expB = expF32UI( uiB );\r
-    sigB = fracF32UI( uiB );\r
-    expDiff = expA - expB;\r
-    sigA <<= 6;\r
-    sigB <<= 6;\r
-    if ( ! expDiff ) {\r
-        if ( expA == 0xFF ) {\r
-            if ( sigA | sigB ) goto propagateNaN;\r
-            uiZ = uiA;\r
-            goto uiZ;\r
-        }\r
-        if ( ! expA ) {\r
-            uiZ = packToF32UI( signZ, 0, ( uiA + uiB ) & 0x7FFFFFFF );\r
-            goto uiZ;\r
-        }\r
-        expZ = expA;\r
-        sigZ = 0x40000000 + sigA + sigB;\r
-    } else {\r
-        if ( expDiff < 0 ) {\r
-            if ( expB == 0xFF ) {\r
-                if ( sigB ) goto propagateNaN;\r
-                uiZ = packToF32UI( signZ, 0xFF, 0 );\r
-                goto uiZ;\r
-            }\r
-            expZ = expB;\r
-            sigA += expA ? 0x20000000 : sigA;\r
-            sigA = softfloat_shift32RightJam( sigA, - expDiff );\r
-        } else {\r
-            if ( expA == 0xFF ) {\r
-                if ( sigA ) goto propagateNaN;\r
-                uiZ = uiA;\r
-                goto uiZ;\r
-            }\r
-            expZ = expA;\r
-            sigB += expB ? 0x20000000 : sigB;\r
-            sigB = softfloat_shift32RightJam( sigB, expDiff );\r
-        }\r
-        sigZ = 0x20000000 + sigA + sigB;\r
-        if ( sigZ < 0x40000000 ) {\r
-            --expZ;\r
-            sigZ <<= 1;\r
-        }\r
-    }\r
-    return softfloat_roundPackToF32( signZ, expZ, sigZ );\r
- propagateNaN:\r
-    uiZ = softfloat_propagateNaNF32UI( uiA, uiB );\r
- uiZ:\r
-    uZ.ui = uiZ;\r
-    return uZ.f;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/s_addMagsF64.c b/softfloat/SoftFloat-3/source/s_addMagsF64.c
deleted file mode 100755 (executable)
index a81c3e4..0000000
--- a/softfloat/SoftFloat-3/source/s_addMagsF64.c
+++ /dev/null
@@ -1,77 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "primitives.h"
-#include "internals.h"
-#include "specialize.h"
-
-float64_t
- softfloat_addMagsF64( uint_fast64_t uiA, uint_fast64_t uiB, bool signZ )
-{
-    int_fast16_t expA;
-    uint_fast64_t sigA;
-    int_fast16_t expB;
-    uint_fast64_t sigB;
-    int_fast16_t expDiff;
-    uint_fast64_t uiZ;
-    int_fast16_t expZ;
-    uint_fast64_t sigZ;
-    union ui64_f64 uZ;
-
-    expA = expF64UI( uiA );
-    sigA = fracF64UI( uiA );
-    expB = expF64UI( uiB );
-    sigB = fracF64UI( uiB );
-    expDiff = expA - expB;
-    sigA <<= 9;
-    sigB <<= 9;
-    if ( ! expDiff ) {
-        if ( expA == 0x7FF ) {
-            if ( sigA | sigB ) goto propagateNaN;
-            uiZ = uiA;
-            goto uiZ;
-        }
-        if ( ! expA ) {
-            uiZ =
-                packToF64UI(
-                    signZ, 0, ( uiA + uiB ) & UINT64_C( 0x7FFFFFFFFFFFFFFF ) );
-            goto uiZ;
-        }
-        expZ = expA;
-        sigZ = UINT64_C( 0x4000000000000000 ) + sigA + sigB;
-    } else {
-        if ( expDiff < 0 ) {
-            if ( expB == 0x7FF ) {
-                if ( sigB ) goto propagateNaN;
-                uiZ = packToF64UI( signZ, 0x7FF, 0 );
-                goto uiZ;
-            }
-            expZ = expB;
-            sigA += expA ? UINT64_C( 0x2000000000000000 ) : sigA;
-            sigA = softfloat_shift64RightJam( sigA, - expDiff );
-        } else {
-            if ( expA == 0x7FF ) {
-                if ( sigA ) goto propagateNaN;
-                uiZ = uiA;
-                goto uiZ;
-            }
-            expZ = expA;
-            sigB += expB ? UINT64_C( 0x2000000000000000 ) : sigB;
-            sigB = softfloat_shift64RightJam( sigB, expDiff );
-        }
-        sigZ = UINT64_C( 0x2000000000000000 ) + sigA + sigB;
-        if ( sigZ < UINT64_C( 0x4000000000000000 ) ) {
-            --expZ;
-            sigZ <<= 1;
-        }
-    }
-    return softfloat_roundPackToF64( signZ, expZ, sigZ );
- propagateNaN:
-    uiZ = softfloat_propagateNaNF64UI( uiA, uiB );
- uiZ:
-    uZ.ui = uiZ;
-    return uZ.f;
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/s_countLeadingZeros32.c b/softfloat/SoftFloat-3/source/s_countLeadingZeros32.c
deleted file mode 100755 (executable)
index 0bd17e1..0000000
--- a/softfloat/SoftFloat-3/source/s_countLeadingZeros32.c
+++ /dev/null
@@ -1,22 +0,0 @@
-
-#include <stdint.h>
-#include "primitives.h"
-
-int softfloat_countLeadingZeros32( uint32_t a )
-{
-    int count;
-
-    count = 0;
-    if ( a < 0x10000 ) {
-        count = 16;
-        a <<= 16;
-    }
-    if ( a < 0x1000000 ) {
-        count += 8;
-        a <<= 8;
-    }
-    count += softfloat_countLeadingZeros8[ a>>24 ];
-    return count;
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/s_countLeadingZeros64.c b/softfloat/SoftFloat-3/source/s_countLeadingZeros64.c
deleted file mode 100755 (executable)
index 4a96cf6..0000000
--- a/softfloat/SoftFloat-3/source/s_countLeadingZeros64.c
+++ /dev/null
@@ -1,31 +0,0 @@
-
-#include <stdint.h>
-#include "primitives.h"
-
-int softfloat_countLeadingZeros64( uint64_t a )
-{
-    int count;
-    uint32_t a32;
-
-    count = 32;
-    a32 = a;
-    if ( UINT64_C( 0x100000000 ) <= a ) {
-        count = 0;
-        a32 = a>>32;
-    }
-    /*------------------------------------------------------------------------
-    | From here, result is current count + count leading zeros of `a32'.
-    *------------------------------------------------------------------------*/
-    if ( a32 < 0x10000 ) {
-        count += 16;
-        a32 <<= 16;
-    }
-    if ( a32 < 0x1000000 ) {
-        count += 8;
-        a32 <<= 8;
-    }
-    count += softfloat_countLeadingZeros8[ a32>>24 ];
-    return count;
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/s_countLeadingZeros8.c b/softfloat/SoftFloat-3/source/s_countLeadingZeros8.c
deleted file mode 100755 (executable)
index 4eca7e9..0000000
--- a/softfloat/SoftFloat-3/source/s_countLeadingZeros8.c
+++ /dev/null
@@ -1,24 +0,0 @@
-
-#include <stdint.h>
-#include "platform.h"
-#include "primitives.h"
-
-const uint8_t softfloat_countLeadingZeros8[ 256 ] = {
-    8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4,
-    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
-    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
-    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
-    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
-    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
-    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-};
-

diff --git a/softfloat/SoftFloat-3/source/s_eq128.c b/softfloat/SoftFloat-3/source/s_eq128.c
deleted file mode 100755 (executable)
index 7261dc4..0000000
--- a/softfloat/SoftFloat-3/source/s_eq128.c
+++ /dev/null
@@ -1,13 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "primitives.h"
-
-bool softfloat_eq128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
-{
-
-    return ( a64 == b64 ) && ( a0 == b0 );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/s_estimateDiv128To64.c b/softfloat/SoftFloat-3/source/s_estimateDiv128To64.c
deleted file mode 100755 (executable)
index f8610a2..0000000
--- a/softfloat/SoftFloat-3/source/s_estimateDiv128To64.c
+++ /dev/null
@@ -1,28 +0,0 @@
-
-#include <stdint.h>
-#include "platform.h"
-#include "primitives.h"
-
-uint64_t softfloat_estimateDiv128To64( uint64_t a64, uint64_t a0, uint64_t b )
-{
-    uint32_t b32;
-    uint64_t z;
-    struct uint128 term, rem;
-    uint64_t rem32;
-
-    if ( b <= a64 ) return UINT64_C( 0xFFFFFFFFFFFFFFFF );
-    b32 = b>>32;
-    z = ( (uint64_t) b32<<32 <= a64 ) ? UINT64_C( 0xFFFFFFFF00000000 )
-            : ( a64 / b32 )<<32;
-    term = softfloat_mul64To128( b, z );
-    rem = softfloat_sub128( a64, a0, term.v64, term.v0 );
-    while ( UINT64_C( 0x8000000000000000 ) <= rem.v64 ) {
-        z -= UINT64_C( 0x100000000 );
-        rem = softfloat_add128( rem.v64, rem.v0, b32, (uint64_t) ( b<<32 ) );
-    }
-    rem32 = ( rem.v64<<32 ) | ( rem.v0>>32 );
-    z |= ( (uint64_t) b32<<32 <= rem32 ) ? 0xFFFFFFFF : rem32 / b32;
-    return z;
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/s_estimateSqrt32.c b/softfloat/SoftFloat-3/source/s_estimateSqrt32.c
deleted file mode 100755 (executable)
index e22a9dc..0000000
--- a/softfloat/SoftFloat-3/source/s_estimateSqrt32.c
+++ /dev/null
@@ -1,37 +0,0 @@
-
-#include <stdint.h>
-#include "platform.h"
-#include "primitives.h"
-
-uint32_t softfloat_estimateSqrt32( unsigned int expA, uint32_t a )
-{
-    static const uint16_t sqrtOddAdjustments[] = {
-        0x0004, 0x0022, 0x005D, 0x00B1, 0x011D, 0x019F, 0x0236, 0x02E0,
-        0x039C, 0x0468, 0x0545, 0x0631, 0x072B, 0x0832, 0x0946, 0x0A67
-    };
-    static const uint16_t sqrtEvenAdjustments[] = {
-        0x0A2D, 0x08AF, 0x075A, 0x0629, 0x051A, 0x0429, 0x0356, 0x029E,
-        0x0200, 0x0179, 0x0109, 0x00AF, 0x0068, 0x0034, 0x0012, 0x0002
-    };
-    int index;
-    uint32_t z;
-    union { uint32_t ui; int32_t i; } u32;
-
-    index = ( a>>27 ) & 15;
-    if ( expA & 1 ) {
-        z = 0x4000 + ( a>>17 ) - sqrtOddAdjustments[ index ];
-        z = ( ( a / z )<<14 ) + ( z<<15 );
-        a >>= 1;
-    } else {
-        z = 0x8000 + ( a>>17 ) - sqrtEvenAdjustments[ index ];
-        z = a / z + z;
-        z = ( 0x20000 <= z ) ? 0xFFFF8000 : z<<15;
-        if ( z <= a ) {
-            u32.ui = a;
-            return u32.i>>1;
-        }
-    }
-    return (uint32_t) ( ( (uint64_t) a<<31 ) / z ) + ( z>>1 );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/s_le128.c b/softfloat/SoftFloat-3/source/s_le128.c
deleted file mode 100755 (executable)
index 83b1d7f..0000000
--- a/softfloat/SoftFloat-3/source/s_le128.c
+++ /dev/null
@@ -1,13 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-\r
-bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )\r
-{\r
-\r
-    return ( a64 < b64 ) || ( ( a64 == b64 ) && ( a0 <= b0 ) );\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/s_lt128.c b/softfloat/SoftFloat-3/source/s_lt128.c
deleted file mode 100755 (executable)
index 33a3df4..0000000
--- a/softfloat/SoftFloat-3/source/s_lt128.c
+++ /dev/null
@@ -1,13 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-\r
-bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )\r
-{\r
-\r
-    return ( a64 < b64 ) || ( ( a64 == b64 ) && ( a0 < b0 ) );\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/s_mul128By64To192.c b/softfloat/SoftFloat-3/source/s_mul128By64To192.c
deleted file mode 100755 (executable)
index dfa8825..0000000
--- a/softfloat/SoftFloat-3/source/s_mul128By64To192.c
+++ /dev/null
@@ -1,20 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-\r
-struct uint192\r
- softfloat_mul128By64To192( uint64_t a64, uint64_t a0, uint64_t b )\r
-{\r
-    struct uint128 p0, p64;\r
-    struct uint192 z;\r
-\r
-    p0 = softfloat_mul64To128( a0, b );\r
-    z.v0 = p0.v0;\r
-    p64 = softfloat_mul64To128( a64, b );\r
-    z.v64 = p64.v0 + p0.v64;\r
-    z.v128 = p64.v64 + ( z.v64 < p64.v0 );\r
-    return z;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/s_mul128To256.c b/softfloat/SoftFloat-3/source/s_mul128To256.c
deleted file mode 100755 (executable)
index a96cd94..0000000
--- a/softfloat/SoftFloat-3/source/s_mul128To256.c
+++ /dev/null
@@ -1,28 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-\r
-struct uint256\r
- softfloat_mul128To256( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )\r
-{\r
-    struct uint128 p0, p64, p128;\r
-    struct uint256 z;\r
-\r
-    p0 = softfloat_mul64To128( a0, b0 );\r
-    z.v0 = p0.v0;\r
-    p64 = softfloat_mul64To128( a64, b0 );\r
-    z.v64 = p64.v0 + p0.v64;\r
-    z.v128 = p64.v64 + ( z.v64 < p64.v0 );\r
-    p128 = softfloat_mul64To128( a64, b64 );\r
-    z.v128 += p128.v0;\r
-    z.v192 = p128.v64 + ( z.v128 < p128.v0 );\r
-    p64 = softfloat_mul64To128( a0, b64 );\r
-    z.v64 += p64.v0;\r
-    p64.v64 += ( z.v64 < p64.v0 );\r
-    z.v128 += p64.v64;\r
-    z.v192 += ( z.v128 < p64.v64 );\r
-    return z;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/s_mul64To128.c b/softfloat/SoftFloat-3/source/s_mul64To128.c
deleted file mode 100755 (executable)
index c17780b..0000000
--- a/softfloat/SoftFloat-3/source/s_mul64To128.c
+++ /dev/null
@@ -1,28 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-\r
-struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b )\r
-{\r
-    uint32_t a32, a0, b32, b0;\r
-    struct uint128 z;\r
-    uint64_t mid1, mid2, mid;\r
-\r
-    a32 = a>>32;\r
-    a0 = a;\r
-    b32 = b>>32;\r
-    b0 = b;\r
-    z.v0 = (uint64_t) a0 * b0;\r
-    mid1 = (uint64_t) a32 * b0;\r
-    mid2 = (uint64_t) a0 * b32;\r
-    z.v64 = (uint64_t) a32 * b32;\r
-    mid = mid1 + mid2;\r
-    z.v64 += ( (uint64_t) ( mid < mid1 ) )<<32 | mid>>32;\r
-    mid <<= 32;\r
-    z.v0 += mid;\r
-    z.v64 += ( z.v0 < mid );\r
-    return z;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/s_mulAddF32.c b/softfloat/SoftFloat-3/source/s_mulAddF32.c
deleted file mode 100755 (executable)
index e55a0ba..0000000
--- a/softfloat/SoftFloat-3/source/s_mulAddF32.c
+++ /dev/null
@@ -1,171 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-#include "specialize.h"\r
-#include "softfloat.h"\r
-\r
-float32_t\r
- softfloat_mulAddF32(\r
-     int op, uint_fast32_t uiA, uint_fast32_t uiB, uint_fast32_t uiC )\r
-{\r
-    bool signA;\r
-    int_fast16_t expA;\r
-    uint_fast32_t sigA;\r
-    bool signB;\r
-    int_fast16_t expB;\r
-    uint_fast32_t sigB;\r
-    bool signC;\r
-    int_fast16_t expC;\r
-    uint_fast32_t sigC;\r
-    bool signProd;\r
-    uint_fast32_t magBits, uiZ;\r
-    struct exp16_sig32 normExpSig;\r
-    int_fast16_t expProd;\r
-    uint_fast64_t sigProd;\r
-    bool signZ;\r
-    int_fast16_t expZ;\r
-    uint_fast32_t sigZ;\r
-    int_fast16_t expDiff;\r
-    uint_fast64_t sigZ64, sigC64;\r
-    int shiftCount;\r
-    union ui32_f32 uZ;\r
-\r
-    signA = signF32UI( uiA );\r
-    expA = expF32UI( uiA );\r
-    sigA = fracF32UI( uiA );\r
-    signB = signF32UI( uiB );\r
-    expB = expF32UI( uiB );\r
-    sigB = fracF32UI( uiB );\r
-    signC = signF32UI( uiC ) ^ ( op == softfloat_mulAdd_subC );\r
-    expC = expF32UI( uiC );\r
-    sigC = fracF32UI( uiC );\r
-    signProd = signA ^ signB ^ ( op == softfloat_mulAdd_subProd );\r
-    if ( expA == 0xFF ) {\r
-        if ( sigA || ( ( expB == 0xFF ) && sigB ) ) goto propagateNaN_ABC;\r
-        magBits = expB | sigB;\r
-        goto infProdArg;\r
-    }\r
-    if ( expB == 0xFF ) {\r
-        if ( sigB ) goto propagateNaN_ABC;\r
-        magBits = expA | sigA;\r
-        goto infProdArg;\r
-    }\r
-    if ( expC == 0xFF ) {\r
-        if ( sigC ) {\r
-            uiZ = 0;\r
-            goto propagateNaN_ZC;\r
-        }\r
-        uiZ = uiC;\r
-        goto uiZ;\r
-    }\r
-    if ( ! expA ) {\r
-        if ( ! sigA ) goto zeroProd;\r
-        normExpSig = softfloat_normSubnormalF32Sig( sigA );\r
-        expA = normExpSig.exp;\r
-        sigA = normExpSig.sig;\r
-    }\r
-    if ( ! expB ) {\r
-        if ( ! sigB ) goto zeroProd;\r
-        normExpSig = softfloat_normSubnormalF32Sig( sigB );\r
-        expB = normExpSig.exp;\r
-        sigB = normExpSig.sig;\r
-    }\r
-    expProd = expA + expB - 0x7E;\r
-    sigA = ( sigA | 0x00800000 )<<7;\r
-    sigB = ( sigB | 0x00800000 )<<7;\r
-    sigProd = (uint_fast64_t) sigA * sigB;\r
-    if ( sigProd < UINT64_C( 0x2000000000000000 ) ) {\r
-        --expProd;\r
-        sigProd <<= 1;\r
-    }\r
-    signZ = signProd;\r
-    if ( ! expC ) {\r
-        if ( ! sigC ) {\r
-            expZ = expProd - 1;\r
-            sigZ = softfloat_shortShift64RightJam( sigProd, 31 );\r
-            goto roundPack;\r
-        }\r
-        normExpSig = softfloat_normSubnormalF32Sig( sigC );\r
-        expC = normExpSig.exp;\r
-        sigC = normExpSig.sig;\r
-    }\r
-    sigC = ( sigC | 0x00800000 )<<6;\r
-    expDiff = expProd - expC;\r
-    if ( signProd == signC ) {\r
-        if ( expDiff <= 0 ) {\r
-            expZ = expC;\r
-            sigZ = sigC + softfloat_shift64RightJam( sigProd, 32 - expDiff );\r
-        } else {\r
-            expZ = expProd;\r
-            sigZ64 =\r
-                sigProd\r
-                    + softfloat_shift64RightJam(\r
-                          (uint_fast64_t) sigC<<32, expDiff );\r
-            sigZ = softfloat_shortShift64RightJam( sigZ64, 32 );\r
-        }\r
-        if ( sigZ < 0x40000000 ) {\r
-            --expZ;\r
-            sigZ <<= 1;\r
-        }\r
-    } else {\r
-/*** OPTIMIZE BETTER? ***/\r
-        sigC64 = (uint_fast64_t) sigC<<32;\r
-        if ( expDiff < 0 ) {\r
-            signZ = signC;\r
-            expZ = expC;\r
-            sigZ64 = sigC64 - softfloat_shift64RightJam( sigProd, - expDiff );\r
-        } else if ( ! expDiff ) {\r
-            expZ = expProd;\r
-            sigZ64 = sigProd - sigC64;\r
-            if ( ! sigZ64 ) goto completeCancellation;\r
-            if ( sigZ64 & UINT64_C( 0x8000000000000000 ) ) {\r
-                signZ ^= 1;\r
-                sigZ64 = - sigZ64;\r
-            }\r
-        } else {\r
-            expZ = expProd;\r
-            sigZ64 = sigProd - softfloat_shift64RightJam( sigC64, expDiff );\r
-        }\r
-        shiftCount = softfloat_countLeadingZeros64( sigZ64 ) - 1;\r
-        expZ -= shiftCount;\r
-        shiftCount -= 32;\r
-        if ( shiftCount < 0 ) {\r
-            sigZ = softfloat_shortShift64RightJam( sigZ64, - shiftCount );\r
-        } else {\r
-            sigZ = (uint_fast32_t) sigZ64<<shiftCount;\r
-        }\r
-    }\r
- roundPack:\r
-    return softfloat_roundPackToF32( signZ, expZ, sigZ );\r
- propagateNaN_ABC:\r
-    uiZ = softfloat_propagateNaNF32UI( uiA, uiB );\r
-    goto propagateNaN_ZC;\r
- infProdArg:\r
-    if ( magBits ) {\r
-        uiZ = packToF32UI( signProd, 0xFF, 0 );\r
-        if ( expC != 0xFF ) goto uiZ;\r
-        if ( sigC ) goto propagateNaN_ZC;\r
-        if ( signProd == signC ) goto uiZ;\r
-    }\r
- invalid:\r
-    softfloat_raiseFlags( softfloat_flag_invalid );\r
-    uiZ = defaultNaNF32UI;\r
- propagateNaN_ZC:\r
-    uiZ = softfloat_propagateNaNF32UI( uiZ, uiC );\r
-    goto uiZ;\r
- zeroProd:\r
-    uiZ = uiC;\r
-    if ( ! ( expC | sigC ) && ( signProd != signC ) ) {\r
- completeCancellation:\r
-        uiZ =\r
-            packToF32UI( softfloat_roundingMode == softfloat_round_min, 0, 0 );\r
-    }\r
- uiZ:\r
-    uZ.ui = uiZ;\r
-    return uZ.f;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/s_mulAddF64.c b/softfloat/SoftFloat-3/source/s_mulAddF64.c
deleted file mode 100755 (executable)
index 01ba3b4..0000000
--- a/softfloat/SoftFloat-3/source/s_mulAddF64.c
+++ /dev/null
@@ -1,188 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-#include "specialize.h"\r
-#include "softfloat.h"\r
-\r
-float64_t\r
- softfloat_mulAddF64(\r
-     int op, uint_fast64_t uiA, uint_fast64_t uiB, uint_fast64_t uiC )\r
-{\r
-    bool signA;\r
-    int_fast16_t expA;\r
-    uint_fast64_t sigA;\r
-    bool signB;\r
-    int_fast16_t expB;\r
-    uint_fast64_t sigB;\r
-    bool signC;\r
-    int_fast16_t expC;\r
-    uint_fast64_t sigC;\r
-    bool signProd;\r
-    uint_fast64_t magBits, uiZ;\r
-    struct exp16_sig64 normExpSig;\r
-    int_fast16_t expProd;\r
-    struct uint128 sigProd;\r
-    bool signZ;\r
-    int_fast16_t expZ;\r
-    uint_fast64_t sigZ;\r
-    int_fast16_t expDiff;\r
-    struct uint128 sigC128, sigZ128;\r
-    int shiftCount;\r
-    union ui64_f64 uZ;\r
-\r
-    signA = signF64UI( uiA );\r
-    expA = expF64UI( uiA );\r
-    sigA = fracF64UI( uiA );\r
-    signB = signF64UI( uiB );\r
-    expB = expF64UI( uiB );\r
-    sigB = fracF64UI( uiB );\r
-    signC = signF64UI( uiC ) ^ ( op == softfloat_mulAdd_subC );\r
-    expC = expF64UI( uiC );\r
-    sigC = fracF64UI( uiC );\r
-    signProd = signA ^ signB ^ ( op == softfloat_mulAdd_subProd );\r
-    if ( expA == 0x7FF ) {\r
-        if ( sigA || ( ( expB == 0x7FF ) && sigB ) ) goto propagateNaN_ABC;\r
-        magBits = expB | sigB;\r
-        goto infProdArg;\r
-    }\r
-    if ( expB == 0x7FF ) {\r
-        if ( sigB ) goto propagateNaN_ABC;\r
-        magBits = expA | sigA;\r
-        goto infProdArg;\r
-    }\r
-    if ( expC == 0x7FF ) {\r
-        if ( sigC ) {\r
-            uiZ = 0;\r
-            goto propagateNaN_ZC;\r
-        }\r
-        uiZ = uiC;\r
-        goto uiZ;\r
-    }\r
-    if ( ! expA ) {\r
-        if ( ! sigA ) goto zeroProd;\r
-        normExpSig = softfloat_normSubnormalF64Sig( sigA );\r
-        expA = normExpSig.exp;\r
-        sigA = normExpSig.sig;\r
-    }\r
-    if ( ! expB ) {\r
-        if ( ! sigB ) goto zeroProd;\r
-        normExpSig = softfloat_normSubnormalF64Sig( sigB );\r
-        expB = normExpSig.exp;\r
-        sigB = normExpSig.sig;\r
-    }\r
-    expProd = expA + expB - 0x3FE;\r
-    sigA = ( sigA | UINT64_C( 0x0010000000000000 ) )<<10;\r
-    sigB = ( sigB | UINT64_C( 0x0010000000000000 ) )<<10;\r
-    sigProd = softfloat_mul64To128( sigA, sigB );\r
-    if ( sigProd.v64 < UINT64_C( 0x2000000000000000 ) ) {\r
-        --expProd;\r
-        sigProd = softfloat_shortShift128Left( sigProd.v64, sigProd.v0, 1 );\r
-    }\r
-    signZ = signProd;\r
-    if ( ! expC ) {\r
-        if ( ! sigC ) {\r
-            expZ = expProd - 1;\r
-            sigZ = sigProd.v64<<1 | ( sigProd.v0 != 0 );\r
-            goto roundPack;\r
-        }\r
-        normExpSig = softfloat_normSubnormalF64Sig( sigC );\r
-        expC = normExpSig.exp;\r
-        sigC = normExpSig.sig;\r
-    }\r
-    sigC = ( sigC | UINT64_C( 0x0010000000000000 ) )<<9;\r
-    expDiff = expProd - expC;\r
-    if ( signProd == signC ) {\r
-        if ( expDiff <= 0 ) {\r
-            expZ = expC;\r
-            if ( expDiff ) {\r
-                sigProd.v64 =\r
-                    softfloat_shift64RightJam( sigProd.v64, - expDiff );\r
-            }\r
-            sigZ = ( sigC + sigProd.v64 ) | ( sigProd.v0 != 0 );\r
-        } else {\r
-            expZ = expProd;\r
-            sigC128 = softfloat_shift128RightJam( sigC, 0, expDiff );\r
-            sigZ128 =\r
-                softfloat_add128(\r
-                    sigProd.v64, sigProd.v0, sigC128.v64, sigC128.v0 );\r
-            sigZ = sigZ128.v64 | ( sigZ128.v0 != 0 );\r
-        }\r
-        if ( sigZ < UINT64_C( 0x4000000000000000 ) ) {\r
-            --expZ;\r
-            sigZ <<= 1;\r
-        }\r
-    } else {\r
-/*** OPTIMIZE BETTER? ***/\r
-        if ( expDiff < 0 ) {\r
-            signZ = signC;\r
-            expZ = expC;\r
-            sigProd =\r
-                softfloat_shift128RightJam(\r
-                    sigProd.v64, sigProd.v0, - expDiff );\r
-            sigZ128 = softfloat_sub128( sigC, 0, sigProd.v64, sigProd.v0 );\r
-        } else if ( ! expDiff ) {\r
-            expZ = expProd;\r
-            sigZ128 = softfloat_sub128( sigProd.v64, sigProd.v0, sigC, 0 );\r
-            if ( ! ( sigZ128.v64 | sigZ128.v0 ) ) goto completeCancellation;\r
-            if ( sigZ128.v64 & UINT64_C( 0x8000000000000000 ) ) {\r
-                signZ ^= 1;\r
-                sigZ128 = softfloat_sub128( 0, 0, sigZ128.v64, sigZ128.v0 );\r
-            }\r
-        } else {\r
-            expZ = expProd;\r
-            sigC128 = softfloat_shift128RightJam( sigC, 0, expDiff );\r
-            sigZ128 =\r
-                softfloat_sub128(\r
-                    sigProd.v64, sigProd.v0, sigC128.v64, sigC128.v0 );\r
-        }\r
-        if ( ! sigZ128.v64 ) {\r
-            expZ -= 64;\r
-            sigZ128.v64 = sigZ128.v0;\r
-            sigZ128.v0 = 0;\r
-        }\r
-        shiftCount = softfloat_countLeadingZeros64( sigZ128.v64 ) - 1;\r
-        expZ -= shiftCount;\r
-        if ( shiftCount < 0 ) {\r
-            sigZ = softfloat_shortShift64RightJam( sigZ128.v64, - shiftCount );\r
-        } else {\r
-            sigZ128 =\r
-                softfloat_shortShift128Left(\r
-                    sigZ128.v64, sigZ128.v0, shiftCount );\r
-            sigZ = sigZ128.v64;\r
-        }\r
-        sigZ |= ( sigZ128.v0 != 0 );\r
-    }\r
- roundPack:\r
-    return softfloat_roundPackToF64( signZ, expZ, sigZ );\r
- propagateNaN_ABC:\r
-    uiZ = softfloat_propagateNaNF64UI( uiA, uiB );\r
-    goto propagateNaN_ZC;\r
- infProdArg:\r
-    if ( magBits ) {\r
-        uiZ = packToF64UI( signProd, 0x7FF, 0 );\r
-        if ( expC != 0x7FF ) goto uiZ;\r
-        if ( sigC ) goto propagateNaN_ZC;\r
-        if ( signProd == signC ) goto uiZ;\r
-    }\r
- invalid:\r
-    softfloat_raiseFlags( softfloat_flag_invalid );\r
-    uiZ = defaultNaNF64UI;\r
- propagateNaN_ZC:\r
-    uiZ = softfloat_propagateNaNF64UI( uiZ, uiC );\r
-    goto uiZ;\r
- zeroProd:\r
-    uiZ = uiC;\r
-    if ( ! ( expC | sigC ) && ( signProd != signC ) ) {\r
- completeCancellation:\r
-        uiZ =\r
-            packToF64UI( softfloat_roundingMode == softfloat_round_min, 0, 0 );\r
-    }\r
- uiZ:\r
-    uZ.ui = uiZ;\r
-    return uZ.f;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/s_normRoundPackToF32.c b/softfloat/SoftFloat-3/source/s_normRoundPackToF32.c
deleted file mode 100755 (executable)
index 2e6f4b0..0000000
--- a/softfloat/SoftFloat-3/source/s_normRoundPackToF32.c
+++ /dev/null
@@ -1,24 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-\r
-float32_t\r
- softfloat_normRoundPackToF32( bool sign, int_fast16_t exp, uint_fast32_t sig )\r
-{\r
-    int shiftCount;\r
-    union ui32_f32 uZ;\r
-\r
-    shiftCount = softfloat_countLeadingZeros32( sig ) - 1;\r
-    exp -= shiftCount;\r
-    if ( ( 7 <= shiftCount ) && ( (uint16_t) exp < 0xFD ) ) {\r
-        uZ.ui = packToF32UI( sign, sig ? exp : 0, sig<<( shiftCount - 7 ) );\r
-        return uZ.f;\r
-    } else {\r
-        return softfloat_roundPackToF32( sign, exp, sig<<shiftCount );\r
-    }\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/s_normRoundPackToF64.c b/softfloat/SoftFloat-3/source/s_normRoundPackToF64.c
deleted file mode 100755 (executable)
index 64dced4..0000000
--- a/softfloat/SoftFloat-3/source/s_normRoundPackToF64.c
+++ /dev/null
@@ -1,24 +0,0 @@
-\r
-#include <stdbool.h>\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-\r
-float64_t\r
- softfloat_normRoundPackToF64( bool sign, int_fast16_t exp, uint_fast64_t sig )\r
-{\r
-    int shiftCount;\r
-    union ui64_f64 uZ;\r
-\r
-    shiftCount = softfloat_countLeadingZeros64( sig ) - 1;\r
-    exp -= shiftCount;\r
-    if ( ( 10 <= shiftCount ) && ( (uint16_t) exp < 0x7FD ) ) {\r
-        uZ.ui = packToF64UI( sign, sig ? exp : 0, sig<<( shiftCount - 10 ) );\r
-        return uZ.f;\r
-    } else {\r
-        return softfloat_roundPackToF64( sign, exp, sig<<shiftCount );\r
-    }\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/s_normSubnormalF32Sig.c b/softfloat/SoftFloat-3/source/s_normSubnormalF32Sig.c
deleted file mode 100755 (executable)
index b98eb86..0000000
--- a/softfloat/SoftFloat-3/source/s_normSubnormalF32Sig.c
+++ /dev/null
@@ -1,18 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-\r
-struct exp16_sig32 softfloat_normSubnormalF32Sig( uint_fast32_t sig )\r
-{\r
-    int shiftCount;\r
-    struct exp16_sig32 z;\r
-\r
-    shiftCount = softfloat_countLeadingZeros32( sig ) - 8;\r
-    z.exp = 1 - shiftCount;\r
-    z.sig = sig<<shiftCount;\r
-    return z;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/s_normSubnormalF64Sig.c b/softfloat/SoftFloat-3/source/s_normSubnormalF64Sig.c
deleted file mode 100755 (executable)
index 45a7c9e..0000000
--- a/softfloat/SoftFloat-3/source/s_normSubnormalF64Sig.c
+++ /dev/null
@@ -1,18 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-\r
-struct exp16_sig64 softfloat_normSubnormalF64Sig( uint_fast64_t sig )\r
-{\r
-    int shiftCount;\r
-    struct exp16_sig64 z;\r
-\r
-    shiftCount = softfloat_countLeadingZeros64( sig ) - 11;\r
-    z.exp = 1 - shiftCount;\r
-    z.sig = sig<<shiftCount;\r
-    return z;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/s_roundPackToF32.c b/softfloat/SoftFloat-3/source/s_roundPackToF32.c
deleted file mode 100755 (executable)
index 11764f1..0000000
--- a/softfloat/SoftFloat-3/source/s_roundPackToF32.c
+++ /dev/null
@@ -1,65 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "primitives.h"
-#include "internals.h"
-#include "softfloat.h"
-
-float32_t
- softfloat_roundPackToF32( bool sign, int_fast16_t exp, uint_fast32_t sig )
-{
-    int roundingMode;
-    bool roundNearestEven;
-    int roundIncrement, roundBits;
-    bool isTiny;
-    uint_fast32_t uiZ;
-    union ui32_f32 uZ;
-
-    roundingMode = softfloat_roundingMode;
-    roundNearestEven = ( roundingMode == softfloat_round_nearest_even );
-    roundIncrement = 0x40;
-    if (
-           ! roundNearestEven
-        && ( roundingMode != softfloat_round_nearest_maxMag )
-    ) {
-        roundIncrement =
-               ( roundingMode == softfloat_round_minMag )
-            || ( roundingMode
-                     == ( sign ? softfloat_round_max : softfloat_round_min ) )
-                ? 0
-                : 0x7F;
-    }
-    roundBits = sig & 0x7F;
-    if ( 0xFD <= (uint16_t) exp ) {
-        if ( exp < 0 ) {
-            isTiny =
-                   ( softfloat_detectTininess
-                         == softfloat_tininess_beforeRounding )
-                || ( exp < -1 )
-                || ( sig + roundIncrement < 0x80000000 );
-            sig = softfloat_shift32RightJam( sig, - exp );
-            exp = 0;
-            roundBits = sig & 0x7F;
-            if ( isTiny && roundBits ) {
-                softfloat_raiseFlags( softfloat_flag_underflow );
-            }
-        } else if (
-            ( 0xFD < exp ) || ( 0x80000000 <= sig + roundIncrement )
-        ) {
-            softfloat_raiseFlags(
-                softfloat_flag_overflow | softfloat_flag_inexact );
-            uiZ = packToF32UI( sign, 0xFF, 0 ) - ! roundIncrement;
-            goto uiZ;
-        }
-    }
-    if ( roundBits ) softfloat_exceptionFlags |= softfloat_flag_inexact;
-    sig = ( sig + roundIncrement )>>7;
-    sig &= ~ ( ! ( roundBits ^ 0x40 ) & roundNearestEven );
-    uiZ = packToF32UI( sign, sig ? exp : 0, sig );
- uiZ:
-    uZ.ui = uiZ;
-    return uZ.f;
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/s_roundPackToF64.c b/softfloat/SoftFloat-3/source/s_roundPackToF64.c
deleted file mode 100755 (executable)
index fb0ef1d..0000000
--- a/softfloat/SoftFloat-3/source/s_roundPackToF64.c
+++ /dev/null
@@ -1,66 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "primitives.h"
-#include "internals.h"
-#include "softfloat.h"
-
-float64_t
- softfloat_roundPackToF64( bool sign, int_fast16_t exp, uint_fast64_t sig )
-{
-    int roundingMode;
-    bool roundNearestEven;
-    int roundIncrement, roundBits;
-    bool isTiny;
-    uint_fast64_t uiZ;
-    union ui64_f64 uZ;
-
-    roundingMode = softfloat_roundingMode;
-    roundNearestEven = ( roundingMode == softfloat_round_nearest_even );
-    roundIncrement = 0x200;
-    if (
-           ! roundNearestEven
-        && ( roundingMode != softfloat_round_nearest_maxMag )
-    ) {
-        roundIncrement =
-               ( roundingMode == softfloat_round_minMag )
-            || ( roundingMode
-                     == ( sign ? softfloat_round_max : softfloat_round_min ) )
-                ? 0
-                : 0x3FF;
-    }
-    roundBits = sig & 0x3FF;
-    if ( 0x7FD <= (uint16_t) exp ) {
-        if ( exp < 0 ) {
-            isTiny =
-                   ( softfloat_detectTininess
-                         == softfloat_tininess_beforeRounding )
-                || ( exp < -1 )
-                || ( sig + roundIncrement < UINT64_C( 0x8000000000000000 ) );
-            sig = softfloat_shift64RightJam( sig, - exp );
-            exp = 0;
-            roundBits = sig & 0x3FF;
-            if ( isTiny && roundBits ) {
-                softfloat_raiseFlags( softfloat_flag_underflow );
-            }
-        } else if (
-            ( 0x7FD < exp )
-                || ( UINT64_C( 0x8000000000000000 ) <= sig + roundIncrement )
-        ) {
-            softfloat_raiseFlags(
-                softfloat_flag_overflow | softfloat_flag_inexact );
-            uiZ = packToF64UI( sign, 0x7FF, 0 ) - ! roundIncrement;
-            goto uiZ;
-        }
-    }
-    if ( roundBits ) softfloat_exceptionFlags |= softfloat_flag_inexact;
-    sig = ( sig + roundIncrement )>>10;
-    sig &= ~ ( ! ( roundBits ^ 0x200 ) & roundNearestEven );
-    uiZ = packToF64UI( sign, sig ? exp : 0, sig );
- uiZ:
-    uZ.ui = uiZ;
-    return uZ.f;
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/s_roundPackToI32.c b/softfloat/SoftFloat-3/source/s_roundPackToI32.c
deleted file mode 100755 (executable)
index 1c91497..0000000
--- a/softfloat/SoftFloat-3/source/s_roundPackToI32.c
+++ /dev/null
@@ -1,48 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "softfloat.h"
-
-int_fast32_t
- softfloat_roundPackToI32(
-     bool sign, uint_fast64_t sig, int_fast8_t roundingMode, bool exact )
-{
-    bool roundNearestEven;
-    int roundIncrement, roundBits;
-    uint_fast32_t sig32;
-    union { uint32_t ui; int32_t i; } uZ;
-    int_fast32_t z;
-
-    roundNearestEven = ( roundingMode == softfloat_round_nearest_even );
-    roundIncrement = 0x40;
-    if (
-           ! roundNearestEven
-        && ( roundingMode != softfloat_round_nearest_maxMag )
-    ) {
-        roundIncrement =
-               ( roundingMode == softfloat_round_minMag )
-            || ( roundingMode
-                     == ( sign ? softfloat_round_max : softfloat_round_min ) )
-                ? 0
-                : 0x7F;
-    }
-    roundBits = sig & 0x7F;
-    sig += roundIncrement;
-    if ( sig & UINT64_C( 0xFFFFFF8000000000 ) ) goto invalid;
-    sig32 = sig>>7;
-    sig32 &= ~ ( ! ( roundBits ^ 0x40 ) & roundNearestEven );
-    uZ.ui = sign ? - sig32 : sig32;
-    z = uZ.i;
-    if ( z && ( ( z < 0 ) ^ sign ) ) goto invalid;
-    if ( exact && roundBits ) {
-        softfloat_exceptionFlags |= softfloat_flag_inexact;
-    }
-    return z;
- invalid:
-    softfloat_raiseFlags( softfloat_flag_invalid );
-    return sign ? -0x7FFFFFFF - 1 : 0x7FFFFFFF;
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/s_roundPackToI64.c b/softfloat/SoftFloat-3/source/s_roundPackToI64.c
deleted file mode 100755 (executable)
index b2f5d63..0000000
--- a/softfloat/SoftFloat-3/source/s_roundPackToI64.c
+++ /dev/null
@@ -1,52 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "softfloat.h"
-
-int_fast64_t
- softfloat_roundPackToI64(
-     bool sign,
-     uint_fast64_t sig64,
-     uint_fast64_t sig0,
-     int_fast8_t roundingMode,
-     bool exact
- )
-{
-    bool roundNearestEven, increment;
-    union { uint64_t ui; int64_t i; } uZ;
-    int_fast64_t z;
-
-    roundNearestEven = ( roundingMode == softfloat_round_nearest_even );
-    increment = ( UINT64_C( 0x8000000000000000 ) <= sig0 );
-    if (
-           ! roundNearestEven
-        && ( roundingMode != softfloat_round_nearest_maxMag )
-    ) {
-        increment =
-               ( roundingMode != softfloat_round_minMag )
-            && ( roundingMode
-                     == ( sign ? softfloat_round_min : softfloat_round_max ) )
-            && sig0;
-    }
-    if ( increment ) {
-        ++sig64;
-        if ( ! sig64 ) goto invalid;
-        sig64 &=
-            ~ ( ! ( sig0 & UINT64_C( 0x7FFFFFFFFFFFFFFF ) )
-                    & roundNearestEven );
-    }
-    uZ.ui = sign ? - sig64 : sig64;
-    z = uZ.i;
-    if ( z && ( ( z < 0 ) ^ sign ) ) goto invalid;
-    if ( exact && sig0 ) softfloat_exceptionFlags |= softfloat_flag_inexact;
-    return z;
- invalid:
-    softfloat_raiseFlags( softfloat_flag_invalid );
-    return
-        sign ? - INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1
-            : INT64_C( 0x7FFFFFFFFFFFFFFF );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/s_roundPackToUI32.c b/softfloat/SoftFloat-3/source/s_roundPackToUI32.c
deleted file mode 100755 (executable)
index ab44ec7..0000000
--- a/softfloat/SoftFloat-3/source/s_roundPackToUI32.c
+++ /dev/null
@@ -1,44 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "softfloat.h"
-
-uint_fast32_t
- softfloat_roundPackToUI32(
-     bool sign, uint_fast64_t sig, int_fast8_t roundingMode, bool exact )
-{
-    bool roundNearestEven;
-    int roundIncrement, roundBits;
-    uint_fast32_t z;
-
-    roundNearestEven = ( roundingMode == softfloat_round_nearest_even );
-    roundIncrement = 0x40;
-    if (
-           ! roundNearestEven
-        && ( roundingMode != softfloat_round_nearest_maxMag )
-    ) {
-        roundIncrement =
-               ( roundingMode == softfloat_round_minMag )
-            || ( roundingMode
-                     == ( sign ? softfloat_round_max : softfloat_round_min ) )
-                ? 0
-                : 0x7F;
-    }
-    roundBits = sig & 0x7F;
-    sig += roundIncrement;
-    if ( sig & UINT64_C( 0xFFFFFF8000000000 ) ) goto invalid;
-    z = sig>>7;
-    z &= ~ ( ! ( roundBits ^ 0x40 ) & roundNearestEven );
-    if ( sign && z ) goto invalid;
-    if ( exact && roundBits ) {
-        softfloat_exceptionFlags |= softfloat_flag_inexact;
-    }
-    return z;
- invalid:
-    softfloat_raiseFlags( softfloat_flag_invalid );
-    return 0xFFFFFFFF;
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/s_roundPackToUI64.c b/softfloat/SoftFloat-3/source/s_roundPackToUI64.c
deleted file mode 100755 (executable)
index d42266f..0000000
--- a/softfloat/SoftFloat-3/source/s_roundPackToUI64.c
+++ /dev/null
@@ -1,46 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "internals.h"
-#include "softfloat.h"
-
-uint_fast64_t
- softfloat_roundPackToUI64(
-     bool sign,
-     uint_fast64_t sig64,
-     uint_fast64_t sig0,
-     int_fast8_t roundingMode,
-     bool exact
- )
-{
-    bool roundNearestEven, increment;
-
-    roundNearestEven = ( roundingMode == softfloat_round_nearest_even );
-    increment = ( UINT64_C( 0x8000000000000000 ) <= sig0 );
-    if (
-           ! roundNearestEven
-        && ( roundingMode != softfloat_round_nearest_maxMag )
-    ) {
-        increment =
-               ( roundingMode != softfloat_round_minMag )
-            && ( roundingMode
-                     == ( sign ? softfloat_round_min : softfloat_round_max ) )
-            && sig0;
-    }
-    if ( increment ) {
-        ++sig64;
-        if ( ! sig64 ) goto invalid;
-        sig64 &=
-            ~ ( ! ( sig0 & UINT64_C( 0x7FFFFFFFFFFFFFFF ) )
-                    & roundNearestEven );
-    }
-    if ( sign && sig64 ) goto invalid;
-    if ( exact && sig0 ) softfloat_exceptionFlags |= softfloat_flag_inexact;
-    return sig64;
- invalid:
-    softfloat_raiseFlags( softfloat_flag_invalid );
-    return UINT64_C( 0xFFFFFFFFFFFFFFFF );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/s_shift128ExtraRightJam.c b/softfloat/SoftFloat-3/source/s_shift128ExtraRightJam.c
deleted file mode 100755 (executable)
index 6c57974..0000000
--- a/softfloat/SoftFloat-3/source/s_shift128ExtraRightJam.c
+++ /dev/null
@@ -1,38 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-\r
-struct uint128_extra\r
- softfloat_shift128ExtraRightJam(\r
-     uint64_t a64, uint64_t a0, uint64_t extra, unsigned int count )\r
-{\r
-    unsigned int negCount;\r
-    struct uint128_extra z;\r
-\r
-    negCount = - count;\r
-    if ( count < 64 ) {\r
-        z.v64 = a64>>count;\r
-        z.v0 = a64<<( negCount & 63 ) | a0>>count;\r
-        z.extra = a0<<( negCount & 63 );\r
-    } else {\r
-        z.v64 = 0;\r
-        if ( count == 64 ) {\r
-            z.v0 = a64;\r
-            z.extra = a0;\r
-        } else {\r
-            extra |= a0;\r
-            if ( count < 128 ) {\r
-                z.v0 = a64>>( count & 63 );\r
-                z.extra = a64<<( negCount & 63 );\r
-            } else {\r
-                z.v0 = 0;\r
-                z.extra = ( count == 128 ) ? a64 : ( a64 != 0 );\r
-            }\r
-        }\r
-    }\r
-    z.extra |= ( extra != 0 );\r
-    return z;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/s_shift128RightJam.c b/softfloat/SoftFloat-3/source/s_shift128RightJam.c
deleted file mode 100755 (executable)
index 5a4e188..0000000
--- a/softfloat/SoftFloat-3/source/s_shift128RightJam.c
+++ /dev/null
@@ -1,31 +0,0 @@
-
-#include <stdint.h>
-#include "platform.h"
-#include "primitives.h"
-
-struct uint128
- softfloat_shift128RightJam( uint64_t a64, uint64_t a0, unsigned int count )
-{
-    unsigned int negCount;
-    struct uint128 z;
-
-    if ( count < 64 ) {
-        negCount = - count;
-        z.v64 = a64>>( count & 63 );
-        z.v0 =
-            a64<<( negCount & 63 ) | a0>>count
-                | ( (uint64_t) ( a0<<( negCount & 63 ) ) != 0 );
-    } else {
-        z.v64 = 0;
-        z.v0 =
-            ( count < 128 )
-                ? a64>>( count & 63 )
-                      | ( ( ( a64 & ( ( (uint64_t) 1<<( count & 63 ) ) - 1 ) )
-                                | a0 )
-                              != 0 )
-                : ( ( a64 | a0 ) != 0 );
-    }
-    return z;
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/s_shift32RightJam.c b/softfloat/SoftFloat-3/source/s_shift32RightJam.c
deleted file mode 100755 (executable)
index b697a34..0000000
--- a/softfloat/SoftFloat-3/source/s_shift32RightJam.c
+++ /dev/null
@@ -1,15 +0,0 @@
-
-#include <stdint.h>
-#include "platform.h"
-#include "primitives.h"
-
-uint32_t softfloat_shift32RightJam( uint32_t a, unsigned int count )
-{
-
-    return
-        ( count < 32 )
-            ? a>>count | ( (uint32_t) ( a<<( ( - count ) & 31 ) ) != 0 )
-            : ( a != 0 );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/s_shift64ExtraRightJam.c b/softfloat/SoftFloat-3/source/s_shift64ExtraRightJam.c
deleted file mode 100755 (executable)
index 167ea54..0000000
--- a/softfloat/SoftFloat-3/source/s_shift64ExtraRightJam.c
+++ /dev/null
@@ -1,23 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-\r
-struct uint64_extra\r
- softfloat_shift64ExtraRightJam(\r
-     uint64_t a, uint64_t extra, unsigned int count )\r
-{\r
-    struct uint64_extra z;\r
-\r
-    if ( count < 64 ) {\r
-        z.v = a>>count;\r
-        z.extra = a<<( ( - count ) & 63 );\r
-    } else {\r
-        z.v = 0;\r
-        z.extra = ( count == 64 ) ? a : ( a != 0 );\r
-    }\r
-    z.extra |= ( extra != 0 );\r
-    return z;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/s_shift64RightJam.c b/softfloat/SoftFloat-3/source/s_shift64RightJam.c
deleted file mode 100755 (executable)
index ebebb61..0000000
--- a/softfloat/SoftFloat-3/source/s_shift64RightJam.c
+++ /dev/null
@@ -1,15 +0,0 @@
-
-#include <stdint.h>
-#include "platform.h"
-#include "primitives.h"
-
-uint64_t softfloat_shift64RightJam( uint64_t a, unsigned int count )
-{
-
-    return
-        ( count < 64 )
-            ? a>>count | ( (uint64_t) ( a<<( ( - count ) & 63 ) ) != 0 )
-            : ( a != 0 );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/s_shortShift128ExtraRightJam.c b/softfloat/SoftFloat-3/source/s_shortShift128ExtraRightJam.c
deleted file mode 100755 (executable)
index c772740..0000000
--- a/softfloat/SoftFloat-3/source/s_shortShift128ExtraRightJam.c
+++ /dev/null
@@ -1,20 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-\r
-struct uint128_extra\r
- softfloat_shortShift128ExtraRightJam(\r
-     uint64_t a64, uint64_t a0, uint64_t extra, unsigned int count )\r
-{\r
-    unsigned int negCount;\r
-    struct uint128_extra z;\r
-\r
-    negCount = - count;\r
-    z.v64 = a64>>count;\r
-    z.v0 = a64<<( negCount & 63 ) | a0>>count;\r
-    z.extra = a0<<( negCount & 63 ) | ( extra != 0 );\r
-    return z;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/s_shortShift128Left.c b/softfloat/SoftFloat-3/source/s_shortShift128Left.c
deleted file mode 100755 (executable)
index 9c29988..0000000
--- a/softfloat/SoftFloat-3/source/s_shortShift128Left.c
+++ /dev/null
@@ -1,16 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-\r
-struct uint128\r
- softfloat_shortShift128Left( uint64_t a64, uint64_t a0, unsigned int count )\r
-{\r
-    struct uint128 z;\r
-\r
-    z.v64 = a64<<count | a0>>( ( - count ) & 63 );\r
-    z.v0 = a0<<count;\r
-    return z;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/s_shortShift128Right.c b/softfloat/SoftFloat-3/source/s_shortShift128Right.c
deleted file mode 100755 (executable)
index f7f4ce8..0000000
--- a/softfloat/SoftFloat-3/source/s_shortShift128Right.c
+++ /dev/null
@@ -1,16 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-\r
-struct uint128\r
- softfloat_shortShift128Right( uint64_t a64, uint64_t a0, unsigned int count )\r
-{\r
-    struct uint128 z;\r
-\r
-    z.v64 = a64>>count;\r
-    z.v0 = a64<<( ( - count ) & 63 ) | a0>>count;\r
-    return z;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/s_shortShift192Left.c b/softfloat/SoftFloat-3/source/s_shortShift192Left.c
deleted file mode 100755 (executable)
index cf1e55d..0000000
--- a/softfloat/SoftFloat-3/source/s_shortShift192Left.c
+++ /dev/null
@@ -1,20 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-\r
-struct uint192\r
- softfloat_shortShift192Left(\r
-     uint64_t a128, uint64_t a64, uint64_t a0, unsigned int count )\r
-{\r
-    unsigned int negCount;\r
-    struct uint192 z;\r
-\r
-    negCount = - count;\r
-    z.v128 = a128<<count | a64>>( negCount & 63 );\r
-    z.v64 = a64<<count | a0>>( negCount & 63 );\r
-    z.v0 = a0<<count;\r
-    return z;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/s_shortShift32Right1Jam.c b/softfloat/SoftFloat-3/source/s_shortShift32Right1Jam.c
deleted file mode 100755 (executable)
index db4c304..0000000
--- a/softfloat/SoftFloat-3/source/s_shortShift32Right1Jam.c
+++ /dev/null
@@ -1,12 +0,0 @@
-
-#include <stdint.h>
-#include "platform.h"
-#include "primitives.h"
-
-uint32_t softfloat_shortShift32Right1Jam( uint32_t a )
-{
-
-    return a>>1 | ( a & 1 );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/s_shortShift64ExtraRightJam.c b/softfloat/SoftFloat-3/source/s_shortShift64ExtraRightJam.c
deleted file mode 100755 (executable)
index b861c67..0000000
--- a/softfloat/SoftFloat-3/source/s_shortShift64ExtraRightJam.c
+++ /dev/null
@@ -1,17 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-\r
-struct uint64_extra\r
- softfloat_shortShift64ExtraRightJam(\r
-     uint64_t a, uint64_t extra, unsigned int count )\r
-{\r
-    struct uint64_extra z;\r
-\r
-    z.v = a>>count;\r
-    z.extra = a<<( ( - count ) & 63 ) | ( extra != 0 );\r
-    return z;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/s_shortShift64RightJam.c b/softfloat/SoftFloat-3/source/s_shortShift64RightJam.c
deleted file mode 100755 (executable)
index 0da6c93..0000000
--- a/softfloat/SoftFloat-3/source/s_shortShift64RightJam.c
+++ /dev/null
@@ -1,12 +0,0 @@
-
-#include <stdint.h>
-#include "platform.h"
-#include "primitives.h"
-
-uint64_t softfloat_shortShift64RightJam( uint64_t a, unsigned int count )
-{
-
-    return a>>count | ( ( a & ( ( (uint64_t) 1<<count ) - 1 ) ) != 0 );
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/s_sub128.c b/softfloat/SoftFloat-3/source/s_sub128.c
deleted file mode 100755 (executable)
index 0c4f181..0000000
--- a/softfloat/SoftFloat-3/source/s_sub128.c
+++ /dev/null
@@ -1,17 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-\r
-struct uint128\r
- softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )\r
-{\r
-    struct uint128 z;\r
-\r
-    z.v0 = a0 - b0;\r
-    z.v64 = a64 - b64;\r
-    z.v64 -= ( a0 < b0 );\r
-    return z;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/s_sub192.c b/softfloat/SoftFloat-3/source/s_sub192.c
deleted file mode 100755 (executable)
index 96f21c9..0000000
--- a/softfloat/SoftFloat-3/source/s_sub192.c
+++ /dev/null
@@ -1,30 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-\r
-struct uint192\r
- softfloat_sub192(\r
-     uint64_t a128,\r
-     uint64_t a64,\r
-     uint64_t a0,\r
-     uint64_t b128,\r
-     uint64_t b64,\r
-     uint64_t b0\r
- )\r
-{\r
-    struct uint192 z;\r
-    unsigned int borrow64, borrow128;\r
-\r
-    z.v0 = a0 - b0;\r
-    borrow64 = ( a0 < b0 );\r
-    z.v64 = a64 - b64;\r
-    borrow128 = ( a64 < b64 );\r
-    z.v128 = a128 - b128;\r
-    borrow128 += ( z.v64 < borrow64 );\r
-    z.v64 -= borrow64;\r
-    z.v128 -= borrow128;\r
-    return z;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/s_subMagsF32.c b/softfloat/SoftFloat-3/source/s_subMagsF32.c
deleted file mode 100755 (executable)
index 0c83b02..0000000
--- a/softfloat/SoftFloat-3/source/s_subMagsF32.c
+++ /dev/null
@@ -1,81 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "primitives.h"
-#include "internals.h"
-#include "specialize.h"
-#include "softfloat.h"
-
-float32_t
- softfloat_subMagsF32( uint_fast32_t uiA, uint_fast32_t uiB, bool signZ )
-{
-    int_fast16_t expA;
-    uint_fast32_t sigA;
-    int_fast16_t expB;
-    uint_fast32_t sigB;
-    int_fast16_t expDiff;
-    uint_fast32_t uiZ;
-    int_fast16_t expZ;
-    uint_fast32_t sigZ;
-    union ui32_f32 uZ;
-
-    expA = expF32UI( uiA );
-    sigA = fracF32UI( uiA );
-    expB = expF32UI( uiB );
-    sigB = fracF32UI( uiB );
-    expDiff = expA - expB;
-    sigA <<= 7;
-    sigB <<= 7;
-    if ( 0 < expDiff ) goto expABigger;
-    if ( expDiff < 0 ) goto expBBigger;
-    if ( expA == 0xFF ) {
-        if ( sigA | sigB ) goto propagateNaN;
-        softfloat_raiseFlags( softfloat_flag_invalid );
-        uiZ = defaultNaNF32UI;
-        goto uiZ;
-    }
-    if ( ! expA ) {
-        expA = 1;
-        expB = 1;
-    }
-    if ( sigB < sigA ) goto aBigger;
-    if ( sigA < sigB ) goto bBigger;
-    uiZ = packToF32UI( softfloat_roundingMode == softfloat_round_min, 0, 0 );
-    goto uiZ;
- expBBigger:
-    if ( expB == 0xFF ) {
-        if ( sigB ) goto propagateNaN;
-        uiZ = packToF32UI( signZ ^ 1, 0xFF, 0 );
-        goto uiZ;
-    }
-    sigA += expA ? 0x40000000 : sigA;
-    sigA = softfloat_shift32RightJam( sigA, - expDiff );
-    sigB |= 0x40000000;
- bBigger:
-    signZ ^= 1;
-    expZ = expB;
-    sigZ = sigB - sigA;
-    goto normRoundPack;
- expABigger:
-    if ( expA == 0xFF ) {
-        if ( sigA ) goto propagateNaN;
-        uiZ = uiA;
-        goto uiZ;
-    }
-    sigB += expB ? 0x40000000 : sigB;
-    sigB = softfloat_shift32RightJam( sigB, expDiff );
-    sigA |= 0x40000000;
- aBigger:
-    expZ = expA;
-    sigZ = sigA - sigB;
- normRoundPack:
-    return softfloat_normRoundPackToF32( signZ, expZ - 1, sigZ );
- propagateNaN:
-    uiZ = softfloat_propagateNaNF32UI( uiA, uiB );
- uiZ:
-    uZ.ui = uiZ;
-    return uZ.f;
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/s_subMagsF64.c b/softfloat/SoftFloat-3/source/s_subMagsF64.c
deleted file mode 100755 (executable)
index 45b81ba..0000000
--- a/softfloat/SoftFloat-3/source/s_subMagsF64.c
+++ /dev/null
@@ -1,81 +0,0 @@
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "platform.h"
-#include "primitives.h"
-#include "internals.h"
-#include "specialize.h"
-#include "softfloat.h"
-
-float64_t
- softfloat_subMagsF64( uint_fast64_t uiA, uint_fast64_t uiB, bool signZ )
-{
-    int_fast16_t expA;
-    uint_fast64_t sigA;
-    int_fast16_t expB;
-    uint_fast64_t sigB;
-    int_fast16_t expDiff;
-    uint_fast64_t uiZ;
-    int_fast16_t expZ;
-    uint_fast64_t sigZ;
-    union ui64_f64 uZ;
-
-    expA = expF64UI( uiA );
-    sigA = fracF64UI( uiA );
-    expB = expF64UI( uiB );
-    sigB = fracF64UI( uiB );
-    expDiff = expA - expB;
-    sigA <<= 10;
-    sigB <<= 10;
-    if ( 0 < expDiff ) goto expABigger;
-    if ( expDiff < 0 ) goto expBBigger;
-    if ( expA == 0x7FF ) {
-        if ( sigA | sigB ) goto propagateNaN;
-        softfloat_raiseFlags( softfloat_flag_invalid );
-        uiZ = defaultNaNF64UI;
-        goto uiZ;
-    }
-    if ( ! expA ) {
-        expA = 1;
-        expB = 1;
-    }
-    if ( sigB < sigA ) goto aBigger;
-    if ( sigA < sigB ) goto bBigger;
-    uiZ = packToF64UI( softfloat_roundingMode == softfloat_round_min, 0, 0 );
-    goto uiZ;
- expBBigger:
-    if ( expB == 0x7FF ) {
-        if ( sigB ) goto propagateNaN;
-        uiZ = packToF64UI( signZ ^ 1, 0x7FF, 0 );
-        goto uiZ;
-    }
-    sigA += expA ? UINT64_C( 0x4000000000000000 ) : sigA;
-    sigA = softfloat_shift64RightJam( sigA, - expDiff );
-    sigB |= UINT64_C( 0x4000000000000000 );
- bBigger:
-    signZ ^= 1;
-    expZ = expB;
-    sigZ = sigB - sigA;
-    goto normRoundPack;
- expABigger:
-    if ( expA == 0x7FF ) {
-        if ( sigA ) goto propagateNaN;
-        uiZ = uiA;
-        goto uiZ;
-    }
-    sigB += expB ? UINT64_C( 0x4000000000000000 ) : sigB;
-    sigB = softfloat_shift64RightJam( sigB, expDiff );
-    sigA |= UINT64_C( 0x4000000000000000 );
- aBigger:
-    expZ = expA;
-    sigZ = sigA - sigB;
- normRoundPack:
-    return softfloat_normRoundPackToF64( signZ, expZ - 1, sigZ );
- propagateNaN:
-    uiZ = softfloat_propagateNaNF64UI( uiA, uiB );
- uiZ:
-    uZ.ui = uiZ;
-    return uZ.f;
-
-}
-

diff --git a/softfloat/SoftFloat-3/source/softfloat.h b/softfloat/SoftFloat-3/source/softfloat.h
deleted file mode 100755 (executable)
index a7ea248..0000000
--- a/softfloat/SoftFloat-3/source/softfloat.h
+++ /dev/null
@@ -1,225 +0,0 @@
-\r
-#ifndef softfloat_h\r
-#define softfloat_h\r
-\r
-/*** UPDATE COMMENTS. ***/\r
-\r
-/*============================================================================\r
-\r
-This C header file is part of the SoftFloat IEEE Floating-point Arithmetic\r
-Package, Release 2b.\r
-\r
-Written by John R. Hauser.  This work was made possible in part by the\r
-International Computer Science Institute, located at Suite 600, 1947 Center\r
-Street, Berkeley, California 94704.  Funding was partially provided by the\r
-National Science Foundation under grant MIP-9311980.  The original version\r
-of this code was written as part of a project to build a fixed-point vector\r
-processor in collaboration with the University of California at Berkeley,\r
-overseen by Profs. Nelson Morgan and John Wawrzynek.  More information\r
-is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
-arithmetic/SoftFloat.html'.\r
-\r
-THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has\r
-been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
-RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
-AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
-COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
-EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
-INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
-OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
-\r
-Derivative works are acceptable, even for commercial purposes, so long as\r
-(1) the source code for the derivative work includes prominent notice that\r
-the work is derivative, and (2) the source code includes prominent notice with\r
-these four paragraphs for those parts of this code that are retained.\r
-\r
-=============================================================================*/\r
-\r
-#include "softfloat_types.h"\r
-\r
-/*----------------------------------------------------------------------------\r
-| Software floating-point underflow tininess-detection mode.\r
-*----------------------------------------------------------------------------*/\r
-extern int_fast8_t softfloat_detectTininess;\r
-enum {\r
-    softfloat_tininess_beforeRounding = 0,\r
-    softfloat_tininess_afterRounding  = 1\r
-};\r
-\r
-/*----------------------------------------------------------------------------\r
-| Software floating-point rounding mode.\r
-*----------------------------------------------------------------------------*/\r
-extern int_fast8_t softfloat_roundingMode;\r
-enum {\r
-    softfloat_round_nearest_even   = 0,\r
-    softfloat_round_minMag         = 1,\r
-    softfloat_round_min            = 2,\r
-    softfloat_round_max            = 3,\r
-    softfloat_round_nearest_maxMag = 4\r
-};\r
-\r
-/*----------------------------------------------------------------------------\r
-| Software floating-point exception flags.\r
-*----------------------------------------------------------------------------*/\r
-extern int_fast8_t softfloat_exceptionFlags;\r
-enum {\r
-    softfloat_flag_inexact   =  1,\r
-    softfloat_flag_underflow =  2,\r
-    softfloat_flag_overflow  =  4,\r
-    softfloat_flag_infinity  =  8,\r
-    softfloat_flag_invalid   = 16\r
-};\r
-\r
-/*----------------------------------------------------------------------------\r
-| Routine to raise any or all of the software floating-point exception flags.\r
-*----------------------------------------------------------------------------*/\r
-void softfloat_raiseFlags( int_fast8_t );\r
-\r
-/*----------------------------------------------------------------------------\r
-| Integer-to-floating-point conversion routines.\r
-*----------------------------------------------------------------------------*/\r
-float32_t ui32_to_f32( uint_fast32_t );\r
-float64_t ui32_to_f64( uint_fast32_t );\r
-floatx80_t ui32_to_fx80( uint_fast32_t );\r
-float128_t ui32_to_f128( uint_fast32_t );\r
-float32_t ui64_to_f32( uint_fast64_t );\r
-float64_t ui64_to_f64( uint_fast64_t );\r
-floatx80_t ui64_to_fx80( uint_fast64_t );\r
-float128_t ui64_to_f128( uint_fast64_t );\r
-float32_t i32_to_f32( int_fast32_t );\r
-float64_t i32_to_f64( int_fast32_t );\r
-floatx80_t i32_to_fx80( int_fast32_t );\r
-float128_t i32_to_f128( int_fast32_t );\r
-float32_t i64_to_f32( int_fast64_t );\r
-float64_t i64_to_f64( int_fast64_t );\r
-floatx80_t i64_to_fx80( int_fast64_t );\r
-float128_t i64_to_f128( int_fast64_t );\r
-\r
-/*----------------------------------------------------------------------------\r
-| 32-bit (single-precision) floating-point operations.\r
-*----------------------------------------------------------------------------*/\r
-uint_fast32_t f32_to_ui32( float32_t, int_fast8_t, bool );\r
-uint_fast64_t f32_to_ui64( float32_t, int_fast8_t, bool );\r
-int_fast32_t f32_to_i32( float32_t, int_fast8_t, bool );\r
-int_fast64_t f32_to_i64( float32_t, int_fast8_t, bool );\r
-uint_fast32_t f32_to_ui32_r_minMag( float32_t, bool );\r
-uint_fast64_t f32_to_ui64_r_minMag( float32_t, bool );\r
-int_fast32_t f32_to_i32_r_minMag( float32_t, bool );\r
-int_fast64_t f32_to_i64_r_minMag( float32_t, bool );\r
-float64_t f32_to_f64( float32_t );\r
-floatx80_t f32_to_fx80( float32_t );\r
-float128_t f32_to_f128( float32_t );\r
-float32_t f32_roundToInt( float32_t, int_fast8_t, bool );\r
-float32_t f32_add( float32_t, float32_t );\r
-float32_t f32_sub( float32_t, float32_t );\r
-float32_t f32_mul( float32_t, float32_t );\r
-float32_t f32_mulAdd( float32_t, float32_t, float32_t );\r
-float32_t f32_div( float32_t, float32_t );\r
-float32_t f32_rem( float32_t, float32_t );\r
-float32_t f32_sqrt( float32_t );\r
-bool f32_eq( float32_t, float32_t );\r
-bool f32_le( float32_t, float32_t );\r
-bool f32_lt( float32_t, float32_t );\r
-bool f32_eq_signaling( float32_t, float32_t );\r
-bool f32_le_quiet( float32_t, float32_t );\r
-bool f32_lt_quiet( float32_t, float32_t );\r
-bool f32_isSignalingNaN( float32_t );\r
-\r
-/*----------------------------------------------------------------------------\r
-| 64-bit (double-precision) floating-point operations.\r
-*----------------------------------------------------------------------------*/\r
-uint_fast32_t f64_to_ui32( float64_t, int_fast8_t, bool );\r
-uint_fast64_t f64_to_ui64( float64_t, int_fast8_t, bool );\r
-int_fast32_t f64_to_i32( float64_t, int_fast8_t, bool );\r
-int_fast64_t f64_to_i64( float64_t, int_fast8_t, bool );\r
-uint_fast32_t f64_to_ui32_r_minMag( float64_t, bool );\r
-uint_fast64_t f64_to_ui64_r_minMag( float64_t, bool );\r
-int_fast32_t f64_to_i32_r_minMag( float64_t, bool );\r
-int_fast64_t f64_to_i64_r_minMag( float64_t, bool );\r
-float32_t f64_to_f32( float64_t );\r
-floatx80_t f64_to_fx80( float64_t );\r
-float128_t f64_to_f128( float64_t );\r
-float64_t f64_roundToInt( float64_t, int_fast8_t, bool );\r
-float64_t f64_add( float64_t, float64_t );\r
-float64_t f64_sub( float64_t, float64_t );\r
-float64_t f64_mul( float64_t, float64_t );\r
-float64_t f64_mulAdd( float64_t, float64_t, float64_t );\r
-float64_t f64_div( float64_t, float64_t );\r
-float64_t f64_rem( float64_t, float64_t );\r
-float64_t f64_sqrt( float64_t );\r
-bool f64_eq( float64_t, float64_t );\r
-bool f64_le( float64_t, float64_t );\r
-bool f64_lt( float64_t, float64_t );\r
-bool f64_eq_signaling( float64_t, float64_t );\r
-bool f64_le_quiet( float64_t, float64_t );\r
-bool f64_lt_quiet( float64_t, float64_t );\r
-bool f64_isSignalingNaN( float64_t );\r
-\r
-/*----------------------------------------------------------------------------\r
-| Extended double-precision rounding precision.  Valid values are 32, 64, and\r
-| 80.\r
-*----------------------------------------------------------------------------*/\r
-extern int_fast8_t floatx80_roundingPrecision;\r
-\r
-/*----------------------------------------------------------------------------\r
-| Extended double-precision floating-point operations.\r
-*----------------------------------------------------------------------------*/\r
-uint_fast32_t fx80_to_ui32( floatx80_t, int_fast8_t, bool );\r
-uint_fast64_t fx80_to_ui64( floatx80_t, int_fast8_t, bool );\r
-int_fast32_t fx80_to_i32( floatx80_t, int_fast8_t, bool );\r
-int_fast64_t fx80_to_i64( floatx80_t, int_fast8_t, bool );\r
-uint_fast32_t fx80_to_ui32_r_minMag( floatx80_t, bool );\r
-uint_fast64_t fx80_to_ui64_r_minMag( floatx80_t, bool );\r
-int_fast32_t fx80_to_i32_r_minMag( floatx80_t, bool );\r
-int_fast64_t fx80_to_i64_r_minMag( floatx80_t, bool );\r
-float32_t fx80_to_f32( floatx80_t );\r
-float64_t fx80_to_f64( floatx80_t );\r
-float128_t fx80_to_f128( floatx80_t );\r
-floatx80_t fx80_roundToInt( floatx80_t, int_fast8_t, bool );\r
-floatx80_t fx80_add( floatx80_t, floatx80_t );\r
-floatx80_t fx80_sub( floatx80_t, floatx80_t );\r
-floatx80_t fx80_mul( floatx80_t, floatx80_t );\r
-floatx80_t fx80_mulAdd( floatx80_t, floatx80_t, floatx80_t );\r
-floatx80_t fx80_div( floatx80_t, floatx80_t );\r
-floatx80_t fx80_rem( floatx80_t, floatx80_t );\r
-floatx80_t fx80_sqrt( floatx80_t );\r
-bool fx80_eq( floatx80_t, floatx80_t );\r
-bool fx80_le( floatx80_t, floatx80_t );\r
-bool fx80_lt( floatx80_t, floatx80_t );\r
-bool fx80_eq_signaling( floatx80_t, floatx80_t );\r
-bool fx80_le_quiet( floatx80_t, floatx80_t );\r
-bool fx80_lt_quiet( floatx80_t, floatx80_t );\r
-bool fx80_isSignalingNaN( floatx80_t );\r
-\r
-/*----------------------------------------------------------------------------\r
-| 128-bit (quadruple-precision) floating-point operations.\r
-*----------------------------------------------------------------------------*/\r
-uint_fast32_t f128_to_ui32( float128_t, int_fast8_t, bool );\r
-uint_fast64_t f128_to_ui64( float128_t, int_fast8_t, bool );\r
-int_fast32_t f128_to_i32( float128_t, int_fast8_t, bool );\r
-int_fast64_t f128_to_i64( float128_t, int_fast8_t, bool );\r
-uint_fast32_t f128_to_ui32_r_minMag( float128_t, bool );\r
-uint_fast64_t f128_to_ui64_r_minMag( float128_t, bool );\r
-int_fast32_t f128_to_i32_r_minMag( float128_t, bool );\r
-int_fast64_t f128_to_i64_r_minMag( float128_t, bool );\r
-float32_t f128_to_f32( float128_t );\r
-float64_t f128_to_f64( float128_t );\r
-floatx80_t f128_to_fx80( float128_t );\r
-float128_t f128_roundToInt( float128_t, int_fast8_t, bool );\r
-float128_t f128_add( float128_t, float128_t );\r
-float128_t f128_sub( float128_t, float128_t );\r
-float128_t f128_mul( float128_t, float128_t );\r
-float128_t f128_mulAdd( float128_t, float128_t, float128_t );\r
-float128_t f128_div( float128_t, float128_t );\r
-float128_t f128_rem( float128_t, float128_t );\r
-float128_t f128_sqrt( float128_t );\r
-bool f128_eq( float128_t, float128_t );\r
-bool f128_le( float128_t, float128_t );\r
-bool f128_lt( float128_t, float128_t );\r
-bool f128_eq_signaling( float128_t, float128_t );\r
-bool f128_le_quiet( float128_t, float128_t );\r
-bool f128_lt_quiet( float128_t, float128_t );\r
-bool f128_isSignalingNaN( float128_t );\r
-\r
-#endif\r
-\r

diff --git a/softfloat/SoftFloat-3/source/softfloat_state.c b/softfloat/SoftFloat-3/source/softfloat_state.c
deleted file mode 100755 (executable)
index 8859089..0000000
--- a/softfloat/SoftFloat-3/source/softfloat_state.c
+++ /dev/null
@@ -1,19 +0,0 @@
-\r
-/*** COMMENTS. ***/\r
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "internals.h"\r
-#include "specialize.h"\r
-#include "softfloat.h"\r
-\r
-/*----------------------------------------------------------------------------\r
-| Floating-point rounding mode, extended double-precision rounding precision,\r
-| and exception flags.\r
-*----------------------------------------------------------------------------*/\r
-int_fast8_t softfloat_roundingMode = softfloat_round_nearest_even;\r
-int_fast8_t softfloat_detectTininess = init_detectTininess;\r
-int_fast8_t softfloat_exceptionFlags = 0;\r
-\r
-int_fast8_t floatx80_roundingPrecision = 80;\r
-\r

diff --git a/softfloat/SoftFloat-3/source/ui32_to_f32.c b/softfloat/SoftFloat-3/source/ui32_to_f32.c
deleted file mode 100755 (executable)
index ba0fc1a..0000000
--- a/softfloat/SoftFloat-3/source/ui32_to_f32.c
+++ /dev/null
@@ -1,25 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-float32_t ui32_to_f32( uint_fast32_t a )\r
-{\r
-    union ui32_f32 uZ;\r
-\r
-    if ( ! a ) {\r
-        uZ.ui = 0;\r
-        return uZ.f;\r
-    }\r
-    if ( a & 0x80000000 ) {\r
-        return\r
-            softfloat_roundPackToF32(\r
-                0, 0x9D, softfloat_shortShift32Right1Jam( a ) );\r
-    } else {\r
-        return softfloat_normRoundPackToF32( 0, 0x9C, a );\r
-    }\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/ui32_to_f64.c b/softfloat/SoftFloat-3/source/ui32_to_f64.c
deleted file mode 100755 (executable)
index d0bd177..0000000
--- a/softfloat/SoftFloat-3/source/ui32_to_f64.c
+++ /dev/null
@@ -1,26 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-float64_t ui32_to_f64( uint_fast32_t a )\r
-{\r
-    uint_fast64_t uiZ;\r
-    int shiftCount;\r
-    union ui64_f64 uZ;\r
-\r
-    if ( ! a ) {\r
-        uiZ = 0;\r
-    } else {\r
-        shiftCount = softfloat_countLeadingZeros32( a ) + 21;\r
-        uiZ =\r
-            packToF64UI(\r
-                0, 0x432 - shiftCount, (uint_fast64_t) a<<shiftCount );\r
-    }\r
-    uZ.ui = uiZ;\r
-    return uZ.f;\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/ui64_to_f32.c b/softfloat/SoftFloat-3/source/ui64_to_f32.c
deleted file mode 100755 (executable)
index 82afbdc..0000000
--- a/softfloat/SoftFloat-3/source/ui64_to_f32.c
+++ /dev/null
@@ -1,31 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-float32_t ui64_to_f32( uint_fast64_t a )\r
-{\r
-    int shiftCount;\r
-    union ui32_f32 u;\r
-    uint_fast32_t sig;\r
-\r
-    shiftCount = softfloat_countLeadingZeros64( a ) - 40;\r
-    if ( 0 <= shiftCount ) {\r
-        u.ui =\r
-            a ? packToF32UI(\r
-                    0, 0x95 - shiftCount, (uint_fast32_t) a<<shiftCount )\r
-                : 0;\r
-        return u.f;\r
-    } else {\r
-        shiftCount += 7;\r
-        sig =\r
-            ( shiftCount < 0 )\r
-                ? softfloat_shortShift64RightJam( a, - shiftCount )\r
-                : (uint_fast32_t) a<<shiftCount;\r
-        return softfloat_roundPackToF32( 0, 0x9C - shiftCount, sig );\r
-    }\r
-\r
-}\r
-\r

diff --git a/softfloat/SoftFloat-3/source/ui64_to_f64.c b/softfloat/SoftFloat-3/source/ui64_to_f64.c
deleted file mode 100755 (executable)
index 52c158b..0000000
--- a/softfloat/SoftFloat-3/source/ui64_to_f64.c
+++ /dev/null
@@ -1,25 +0,0 @@
-\r
-#include <stdint.h>\r
-#include "platform.h"\r
-#include "primitives.h"\r
-#include "internals.h"\r
-#include "softfloat.h"\r
-\r
-float64_t ui64_to_f64( uint_fast64_t a )\r
-{\r
-    union ui64_f64 uZ;\r
-\r
-    if ( ! a ) {\r
-        uZ.ui = 0;\r
-        return uZ.f;\r
-    }\r
-    if ( a & UINT64_C( 0x8000000000000000 ) ) {\r
-        return\r
-            softfloat_roundPackToF64(\r
-                0, 0x43D, softfloat_shortShift64RightJam( a, 1 ) );\r
-    } else {\r
-        return softfloat_normRoundPackToF64( 0, 0x43C, a );\r
-    }\r
-\r
-}\r
-\r

diff --git a/softfloat/f32_add.cc b/softfloat/f32_add.cc
new file mode 100755 (executable)
index 0000000..dc53d68
--- /dev/null
+++ b/softfloat/f32_add.cc
@@ -0,0 +1,29 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float32_t f32_add( float32_t a, float32_t b )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    bool signA;
+    union ui32_f32 uB;
+    uint_fast32_t uiB;
+    bool signB;
+    float32_t ( *magsRoutine )( uint_fast32_t, uint_fast32_t, bool );
+
+    uA.f = a;
+    uiA = uA.ui;
+    signA = signF32UI( uiA );
+    uB.f = b;
+    uiB = uB.ui;
+    signB = signF32UI( uiB );
+    magsRoutine =
+        ( signA == signB ) ? softfloat_addMagsF32 : softfloat_subMagsF32;
+    return magsRoutine( uiA, uiB, signA );
+
+}
+

diff --git a/softfloat/f32_div.cc b/softfloat/f32_div.cc
new file mode 100755 (executable)
index 0000000..958b140
--- /dev/null
+++ b/softfloat/f32_div.cc
@@ -0,0 +1,96 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float32_t f32_div( float32_t a, float32_t b )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    bool signA;
+    int_fast16_t expA;
+    uint_fast32_t sigA;
+    union ui32_f32 uB;
+    uint_fast32_t uiB;
+    bool signB;
+    int_fast16_t expB;
+    uint_fast32_t sigB;
+    bool signZ;
+    struct exp16_sig32 normExpSig;
+    int_fast16_t expZ;
+    uint_fast32_t sigZ;
+    uint_fast32_t uiZ;
+    union ui32_f32 uZ;
+
+    uA.f = a;
+    uiA = uA.ui;
+    signA = signF32UI( uiA );
+    expA = expF32UI( uiA );
+    sigA = fracF32UI( uiA );
+    uB.f = b;
+    uiB = uB.ui;
+    signB = signF32UI( uiB );
+    expB = expF32UI( uiB );
+    sigB = fracF32UI( uiB );
+    signZ = signA ^ signB;
+    if ( expA == 0xFF ) {
+        if ( sigA ) goto propagateNaN;
+        if ( expB == 0xFF ) {
+            if ( sigB ) goto propagateNaN;
+            goto invalid;
+        }
+        goto infinity;
+    }
+    if ( expB == 0xFF ) {
+        if ( sigB ) goto propagateNaN;
+        goto zero;
+    }
+    if ( ! expB ) {
+        if ( ! sigB ) {
+            if ( ! ( expA | sigA ) ) goto invalid;
+            softfloat_raiseFlags( softfloat_flag_infinity );
+            goto infinity;
+        }
+        normExpSig = softfloat_normSubnormalF32Sig( sigB );
+        expB = normExpSig.exp;
+        sigB = normExpSig.sig;
+    }
+    if ( ! expA ) {
+        if ( ! sigA ) goto zero;
+        normExpSig = softfloat_normSubnormalF32Sig( sigA );
+        expA = normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    expZ = expA - expB + 0x7D;
+    sigA = ( sigA | 0x00800000 )<<7;
+    sigB = ( sigB | 0x00800000 )<<8;
+    if ( sigB <= ( sigA + sigA ) ) {
+        ++expZ;
+        sigA >>= 1;
+    }
+    sigZ = ( (uint_fast64_t) sigA<<32 ) / sigB;
+    if ( ! ( sigZ & 0x3F ) ) {
+        sigZ |= ( (uint_fast64_t) sigB * sigZ != (uint_fast64_t) sigA<<32 );
+    }
+    return softfloat_roundPackToF32( signZ, expZ, sigZ );
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF32UI( uiA, uiB );
+    goto uiZ;
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    uiZ = defaultNaNF32UI;
+    goto uiZ;
+ infinity:
+    uiZ = packToF32UI( signZ, 0xFF, 0 );
+    goto uiZ;
+ zero:
+    uiZ = packToF32UI( signZ, 0, 0 );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+

diff --git a/softfloat/f32_eq.cc b/softfloat/f32_eq.cc
new file mode 100755 (executable)
index 0000000..8f2306b
--- /dev/null
+++ b/softfloat/f32_eq.cc
@@ -0,0 +1,34 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool f32_eq( float32_t a, float32_t b )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    union ui32_f32 uB;
+    uint_fast32_t uiB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if (
+           ( ( expF32UI( uiA ) == 0xFF ) && fracF32UI( uiA ) )
+        || ( ( expF32UI( uiB ) == 0xFF ) && fracF32UI( uiB ) )
+    ) {
+        if (
+            softfloat_isSigNaNF32UI( uiA ) || softfloat_isSigNaNF32UI( uiB )
+        ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    return ( uiA == uiB ) || ! (uint32_t) ( ( uiA | uiB )<<1 );
+
+}
+

diff --git a/softfloat/f32_eq_signaling.cc b/softfloat/f32_eq_signaling.cc
new file mode 100755 (executable)
index 0000000..bfba48a
--- /dev/null
+++ b/softfloat/f32_eq_signaling.cc
@@ -0,0 +1,29 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+bool f32_eq_signaling( float32_t a, float32_t b )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    union ui32_f32 uB;
+    uint_fast32_t uiB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if (
+           ( ( expF32UI( uiA ) == 0xFF ) && fracF32UI( uiA ) )
+        || ( ( expF32UI( uiB ) == 0xFF ) && fracF32UI( uiB ) )
+    ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    return ( uiA == uiB ) || ! (uint32_t) ( ( uiA | uiB )<<1 );
+
+}
+

diff --git a/softfloat/f32_isSignalingNaN.cc b/softfloat/f32_isSignalingNaN.cc
new file mode 100755 (executable)
index 0000000..09aaa82
--- /dev/null
+++ b/softfloat/f32_isSignalingNaN.cc
@@ -0,0 +1,16 @@
+
+#include <stdbool.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool f32_isSignalingNaN( float32_t a )
+{
+    union ui32_f32 uA;
+
+    uA.f = a;
+    return softfloat_isSigNaNF32UI( uA.ui );
+
+}
+

diff --git a/softfloat/f32_le.cc b/softfloat/f32_le.cc
new file mode 100755 (executable)
index 0000000..5f47be5
--- /dev/null
+++ b/softfloat/f32_le.cc
@@ -0,0 +1,34 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+bool f32_le( float32_t a, float32_t b )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    union ui32_f32 uB;
+    uint_fast32_t uiB;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if (
+           ( ( expF32UI( uiA ) == 0xFF ) && fracF32UI( uiA ) )
+        || ( ( expF32UI( uiB ) == 0xFF ) && fracF32UI( uiB ) )
+    ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    signA = signF32UI( uiA );
+    signB = signF32UI( uiB );
+    return
+        ( signA != signB ) ? signA || ! (uint32_t) ( ( uiA | uiB )<<1 )
+            : ( uiA == uiB ) || ( signA ^ ( uiA < uiB ) );
+
+}
+

diff --git a/softfloat/f32_le_quiet.cc b/softfloat/f32_le_quiet.cc
new file mode 100755 (executable)
index 0000000..2b541da
--- /dev/null
+++ b/softfloat/f32_le_quiet.cc
@@ -0,0 +1,39 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool f32_le_quiet( float32_t a, float32_t b )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    union ui32_f32 uB;
+    uint_fast32_t uiB;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if (
+           ( ( expF32UI( uiA ) == 0xFF ) && fracF32UI( uiA ) )
+        || ( ( expF32UI( uiB ) == 0xFF ) && fracF32UI( uiB ) )
+    ) {
+        if (
+            softfloat_isSigNaNF32UI( uiA ) || softfloat_isSigNaNF32UI( uiB )
+        ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    signA = signF32UI( uiA );
+    signB = signF32UI( uiB );
+    return
+        ( signA != signB ) ? signA || ! (uint32_t) ( ( uiA | uiB )<<1 )
+            : ( uiA == uiB ) || ( signA ^ ( uiA < uiB ) );
+
+}
+

diff --git a/softfloat/f32_lt.cc b/softfloat/f32_lt.cc
new file mode 100755 (executable)
index 0000000..753b28a
--- /dev/null
+++ b/softfloat/f32_lt.cc
@@ -0,0 +1,34 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+bool f32_lt( float32_t a, float32_t b )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    union ui32_f32 uB;
+    uint_fast32_t uiB;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if (
+           ( ( expF32UI( uiA ) == 0xFF ) && fracF32UI( uiA ) )
+        || ( ( expF32UI( uiB ) == 0xFF ) && fracF32UI( uiB ) )
+    ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    signA = signF32UI( uiA );
+    signB = signF32UI( uiB );
+    return
+        ( signA != signB ) ? signA && ( (uint32_t) ( ( uiA | uiB )<<1 ) != 0 )
+            : ( uiA != uiB ) && ( signA ^ ( uiA < uiB ) );
+
+}
+

diff --git a/softfloat/f32_lt_quiet.cc b/softfloat/f32_lt_quiet.cc
new file mode 100755 (executable)
index 0000000..ecd90bf
--- /dev/null
+++ b/softfloat/f32_lt_quiet.cc
@@ -0,0 +1,39 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool f32_lt_quiet( float32_t a, float32_t b )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    union ui32_f32 uB;
+    uint_fast32_t uiB;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if (
+           ( ( expF32UI( uiA ) == 0xFF ) && fracF32UI( uiA ) )
+        || ( ( expF32UI( uiB ) == 0xFF ) && fracF32UI( uiB ) )
+    ) {
+        if (
+            softfloat_isSigNaNF32UI( uiA ) || softfloat_isSigNaNF32UI( uiB )
+        ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    signA = signF32UI( uiA );
+    signB = signF32UI( uiB );
+    return
+        ( signA != signB ) ? signA && ( (uint32_t) ( ( uiA | uiB )<<1 ) != 0 )
+            : ( uiA != uiB ) && ( signA ^ ( uiA < uiB ) );
+
+}
+

diff --git a/softfloat/f32_mul.cc b/softfloat/f32_mul.cc
new file mode 100755 (executable)
index 0000000..d49c1dd
--- /dev/null
+++ b/softfloat/f32_mul.cc
@@ -0,0 +1,89 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+#include "specialize.h"\r
+#include "softfloat.h"\r
+\r
+float32_t f32_mul( float32_t a, float32_t b )\r
+{\r
+    union ui32_f32 uA;\r
+    uint_fast32_t uiA;\r
+    bool signA;\r
+    int_fast16_t expA;\r
+    uint_fast32_t sigA;\r
+    union ui32_f32 uB;\r
+    uint_fast32_t uiB;\r
+    bool signB;\r
+    int_fast16_t expB;\r
+    uint_fast32_t sigB;\r
+    bool signZ;\r
+    uint_fast32_t magBits;\r
+    struct exp16_sig32 normExpSig;\r
+    int_fast16_t expZ;\r
+    uint_fast32_t sigZ, uiZ;\r
+    union ui32_f32 uZ;\r
+\r
+    uA.f = a;\r
+    uiA = uA.ui;\r
+    signA = signF32UI( uiA );\r
+    expA = expF32UI( uiA );\r
+    sigA = fracF32UI( uiA );\r
+    uB.f = b;\r
+    uiB = uB.ui;\r
+    signB = signF32UI( uiB );\r
+    expB = expF32UI( uiB );\r
+    sigB = fracF32UI( uiB );\r
+    signZ = signA ^ signB;\r
+    if ( expA == 0xFF ) {\r
+        if ( sigA || ( ( expB == 0xFF ) && sigB ) ) goto propagateNaN;\r
+        magBits = expB | sigB;\r
+        goto infArg;\r
+    }\r
+    if ( expB == 0xFF ) {\r
+        if ( sigB ) goto propagateNaN;\r
+        magBits = expA | sigA;\r
+        goto infArg;\r
+    }\r
+    if ( ! expA ) {\r
+        if ( ! sigA ) goto zero;\r
+        normExpSig = softfloat_normSubnormalF32Sig( sigA );\r
+        expA = normExpSig.exp;\r
+        sigA = normExpSig.sig;\r
+    }\r
+    if ( ! expB ) {\r
+        if ( ! sigB ) goto zero;\r
+        normExpSig = softfloat_normSubnormalF32Sig( sigB );\r
+        expB = normExpSig.exp;\r
+        sigB = normExpSig.sig;\r
+    }\r
+    expZ = expA + expB - 0x7F;\r
+    sigA = ( sigA | 0x00800000 )<<7;\r
+    sigB = ( sigB | 0x00800000 )<<8;\r
+    sigZ = softfloat_shortShift64RightJam( (uint_fast64_t) sigA * sigB, 32 );\r
+    if ( sigZ < 0x40000000 ) {\r
+        --expZ;\r
+        sigZ <<= 1;\r
+    }\r
+    return softfloat_roundPackToF32( signZ, expZ, sigZ );\r
+ propagateNaN:\r
+    uiZ = softfloat_propagateNaNF32UI( uiA, uiB );\r
+    goto uiZ;\r
+ infArg:\r
+    if ( ! magBits ) {\r
+        softfloat_raiseFlags( softfloat_flag_invalid );\r
+        uiZ = defaultNaNF32UI;\r
+    } else {\r
+        uiZ = packToF32UI( signZ, 0xFF, 0 );\r
+    }\r
+    goto uiZ;\r
+ zero:\r
+    uiZ = packToF32UI( signZ, 0, 0 );\r
+ uiZ:\r
+    uZ.ui = uiZ;\r
+    return uZ.f;\r
+\r
+}\r
+\r

diff --git a/softfloat/f32_mulAdd.cc b/softfloat/f32_mulAdd.cc
new file mode 100755 (executable)
index 0000000..3d4cee9
--- /dev/null
+++ b/softfloat/f32_mulAdd.cc
@@ -0,0 +1,25 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+float32_t f32_mulAdd( float32_t a, float32_t b, float32_t c )\r
+{\r
+    union ui32_f32 uA;\r
+    uint_fast32_t uiA;\r
+    union ui32_f32 uB;\r
+    uint_fast32_t uiB;\r
+    union ui32_f32 uC;\r
+    uint_fast32_t uiC;\r
+\r
+    uA.f = a;\r
+    uiA = uA.ui;\r
+    uB.f = b;\r
+    uiB = uB.ui;\r
+    uC.f = c;\r
+    uiC = uC.ui;\r
+    return softfloat_mulAddF32( 0, uiA, uiB, uiC );\r
+\r
+}\r
+\r

diff --git a/softfloat/f32_rem.cc b/softfloat/f32_rem.cc
new file mode 100755 (executable)
index 0000000..d29b840
--- /dev/null
+++ b/softfloat/f32_rem.cc
@@ -0,0 +1,124 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float32_t f32_rem( float32_t a, float32_t b )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    bool signA;
+    int_fast16_t expA;
+    uint_fast32_t sigA;
+    union ui32_f32 uB;
+    uint_fast32_t uiB;
+    bool signB;
+    int_fast16_t expB;
+    uint_fast32_t sigB;
+    struct exp16_sig32 normExpSig;
+    int_fast16_t expDiff;
+    uint_fast32_t q;
+    uint_fast64_t sigA64, sigB64, q64;
+    uint_fast32_t alternateSigA;
+    uint32_t sigMean;
+    bool signZ;
+    uint_fast32_t uiZ;
+    union ui32_f32 uZ;
+
+    uA.f = a;
+    uiA = uA.ui;
+    signA = signF32UI( uiA );
+    expA = expF32UI( uiA );
+    sigA = fracF32UI( uiA );
+    uB.f = b;
+    uiB = uB.ui;
+    signB = signF32UI( uiB );
+    expB = expF32UI( uiB );
+    sigB = fracF32UI( uiB );
+    if ( expA == 0xFF ) {
+        if ( sigA || ( ( expB == 0xFF ) && sigB ) ) goto propagateNaN;
+        goto invalid;
+    }
+    if ( expB == 0xFF ) {
+        if ( sigB ) goto propagateNaN;
+        return a;
+    }
+    if ( ! expB ) {
+        if ( ! sigB ) goto invalid;
+        normExpSig = softfloat_normSubnormalF32Sig( sigB );
+        expB = normExpSig.exp;
+        sigB = normExpSig.sig;
+    }
+    if ( ! expA ) {
+        if ( ! sigA ) return a;
+        normExpSig = softfloat_normSubnormalF32Sig( sigA );
+        expA = normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    expDiff = expA - expB;
+    sigA |= 0x00800000;
+    sigB |= 0x00800000;
+    if ( expDiff < 32 ) {
+        sigA <<= 8;
+        sigB <<= 8;
+        if ( expDiff < 0 ) {
+            if ( expDiff < -1 ) return a;
+            sigA >>= 1;
+        }
+        q = ( sigB <= sigA );
+        if ( q ) sigA -= sigB;
+        if ( 0 < expDiff ) {
+            q = ( (uint_fast64_t) sigA<<32 ) / sigB;
+            q >>= 32 - expDiff;
+            sigB >>= 2;
+            sigA = ( ( sigA>>1 )<<( expDiff - 1 ) ) - sigB * q;
+        } else {
+            sigA >>= 2;
+            sigB >>= 2;
+        }
+    } else {
+        if ( sigB <= sigA ) sigA -= sigB;
+        sigA64 = (uint_fast64_t) sigA<<40;
+        sigB64 = (uint_fast64_t) sigB<<40;
+        expDiff -= 64;
+        while ( 0 < expDiff ) {
+            q64 = softfloat_estimateDiv128To64( sigA64, 0, sigB64 );
+            q64 = ( 2 < q64 ) ? q64 - 2 : 0;
+            sigA64 = - ( ( sigB * q64 )<<38 );
+            expDiff -= 62;
+        }
+        expDiff += 64;
+        q64 = softfloat_estimateDiv128To64( sigA64, 0, sigB64 );
+        q64 = ( 2 < q64 ) ? q64 - 2 : 0;
+        q = q64>>( 64 - expDiff );
+        sigB <<= 6;
+        sigA = ( ( sigA64>>33 )<<( expDiff - 1 ) ) - sigB * q;
+    }
+    do {
+        alternateSigA = sigA;
+        ++q;
+        sigA -= sigB;
+    } while ( sigA < 0x80000000 );
+    sigMean = sigA + alternateSigA;
+    if ( ( 0x80000000 <= sigMean ) || ( ! sigMean && ( q & 1 ) ) ) {
+        sigA = alternateSigA;
+    }
+    signZ = ( 0x80000000 <= sigA );
+    if ( signZ ) sigA = - sigA;
+    return softfloat_normRoundPackToF32( signA ^ signZ, expB, sigA );
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF32UI( uiA, uiB );
+    goto uiZ;
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    uiZ = defaultNaNF32UI;
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+

diff --git a/softfloat/f32_roundToInt.cc b/softfloat/f32_roundToInt.cc
new file mode 100755 (executable)
index 0000000..f8f9114
--- /dev/null
+++ b/softfloat/f32_roundToInt.cc
@@ -0,0 +1,78 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float32_t f32_roundToInt( float32_t a, int_fast8_t roundingMode, bool exact )
+{
+    union ui32_f32 uA;
+    uint_fast32_t uiA;
+    int_fast16_t expA;
+    uint_fast32_t uiZ;
+    bool signA;
+    uint_fast32_t lastBitMask, roundBitsMask;
+    union ui32_f32 uZ;
+
+    uA.f = a;
+    uiA = uA.ui;
+    expA = expF32UI( uiA );
+    if ( 0x96 <= expA ) {
+        if ( ( expA == 0xFF ) && fracF32UI( uiA ) ) {
+            uiZ = softfloat_propagateNaNF32UI( uiA, 0 );
+            goto uiZ;
+        }
+        return a;
+    }
+    if ( expA <= 0x7E ) {
+        if ( ! (uint32_t) ( uiA<<1 ) ) return a;
+        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+        signA = signF32UI( uiA );
+        switch ( roundingMode ) {
+         case softfloat_round_nearest_even:
+            if ( ( expA == 0x7E ) && fracF32UI( uiA ) ) {
+                uiZ = packToF32UI( signA, 0x7F, 0 );
+                goto uiZ;
+            }
+            break;
+         case softfloat_round_min:
+            uiZ = signA ? 0xBF800000 : 0;
+            goto uiZ;
+         case softfloat_round_max:
+            uiZ = signA ? 0x80000000 : 0x3F800000;
+            goto uiZ;
+         case softfloat_round_nearest_maxMag:
+            if ( expA == 0x7E ) {
+                uiZ = packToF32UI( signA, 0x7F, 0 );
+                goto uiZ;
+            }
+            break;
+        }
+        uiZ = packToF32UI( signA, 0, 0 );
+        goto uiZ;
+    }
+    lastBitMask = (uint_fast32_t) 1<<( 0x96 - expA );
+    roundBitsMask = lastBitMask - 1;
+    uiZ = uiA;
+    if ( roundingMode == softfloat_round_nearest_maxMag ) {
+        uiZ += lastBitMask>>1;
+    } else if ( roundingMode == softfloat_round_nearest_even ) {
+        uiZ += lastBitMask>>1;
+        if ( ! ( uiZ & roundBitsMask ) ) uiZ &= ~ lastBitMask;
+    } else if ( roundingMode != softfloat_round_minMag ) {
+        if ( signF32UI( uiZ ) ^ ( roundingMode == softfloat_round_max ) ) {
+            uiZ += roundBitsMask;
+        }
+    }
+    uiZ &= ~ roundBitsMask;
+    if ( exact && ( uiZ != uiA ) ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+

diff --git a/softfloat/f32_sqrt.cc b/softfloat/f32_sqrt.cc
new file mode 100755 (executable)
index 0000000..c9eb907
--- /dev/null
+++ b/softfloat/f32_sqrt.cc
@@ -0,0 +1,74 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+#include "specialize.h"\r
+#include "softfloat.h"\r
+\r
+float32_t f32_sqrt( float32_t a )\r
+{\r
+    union ui32_f32 uA;\r
+    uint_fast32_t uiA;\r
+    bool signA;\r
+    int_fast16_t expA;\r
+    uint_fast32_t sigA, uiZ;\r
+    struct exp16_sig32 normExpSig;\r
+    int_fast16_t expZ;\r
+    uint_fast32_t sigZ;\r
+    uint_fast64_t term, rem;\r
+    union ui32_f32 uZ;\r
+\r
+    uA.f = a;\r
+    uiA = uA.ui;\r
+    signA = signF32UI( uiA );\r
+    expA = expF32UI( uiA );\r
+    sigA = fracF32UI( uiA );\r
+    if ( expA == 0xFF ) {\r
+        if ( sigA ) {\r
+            uiZ = softfloat_propagateNaNF32UI( uiA, 0 );\r
+            goto uiZ;\r
+        }\r
+        if ( ! signA ) return a;\r
+        goto invalid;\r
+    }\r
+    if ( signA ) {\r
+        if ( ! ( expA | sigA ) ) return a;\r
+        goto invalid;\r
+    }\r
+    if ( ! expA ) {\r
+        if ( ! sigA ) return a;\r
+        normExpSig = softfloat_normSubnormalF32Sig( sigA );\r
+        expA = normExpSig.exp;\r
+        sigA = normExpSig.sig;\r
+    }\r
+    expZ = ( ( expA - 0x7F )>>1 ) + 0x7E;\r
+    sigA = ( sigA | 0x00800000 )<<8;\r
+    sigZ = softfloat_estimateSqrt32( expA, sigA ) + 2;\r
+    if ( ( sigZ & 0x7F ) <= 5 ) {\r
+        if ( sigZ < 2 ) {\r
+            sigZ = 0x7FFFFFFF;\r
+            goto roundPack;\r
+        }\r
+        sigA >>= expA & 1;\r
+        term = (uint_fast64_t) sigZ * sigZ;\r
+        rem = ( (uint_fast64_t) sigA<<32 ) - term;\r
+        while ( UINT64_C( 0x8000000000000000 ) <= rem ) {\r
+            --sigZ;\r
+            rem += ( (uint_fast64_t) sigZ<<1 ) | 1;\r
+        }\r
+        sigZ |= ( rem != 0 );\r
+    }\r
+    sigZ = softfloat_shortShift32Right1Jam( sigZ );\r
+ roundPack:\r
+    return softfloat_roundPackToF32( 0, expZ, sigZ );\r
+ invalid:\r
+    softfloat_raiseFlags( softfloat_flag_invalid );\r
+    uiZ = defaultNaNF32UI;\r
+ uiZ:\r
+    uZ.ui = uiZ;\r
+    return uZ.f;\r
+\r
+}\r
+\r

diff --git a/softfloat/f32_sub.cc b/softfloat/f32_sub.cc
new file mode 100755 (executable)
index 0000000..c64df8e
--- /dev/null
+++ b/softfloat/f32_sub.cc
@@ -0,0 +1,29 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+float32_t f32_sub( float32_t a, float32_t b )\r
+{\r
+    union ui32_f32 uA;\r
+    uint_fast32_t uiA;\r
+    bool signA;\r
+    union ui32_f32 uB;\r
+    uint_fast32_t uiB;\r
+    bool signB;\r
+    float32_t ( *magsRoutine )( uint_fast32_t, uint_fast32_t, bool );\r
+\r
+    uA.f = a;\r
+    uiA = uA.ui;\r
+    signA = signF32UI( uiA );\r
+    uB.f = b;\r
+    uiB = uB.ui;\r
+    signB = signF32UI( uiB );\r
+    magsRoutine =\r
+        ( signA == signB ) ? softfloat_subMagsF32 : softfloat_addMagsF32;\r
+    return magsRoutine( uiA, uiB ^ 0x80000000, signA );\r
+\r
+}\r
+\r

diff --git a/softfloat/f32_to_f64.cc b/softfloat/f32_to_f64.cc
new file mode 100755 (executable)
index 0000000..9f0ae5c
--- /dev/null
+++ b/softfloat/f32_to_f64.cc
@@ -0,0 +1,47 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "internals.h"\r
+#include "specialize.h"\r
+#include "softfloat.h"\r
+\r
+float64_t f32_to_f64( float32_t a )\r
+{\r
+    union ui32_f32 uA;\r
+    uint_fast32_t uiA;\r
+    bool sign;\r
+    int_fast16_t exp;\r
+    uint_fast32_t sig;\r
+    uint_fast64_t uiZ;\r
+    struct exp16_sig32 normExpSig;\r
+    union ui64_f64 uZ;\r
+\r
+    uA.f = a;\r
+    uiA = uA.ui;\r
+    sign = signF32UI( uiA );\r
+    exp = expF32UI( uiA );\r
+    sig = fracF32UI( uiA );\r
+    if ( exp == 0xFF ) {\r
+        uiZ =\r
+            sig ? softfloat_commonNaNToF64UI(\r
+                      softfloat_f32UIToCommonNaN( uiA ) )\r
+                : packToF64UI( sign, 0x7FF, 0 );\r
+        goto uiZ;\r
+    }\r
+    if ( ! exp ) {\r
+        if ( ! sig ) {\r
+            uiZ = packToF64UI( sign, 0, 0 );\r
+            goto uiZ;\r
+        }\r
+        normExpSig = softfloat_normSubnormalF32Sig( sig );\r
+        exp = normExpSig.exp - 1;\r
+        sig = normExpSig.sig;\r
+    }\r
+    uiZ = packToF64UI( sign, exp + 0x380, (uint_fast64_t) sig<<29 );\r
+ uiZ:\r
+    uZ.ui = uiZ;\r
+    return uZ.f;\r
+\r
+}\r
+\r

diff --git a/softfloat/f32_to_i32.cc b/softfloat/f32_to_i32.cc
new file mode 100755 (executable)
index 0000000..bbbaee0
--- /dev/null
+++ b/softfloat/f32_to_i32.cc
@@ -0,0 +1,34 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+int_fast32_t f32_to_i32( float32_t a, int_fast8_t roundingMode, bool exact )\r
+{\r
+    union ui32_f32 uA;\r
+    uint_fast32_t uiA;\r
+    bool sign;\r
+    int_fast16_t exp;\r
+    uint_fast32_t sig;\r
+    uint_fast64_t sig64;\r
+    int_fast16_t shiftCount;\r
+\r
+    uA.f = a;\r
+    uiA = uA.ui;\r
+    sign = signF32UI( uiA );\r
+    exp = expF32UI( uiA );\r
+    sig = fracF32UI( uiA );\r
+    if ( ( exp == 0xFF ) && sig ) sign = 0;\r
+    if ( exp ) sig |= 0x00800000;\r
+    sig64 = (uint_fast64_t) sig<<32;\r
+    shiftCount = 0xAF - exp;\r
+    if ( 0 < shiftCount ) {\r
+        sig64 = softfloat_shift64RightJam( sig64, shiftCount );\r
+    }\r
+    return softfloat_roundPackToI32( sign, sig64, roundingMode, exact );\r
+\r
+}\r
+\r

diff --git a/softfloat/f32_to_i32_r_minMag.cc b/softfloat/f32_to_i32_r_minMag.cc
new file mode 100755 (executable)
index 0000000..63ff1e2
--- /dev/null
+++ b/softfloat/f32_to_i32_r_minMag.cc
@@ -0,0 +1,45 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+int_fast32_t f32_to_i32_r_minMag( float32_t a, bool exact )\r
+{\r
+    union ui32_f32 uA;\r
+    uint_fast32_t uiA;\r
+    int_fast16_t exp;\r
+    uint_fast32_t sig;\r
+    bool sign;\r
+    int_fast16_t shiftCount;\r
+    int_fast32_t absZ;\r
+\r
+    uA.f = a;\r
+    uiA = uA.ui;\r
+    exp = expF32UI( uiA );\r
+    sig = fracF32UI( uiA );\r
+    if ( exp < 0x7F ) {\r
+        if ( exact && ( exp | sig ) ) {\r
+            softfloat_exceptionFlags |= softfloat_flag_inexact;\r
+        }\r
+        return 0;\r
+    }\r
+    sign = signF32UI( uiA );\r
+    shiftCount = 0x9E - exp;\r
+    if ( shiftCount <= 0 ) {\r
+        if ( uiA != packToF32UI( 1, 0x9E, 0 ) ) {\r
+            softfloat_raiseFlags( softfloat_flag_invalid );\r
+            if ( ! sign || ( ( exp == 0xFF ) && sig ) ) return 0x7FFFFFFF;\r
+        }\r
+        return -0x7FFFFFFF - 1;\r
+    }\r
+    sig = ( sig | 0x00800000 )<<8;\r
+    absZ = sig>>shiftCount;\r
+    if ( exact && (uint32_t) ( sig<<( ( - shiftCount ) & 31 ) ) ) {\r
+        softfloat_exceptionFlags |= softfloat_flag_inexact;\r
+    }\r
+    return sign ? - absZ : absZ;\r
+\r
+}\r
+\r

diff --git a/softfloat/f32_to_i64.cc b/softfloat/f32_to_i64.cc
new file mode 100755 (executable)
index 0000000..c0b8981
--- /dev/null
+++ b/softfloat/f32_to_i64.cc
@@ -0,0 +1,44 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+int_fast64_t f32_to_i64( float32_t a, int_fast8_t roundingMode, bool exact )\r
+{\r
+    union ui32_f32 uA;\r
+    uint_fast32_t uiA;\r
+    bool sign;\r
+    int_fast16_t exp;\r
+    uint_fast32_t sig;\r
+    int_fast16_t shiftCount;\r
+    uint_fast64_t sig64, extra;\r
+    struct uint64_extra sig64Extra;\r
+\r
+    uA.f = a;\r
+    uiA = uA.ui;\r
+    sign = signF32UI( uiA );\r
+    exp = expF32UI( uiA );\r
+    sig = fracF32UI( uiA );\r
+    shiftCount = 0xBE - exp;\r
+    if ( shiftCount < 0 ) {\r
+        softfloat_raiseFlags( softfloat_flag_invalid );\r
+        if ( ! sign || ( ( exp == 0xFF ) && sig ) ) {\r
+            return INT64_C( 0x7FFFFFFFFFFFFFFF );\r
+        }\r
+        return - INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1;\r
+    }\r
+    if ( exp ) sig |= 0x00800000;\r
+    sig64 = (uint_fast64_t) sig<<40;\r
+    extra = 0;\r
+    if ( shiftCount ) {\r
+        sig64Extra = softfloat_shift64ExtraRightJam( sig64, 0, shiftCount );\r
+        sig64 = sig64Extra.v;\r
+        extra = sig64Extra.extra;\r
+    }\r
+    return softfloat_roundPackToI64( sign, sig64, extra, roundingMode, exact );\r
+\r
+}\r
+\r

diff --git a/softfloat/f32_to_i64_r_minMag.cc b/softfloat/f32_to_i64_r_minMag.cc
new file mode 100755 (executable)
index 0000000..33bff93
--- /dev/null
+++ b/softfloat/f32_to_i64_r_minMag.cc
@@ -0,0 +1,52 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+int_fast64_t f32_to_i64_r_minMag( float32_t a, bool exact )\r
+{\r
+    union ui32_f32 uA;\r
+    uint_fast32_t uiA;\r
+    int_fast16_t exp;\r
+    uint_fast32_t sig;\r
+    bool sign;\r
+    int_fast16_t shiftCount;\r
+    uint_fast64_t sig64;\r
+    int_fast64_t absZ;\r
+\r
+    uA.f = a;\r
+    uiA = uA.ui;\r
+    exp = expF32UI( uiA );\r
+    sig = fracF32UI( uiA );\r
+    if ( exp < 0x7F ) {\r
+        if ( exact && ( exp | sig ) ) {\r
+            softfloat_exceptionFlags |= softfloat_flag_inexact;\r
+        }\r
+        return 0;\r
+    }\r
+    sign = signF32UI( uiA );\r
+    shiftCount = 0xBE - exp;\r
+    if ( shiftCount <= 0 ) {\r
+        if ( uiA != packToF32UI( 1, 0xBE, 0 ) ) {\r
+            softfloat_raiseFlags( softfloat_flag_invalid );\r
+            if ( ! sign || ( ( exp == 0xFF ) && sig ) ) {\r
+                return INT64_C( 0x7FFFFFFFFFFFFFFF );\r
+            }\r
+        }\r
+        return - INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1;\r
+    }\r
+    sig |= 0x00800000;\r
+    sig64 = (uint_fast64_t) sig<<40;\r
+    absZ = sig64>>shiftCount;\r
+    shiftCount = 40 - shiftCount;\r
+    if (\r
+        exact && ( shiftCount < 0 ) && (uint32_t) ( sig<<( shiftCount & 31 ) )\r
+    ) {\r
+        softfloat_exceptionFlags |= softfloat_flag_inexact;\r
+    }\r
+    return sign ? - absZ : absZ;\r
+\r
+}\r
+\r

diff --git a/softfloat/f32_to_ui32.cc b/softfloat/f32_to_ui32.cc
new file mode 100755 (executable)
index 0000000..3501db8
--- /dev/null
+++ b/softfloat/f32_to_ui32.cc
@@ -0,0 +1,33 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+uint_fast32_t f32_to_ui32( float32_t a, int_fast8_t roundingMode, bool exact )\r
+{\r
+    union ui32_f32 uA;\r
+    uint_fast32_t uiA;\r
+    bool sign;\r
+    int_fast16_t exp;\r
+    uint_fast32_t sig;\r
+    uint_fast64_t sig64;\r
+    int_fast16_t shiftCount;\r
+\r
+    uA.f = a;\r
+    uiA = uA.ui;\r
+    sign = signF32UI( uiA );\r
+    exp = expF32UI( uiA );\r
+    sig = fracF32UI( uiA );\r
+    if ( exp ) sig |= 0x00800000;\r
+    sig64 = (uint_fast64_t) sig<<32;\r
+    shiftCount = 0xAF - exp;\r
+    if ( 0 < shiftCount ) {\r
+        sig64 = softfloat_shift64RightJam( sig64, shiftCount );\r
+    }\r
+    return softfloat_roundPackToUI32( sign, sig64, roundingMode, exact );\r
+\r
+}\r
+\r

diff --git a/softfloat/f32_to_ui32_r_minMag.cc b/softfloat/f32_to_ui32_r_minMag.cc
new file mode 100755 (executable)
index 0000000..edd858d
--- /dev/null
+++ b/softfloat/f32_to_ui32_r_minMag.cc
@@ -0,0 +1,41 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+uint_fast32_t f32_to_ui32_r_minMag( float32_t a, bool exact )\r
+{\r
+    union ui32_f32 uA;\r
+    uint_fast32_t uiA;\r
+    int_fast16_t exp;\r
+    uint_fast32_t sig;\r
+    int_fast16_t shiftCount;\r
+    uint_fast32_t z;\r
+\r
+    uA.f = a;\r
+    uiA = uA.ui;\r
+    exp = expF32UI( uiA );\r
+    sig = fracF32UI( uiA );\r
+    if ( exp < 0x7F ) {\r
+        if ( exact && ( exp | sig ) ) {\r
+            softfloat_exceptionFlags |= softfloat_flag_inexact;\r
+        }\r
+        return 0;\r
+    }\r
+    if ( signF32UI( uiA ) ) goto invalid;\r
+    shiftCount = 0x9E - exp;\r
+    if ( shiftCount < 0 ) goto invalid;\r
+    sig = ( sig | 0x00800000 )<<8;\r
+    z = sig>>shiftCount;\r
+    if ( exact && ( sig & ( ( (uint_fast32_t) 1<<shiftCount ) - 1 ) ) ) {\r
+        softfloat_exceptionFlags |= softfloat_flag_inexact;\r
+    }\r
+    return z;\r
+ invalid:\r
+    softfloat_raiseFlags( softfloat_flag_invalid );\r
+    return 0xFFFFFFFF;\r
+\r
+}\r
+\r

diff --git a/softfloat/f32_to_ui64.cc b/softfloat/f32_to_ui64.cc
new file mode 100755 (executable)
index 0000000..6cdcf74
--- /dev/null
+++ b/softfloat/f32_to_ui64.cc
@@ -0,0 +1,42 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+uint_fast64_t f32_to_ui64( float32_t a, int_fast8_t roundingMode, bool exact )\r
+{\r
+    union ui32_f32 uA;\r
+    uint_fast32_t uiA;\r
+    bool sign;\r
+    int_fast16_t exp;\r
+    uint_fast32_t sig;\r
+    int_fast16_t shiftCount;\r
+    uint_fast64_t sig64, extra;\r
+    struct uint64_extra sig64Extra;\r
+\r
+    uA.f = a;\r
+    uiA = uA.ui;\r
+    sign = signF32UI( uiA );\r
+    exp = expF32UI( uiA );\r
+    sig = fracF32UI( uiA );\r
+    shiftCount = 0xBE - exp;\r
+    if ( shiftCount < 0 ) {\r
+        softfloat_raiseFlags( softfloat_flag_invalid );\r
+        return UINT64_C( 0xFFFFFFFFFFFFFFFF );\r
+    }\r
+    if ( exp ) sig |= 0x00800000;\r
+    sig64 = (uint_fast64_t) sig<<40;\r
+    extra = 0;\r
+    if ( shiftCount ) {\r
+        sig64Extra = softfloat_shift64ExtraRightJam( sig64, 0, shiftCount );\r
+        sig64 = sig64Extra.v;\r
+        extra = sig64Extra.extra;\r
+    }\r
+    return\r
+        softfloat_roundPackToUI64( sign, sig64, extra, roundingMode, exact );\r
+\r
+}\r
+\r

diff --git a/softfloat/f32_to_ui64_r_minMag.cc b/softfloat/f32_to_ui64_r_minMag.cc
new file mode 100755 (executable)
index 0000000..738d6b1
--- /dev/null
+++ b/softfloat/f32_to_ui64_r_minMag.cc
@@ -0,0 +1,45 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+uint_fast64_t f32_to_ui64_r_minMag( float32_t a, bool exact )\r
+{\r
+    union ui32_f32 uA;\r
+    uint_fast32_t uiA;\r
+    int_fast16_t exp;\r
+    uint_fast32_t sig;\r
+    int_fast16_t shiftCount;\r
+    uint_fast64_t sig64, z;\r
+\r
+    uA.f = a;\r
+    uiA = uA.ui;\r
+    exp = expF32UI( uiA );\r
+    sig = fracF32UI( uiA );\r
+    if ( exp < 0x7F ) {\r
+        if ( exact && ( exp | sig ) ) {\r
+            softfloat_exceptionFlags |= softfloat_flag_inexact;\r
+        }\r
+        return 0;\r
+    }\r
+    if ( signF32UI( uiA ) ) goto invalid;\r
+    shiftCount = 0xBE - exp;\r
+    if ( shiftCount < 0 ) goto invalid;\r
+    sig |= 0x00800000;\r
+    sig64 = (uint_fast64_t) sig<<40;\r
+    z = sig64>>shiftCount;\r
+    shiftCount = 40 - shiftCount;\r
+    if (\r
+        exact && ( shiftCount < 0 ) && (uint32_t) ( sig<<( shiftCount & 31 ) )\r
+    ) {\r
+        softfloat_exceptionFlags |= softfloat_flag_inexact;\r
+    }\r
+    return z;\r
+ invalid:\r
+    softfloat_raiseFlags( softfloat_flag_invalid );\r
+    return UINT64_C( 0xFFFFFFFFFFFFFFFF );\r
+\r
+}\r
+\r

diff --git a/softfloat/f64_add.cc b/softfloat/f64_add.cc
new file mode 100755 (executable)
index 0000000..9ec4b5f
--- /dev/null
+++ b/softfloat/f64_add.cc
@@ -0,0 +1,29 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float64_t f64_add( float64_t a, float64_t b )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    bool signA;
+    union ui64_f64 uB;
+    uint_fast64_t uiB;
+    bool signB;
+    float64_t ( *magsRoutine )( uint_fast64_t, uint_fast64_t, bool );
+
+    uA.f = a;
+    uiA = uA.ui;
+    signA = signF64UI( uiA );
+    uB.f = b;
+    uiB = uB.ui;
+    signB = signF64UI( uiB );
+    magsRoutine =
+        ( signA == signB ) ? softfloat_addMagsF64 : softfloat_subMagsF64;
+    return magsRoutine( uiA, uiB, signA );
+
+}
+

diff --git a/softfloat/f64_div.cc b/softfloat/f64_div.cc
new file mode 100755 (executable)
index 0000000..9bc72b3
--- /dev/null
+++ b/softfloat/f64_div.cc
@@ -0,0 +1,104 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float64_t f64_div( float64_t a, float64_t b )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    bool signA;
+    int_fast16_t expA;
+    uint_fast64_t sigA;
+    union ui64_f64 uB;
+    uint_fast64_t uiB;
+    bool signB;
+    int_fast16_t expB;
+    uint_fast64_t sigB;
+    bool signZ;
+    struct exp16_sig64 normExpSig;
+    int_fast16_t expZ;
+    uint_fast64_t sigZ;
+    struct uint128 term, rem;
+    uint_fast64_t uiZ;
+    union ui64_f64 uZ;
+
+    uA.f = a;
+    uiA = uA.ui;
+    signA = signF64UI( uiA );
+    expA = expF64UI( uiA );
+    sigA = fracF64UI( uiA );
+    uB.f = b;
+    uiB = uB.ui;
+    signB = signF64UI( uiB );
+    expB = expF64UI( uiB );
+    sigB = fracF64UI( uiB );
+    signZ = signA ^ signB;
+    if ( expA == 0x7FF ) {
+        if ( sigA ) goto propagateNaN;
+        if ( expB == 0x7FF ) {
+            if ( sigB ) goto propagateNaN;
+            goto invalid;
+        }
+        goto infinity;
+    }
+    if ( expB == 0x7FF ) {
+        if ( sigB ) goto propagateNaN;
+        goto zero;
+    }
+    if ( ! expB ) {
+        if ( ! sigB ) {
+            if ( ! ( expA | sigA ) ) goto invalid;
+            softfloat_raiseFlags( softfloat_flag_infinity );
+            goto infinity;
+        }
+        normExpSig = softfloat_normSubnormalF64Sig( sigB );
+        expB = normExpSig.exp;
+        sigB = normExpSig.sig;
+    }
+    if ( ! expA ) {
+        if ( ! sigA ) goto zero;
+        normExpSig = softfloat_normSubnormalF64Sig( sigA );
+        expA = normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    expZ = expA - expB + 0x3FD;
+    sigA = ( sigA | UINT64_C( 0x0010000000000000 ) )<<10;
+    sigB = ( sigB | UINT64_C( 0x0010000000000000 ) )<<11;
+    if ( sigB <= ( sigA + sigA ) ) {
+        ++expZ;
+        sigA >>= 1;
+    }
+    sigZ = softfloat_estimateDiv128To64( sigA, 0, sigB );
+    if ( ( sigZ & 0x1FF ) <= 2 ) {
+        term = softfloat_mul64To128( sigB, sigZ );
+        rem = softfloat_sub128( sigA, 0, term.v64, term.v0 );
+        while ( UINT64_C( 0x8000000000000000 ) <= rem.v64 ) {
+            --sigZ;
+            rem = softfloat_add128( rem.v64, rem.v0, 0, sigB );
+        }
+        sigZ |= ( rem.v0 != 0 );
+    }
+    return softfloat_roundPackToF64( signZ, expZ, sigZ );
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF64UI( uiA, uiB );
+    goto uiZ;
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    uiZ = defaultNaNF64UI;
+    goto uiZ;
+ infinity:
+    uiZ = packToF64UI( signZ, 0x7FF, 0 );
+    goto uiZ;
+ zero:
+    uiZ = packToF64UI( signZ, 0, 0 );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+

diff --git a/softfloat/f64_eq.cc b/softfloat/f64_eq.cc
new file mode 100755 (executable)
index 0000000..925aabc
--- /dev/null
+++ b/softfloat/f64_eq.cc
@@ -0,0 +1,35 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool f64_eq( float64_t a, float64_t b )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    union ui64_f64 uB;
+    uint_fast64_t uiB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if (
+           ( ( expF64UI( uiA ) == 0x7FF ) && fracF64UI( uiA ) )
+        || ( ( expF64UI( uiB ) == 0x7FF ) && fracF64UI( uiB ) )
+    ) {
+        if (
+            softfloat_isSigNaNF64UI( uiA ) || softfloat_isSigNaNF64UI( uiB )
+        ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    return
+        ( uiA == uiB ) || ! ( ( uiA | uiB ) & UINT64_C( 0x7FFFFFFFFFFFFFFF ) );
+
+}
+

diff --git a/softfloat/f64_eq_signaling.cc b/softfloat/f64_eq_signaling.cc
new file mode 100755 (executable)
index 0000000..7a54dc1
--- /dev/null
+++ b/softfloat/f64_eq_signaling.cc
@@ -0,0 +1,30 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+bool f64_eq_signaling( float64_t a, float64_t b )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    union ui64_f64 uB;
+    uint_fast64_t uiB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if (
+           ( ( expF64UI( uiA ) == 0x7FF ) && fracF64UI( uiA ) )
+        || ( ( expF64UI( uiB ) == 0x7FF ) && fracF64UI( uiB ) )
+    ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    return
+        ( uiA == uiB ) || ! ( ( uiA | uiB ) & UINT64_C( 0x7FFFFFFFFFFFFFFF ) );
+
+}
+

diff --git a/softfloat/f64_isSignalingNaN.cc b/softfloat/f64_isSignalingNaN.cc
new file mode 100755 (executable)
index 0000000..d720ac1
--- /dev/null
+++ b/softfloat/f64_isSignalingNaN.cc
@@ -0,0 +1,16 @@
+
+#include <stdbool.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool f64_isSignalingNaN( float64_t a )
+{
+    union ui64_f64 uA;
+
+    uA.f = a;
+    return softfloat_isSigNaNF64UI( uA.ui );
+
+}
+

diff --git a/softfloat/f64_le.cc b/softfloat/f64_le.cc
new file mode 100755 (executable)
index 0000000..e6c5caf
--- /dev/null
+++ b/softfloat/f64_le.cc
@@ -0,0 +1,35 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+bool f64_le( float64_t a, float64_t b )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    union ui64_f64 uB;
+    uint_fast64_t uiB;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if (
+           ( ( expF64UI( uiA ) == 0x7FF ) && fracF64UI( uiA ) )
+        || ( ( expF64UI( uiB ) == 0x7FF ) && fracF64UI( uiB ) )
+    ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    signA = signF64UI( uiA );
+    signB = signF64UI( uiB );
+    return
+        ( signA != signB )
+            ? signA || ! ( ( uiA | uiB ) & UINT64_C( 0x7FFFFFFFFFFFFFFF ) )
+            : ( uiA == uiB ) || ( signA ^ ( uiA < uiB ) );
+
+}
+

diff --git a/softfloat/f64_le_quiet.cc b/softfloat/f64_le_quiet.cc
new file mode 100755 (executable)
index 0000000..e9b7ede
--- /dev/null
+++ b/softfloat/f64_le_quiet.cc
@@ -0,0 +1,40 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool f64_le_quiet( float64_t a, float64_t b )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    union ui64_f64 uB;
+    uint_fast64_t uiB;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if (
+           ( ( expF64UI( uiA ) == 0x7FF ) && fracF64UI( uiA ) )
+        || ( ( expF64UI( uiB ) == 0x7FF ) && fracF64UI( uiB ) )
+    ) {
+        if (
+            softfloat_isSigNaNF64UI( uiA ) || softfloat_isSigNaNF64UI( uiB )
+        ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    signA = signF64UI( uiA );
+    signB = signF64UI( uiB );
+    return
+        ( signA != signB )
+            ? signA || ! ( ( uiA | uiB ) & UINT64_C( 0x7FFFFFFFFFFFFFFF ) )
+            : ( uiA == uiB ) || ( signA ^ ( uiA < uiB ) );
+
+}
+

diff --git a/softfloat/f64_lt.cc b/softfloat/f64_lt.cc
new file mode 100755 (executable)
index 0000000..1b2f696
--- /dev/null
+++ b/softfloat/f64_lt.cc
@@ -0,0 +1,35 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+bool f64_lt( float64_t a, float64_t b )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    union ui64_f64 uB;
+    uint_fast64_t uiB;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if (
+           ( ( expF64UI( uiA ) == 0x7FF ) && fracF64UI( uiA ) )
+        || ( ( expF64UI( uiB ) == 0x7FF ) && fracF64UI( uiB ) )
+    ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        return false;
+    }
+    signA = signF64UI( uiA );
+    signB = signF64UI( uiB );
+    return
+        ( signA != signB )
+            ? signA && ( ( uiA | uiB ) & UINT64_C( 0x7FFFFFFFFFFFFFFF ) )
+            : ( uiA != uiB ) && ( signA ^ ( uiA < uiB ) );
+
+}
+

diff --git a/softfloat/f64_lt_quiet.cc b/softfloat/f64_lt_quiet.cc
new file mode 100755 (executable)
index 0000000..f27e6da
--- /dev/null
+++ b/softfloat/f64_lt_quiet.cc
@@ -0,0 +1,40 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+bool f64_lt_quiet( float64_t a, float64_t b )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    union ui64_f64 uB;
+    uint_fast64_t uiB;
+    bool signA, signB;
+
+    uA.f = a;
+    uiA = uA.ui;
+    uB.f = b;
+    uiB = uB.ui;
+    if (
+           ( ( expF64UI( uiA ) == 0x7FF ) && fracF64UI( uiA ) )
+        || ( ( expF64UI( uiB ) == 0x7FF ) && fracF64UI( uiB ) )
+    ) {
+        if (
+            softfloat_isSigNaNF64UI( uiA ) || softfloat_isSigNaNF64UI( uiB )
+        ) {
+            softfloat_raiseFlags( softfloat_flag_invalid );
+        }
+        return false;
+    }
+    signA = signF64UI( uiA );
+    signB = signF64UI( uiB );
+    return
+        ( signA != signB )
+            ? signA && ( ( uiA | uiB ) & UINT64_C( 0x7FFFFFFFFFFFFFFF ) )
+            : ( uiA != uiB ) && ( signA ^ ( uiA < uiB ) );
+
+}
+

diff --git a/softfloat/f64_mul.cc b/softfloat/f64_mul.cc
new file mode 100755 (executable)
index 0000000..4b5dc4e
--- /dev/null
+++ b/softfloat/f64_mul.cc
@@ -0,0 +1,91 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+#include "specialize.h"\r
+#include "softfloat.h"\r
+\r
+float64_t f64_mul( float64_t a, float64_t b )\r
+{\r
+    union ui64_f64 uA;\r
+    uint_fast64_t uiA;\r
+    bool signA;\r
+    int_fast16_t expA;\r
+    uint_fast64_t sigA;\r
+    union ui64_f64 uB;\r
+    uint_fast64_t uiB;\r
+    bool signB;\r
+    int_fast16_t expB;\r
+    uint_fast64_t sigB;\r
+    bool signZ;\r
+    uint_fast64_t magBits;\r
+    struct exp16_sig64 normExpSig;\r
+    int_fast16_t expZ;\r
+    struct uint128 sigZ128;\r
+    uint_fast64_t sigZ, uiZ;\r
+    union ui64_f64 uZ;\r
+\r
+    uA.f = a;\r
+    uiA = uA.ui;\r
+    signA = signF64UI( uiA );\r
+    expA = expF64UI( uiA );\r
+    sigA = fracF64UI( uiA );\r
+    uB.f = b;\r
+    uiB = uB.ui;\r
+    signB = signF64UI( uiB );\r
+    expB = expF64UI( uiB );\r
+    sigB = fracF64UI( uiB );\r
+    signZ = signA ^ signB;\r
+    if ( expA == 0x7FF ) {\r
+        if ( sigA || ( ( expB == 0x7FF ) && sigB ) ) goto propagateNaN;\r
+        magBits = expB | sigB;\r
+        goto infArg;\r
+    }\r
+    if ( expB == 0x7FF ) {\r
+        if ( sigB ) goto propagateNaN;\r
+        magBits = expA | sigA;\r
+        goto infArg;\r
+    }\r
+    if ( ! expA ) {\r
+        if ( ! sigA ) goto zero;\r
+        normExpSig = softfloat_normSubnormalF64Sig( sigA );\r
+        expA = normExpSig.exp;\r
+        sigA = normExpSig.sig;\r
+    }\r
+    if ( ! expB ) {\r
+        if ( ! sigB ) goto zero;\r
+        normExpSig = softfloat_normSubnormalF64Sig( sigB );\r
+        expB = normExpSig.exp;\r
+        sigB = normExpSig.sig;\r
+    }\r
+    expZ = expA + expB - 0x3FF;\r
+    sigA = ( sigA | UINT64_C( 0x0010000000000000 ) )<<10;\r
+    sigB = ( sigB | UINT64_C( 0x0010000000000000 ) )<<11;\r
+    sigZ128 = softfloat_mul64To128( sigA, sigB );\r
+    sigZ = sigZ128.v64 | ( sigZ128.v0 != 0 );\r
+    if ( sigZ < UINT64_C( 0x4000000000000000 ) ) {\r
+        --expZ;\r
+        sigZ <<= 1;\r
+    }\r
+    return softfloat_roundPackToF64( signZ, expZ, sigZ );\r
+ propagateNaN:\r
+    uiZ = softfloat_propagateNaNF64UI( uiA, uiB );\r
+    goto uiZ;\r
+ infArg:\r
+    if ( ! magBits ) {\r
+        softfloat_raiseFlags( softfloat_flag_invalid );\r
+        uiZ = defaultNaNF64UI;\r
+    } else {\r
+        uiZ = packToF64UI( signZ, 0x7FF, 0 );\r
+    }\r
+    goto uiZ;\r
+ zero:\r
+    uiZ = packToF64UI( signZ, 0, 0 );\r
+ uiZ:\r
+    uZ.ui = uiZ;\r
+    return uZ.f;\r
+\r
+}\r
+\r

diff --git a/softfloat/f64_mulAdd.cc b/softfloat/f64_mulAdd.cc
new file mode 100755 (executable)
index 0000000..fa1669a
--- /dev/null
+++ b/softfloat/f64_mulAdd.cc
@@ -0,0 +1,25 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+float64_t f64_mulAdd( float64_t a, float64_t b, float64_t c )\r
+{\r
+    union ui64_f64 uA;\r
+    uint_fast64_t uiA;\r
+    union ui64_f64 uB;\r
+    uint_fast64_t uiB;\r
+    union ui64_f64 uC;\r
+    uint_fast64_t uiC;\r
+\r
+    uA.f = a;\r
+    uiA = uA.ui;\r
+    uB.f = b;\r
+    uiB = uB.ui;\r
+    uC.f = c;\r
+    uiC = uC.ui;\r
+    return softfloat_mulAddF64( 0, uiA, uiB, uiC );\r
+\r
+}\r
+\r

diff --git a/softfloat/f64_rem.cc b/softfloat/f64_rem.cc
new file mode 100755 (executable)
index 0000000..08fcd78
--- /dev/null
+++ b/softfloat/f64_rem.cc
@@ -0,0 +1,113 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float64_t f64_rem( float64_t a, float64_t b )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    bool signA;
+    int_fast16_t expA;
+    uint_fast64_t sigA;
+    union ui64_f64 uB;
+    uint_fast64_t uiB;
+    bool signB;
+    int_fast16_t expB;
+    uint_fast64_t sigB;
+    struct exp16_sig64 normExpSig;
+    int_fast16_t expDiff;
+    uint_fast64_t q, alternateSigA;
+    uint64_t sigMean;
+    bool signZ;
+    uint_fast64_t uiZ;
+    union ui64_f64 uZ;
+
+    uA.f = a;
+    uiA = uA.ui;
+    signA = signF64UI( uiA );
+    expA = expF64UI( uiA );
+    sigA = fracF64UI( uiA );
+    uB.f = b;
+    uiB = uB.ui;
+    signB = signF64UI( uiB );
+    expB = expF64UI( uiB );
+    sigB = fracF64UI( uiB );
+    if ( expA == 0x7FF ) {
+        if ( sigA || ( ( expB == 0x7FF ) && sigB ) ) goto propagateNaN;
+        goto invalid;
+    }
+    if ( expB == 0x7FF ) {
+        if ( sigB ) goto propagateNaN;
+        return a;
+    }
+    if ( ! expB ) {
+        if ( ! sigB ) goto invalid;
+        normExpSig = softfloat_normSubnormalF64Sig( sigB );
+        expB = normExpSig.exp;
+        sigB = normExpSig.sig;
+    }
+    if ( ! expA ) {
+        if ( ! sigA ) return a;
+        normExpSig = softfloat_normSubnormalF64Sig( sigA );
+        expA = normExpSig.exp;
+        sigA = normExpSig.sig;
+    }
+    expDiff = expA - expB;
+    sigA = ( sigA | UINT64_C( 0x0010000000000000 ) )<<11;
+    sigB = ( sigB | UINT64_C( 0x0010000000000000 ) )<<11;
+    if ( expDiff < 0 ) {
+        if ( expDiff < -1 ) return a;
+        sigA >>= 1;
+    }
+    q = ( sigB <= sigA );
+    if ( q ) sigA -= sigB;
+    expDiff -= 64;
+    while ( 0 < expDiff ) {
+        q = softfloat_estimateDiv128To64( sigA, 0, sigB );
+        q = ( 2 < q ) ? q - 2 : 0;
+        sigA = - ( ( sigB>>2 ) * q );
+        expDiff -= 62;
+    }
+    expDiff += 64;
+    if ( 0 < expDiff ) {
+        q = softfloat_estimateDiv128To64( sigA, 0, sigB );
+        q = ( 2 < q ) ? q - 2 : 0;
+        q >>= 64 - expDiff;
+        sigB >>= 2;
+        sigA = ( ( sigA>>1 )<<( expDiff - 1 ) ) - sigB * q;
+    } else {
+        sigA >>= 2;
+        sigB >>= 2;
+    }
+    do {
+        alternateSigA = sigA;
+        ++q;
+        sigA -= sigB;
+    } while ( sigA < UINT64_C( 0x8000000000000000 ) );
+    sigMean = sigA + alternateSigA;
+    if (
+        ( UINT64_C( 0x8000000000000000 ) <= sigMean )
+            || ( ! sigMean && ( q & 1 ) )
+    ) {
+        sigA = alternateSigA;
+    }
+    signZ = ( UINT64_C( 0x8000000000000000 ) <= sigA );
+    if ( signZ ) sigA = - sigA;
+    return softfloat_normRoundPackToF64( signA ^ signZ, expB, sigA );
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF64UI( uiA, uiB );
+    goto uiZ;
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    uiZ = defaultNaNF64UI;
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+

diff --git a/softfloat/f64_roundToInt.cc b/softfloat/f64_roundToInt.cc
new file mode 100755 (executable)
index 0000000..ef16dfa
--- /dev/null
+++ b/softfloat/f64_roundToInt.cc
@@ -0,0 +1,80 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float64_t f64_roundToInt( float64_t a, int_fast8_t roundingMode, bool exact )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    int_fast16_t expA;
+    uint_fast64_t uiZ;
+    bool signA;
+    uint_fast64_t lastBitMask, roundBitsMask;
+    union ui64_f64 uZ;
+
+    uA.f = a;
+    uiA = uA.ui;
+    expA = expF64UI( uiA );
+    if ( 0x433 <= expA ) {
+        if ( ( expA == 0x7FF ) && fracF64UI( uiA ) ) {
+            uiZ = softfloat_propagateNaNF64UI( uiA, 0 );
+            goto uiZ;
+        }
+        return a;
+    }
+    if ( expA <= 0x3FE ) {
+        if ( ! ( uiA & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) ) return a;
+        if ( exact ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+        signA = signF64UI( uiA );
+        switch ( roundingMode ) {
+         case softfloat_round_nearest_even:
+            if ( ( expA == 0x3FE ) && fracF64UI( uiA ) ) {
+                uiZ = packToF64UI( signA, 0x3FF, 0 );
+                goto uiZ;
+            }
+            break;
+         case softfloat_round_min:
+            uiZ = signA ? UINT64_C( 0xBFF0000000000000 ) : 0;
+            goto uiZ;
+         case softfloat_round_max:
+            uiZ =
+                signA ? UINT64_C( 0x8000000000000000 )
+                    : UINT64_C( 0x3FF0000000000000 );
+            goto uiZ;
+         case softfloat_round_nearest_maxMag:
+            if ( expA == 0x3FE ) {
+                uiZ = packToF64UI( signA, 0x3FF, 0 );
+                goto uiZ;
+            }
+            break;
+        }
+        uiZ = packToF64UI( signA, 0, 0 );
+        goto uiZ;
+    }
+    lastBitMask = (uint_fast64_t) 1<<( 0x433 - expA );
+    roundBitsMask = lastBitMask - 1;
+    uiZ = uiA;
+    if ( roundingMode == softfloat_round_nearest_maxMag ) {
+        uiZ += lastBitMask>>1;
+    } else if ( roundingMode == softfloat_round_nearest_even ) {
+        uiZ += lastBitMask>>1;
+        if ( ! ( uiZ & roundBitsMask ) ) uiZ &= ~ lastBitMask;
+    } else if ( roundingMode != softfloat_round_minMag ) {
+        if ( signF64UI( uiZ ) ^ ( roundingMode == softfloat_round_max ) ) {
+            uiZ += roundBitsMask;
+        }
+    }
+    uiZ &= ~ roundBitsMask;
+    if ( exact && ( uiZ != uiA ) ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+

diff --git a/softfloat/f64_sqrt.cc b/softfloat/f64_sqrt.cc
new file mode 100755 (executable)
index 0000000..cd91010
--- /dev/null
+++ b/softfloat/f64_sqrt.cc
@@ -0,0 +1,74 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+#include "specialize.h"\r
+#include "softfloat.h"\r
+\r
+float64_t f64_sqrt( float64_t a )\r
+{\r
+    union ui64_f64 uA;\r
+    uint_fast64_t uiA;\r
+    bool signA;\r
+    int_fast16_t expA;\r
+    uint_fast64_t sigA, uiZ;\r
+    struct exp16_sig64 normExpSig;\r
+    int_fast16_t expZ;\r
+    uint_fast32_t sigZ32;\r
+    uint_fast64_t sigZ;\r
+    struct uint128 term, rem;\r
+    union ui64_f64 uZ;\r
+\r
+    uA.f = a;\r
+    uiA = uA.ui;\r
+    signA = signF64UI( uiA );\r
+    expA = expF64UI( uiA );\r
+    sigA = fracF64UI( uiA );\r
+    if ( expA == 0x7FF ) {\r
+        if ( sigA ) {\r
+            uiZ = softfloat_propagateNaNF64UI( uiA, 0 );\r
+            goto uiZ;\r
+        }\r
+        if ( ! signA ) return a;\r
+        goto invalid;\r
+    }\r
+    if ( signA ) {\r
+        if ( ! ( expA | sigA ) ) return a;\r
+        goto invalid;\r
+    }\r
+    if ( ! expA ) {\r
+        if ( ! sigA ) return a;\r
+        normExpSig = softfloat_normSubnormalF64Sig( sigA );\r
+        expA = normExpSig.exp;\r
+        sigA = normExpSig.sig;\r
+    }\r
+    expZ = ( ( expA - 0x3FF )>>1 ) + 0x3FE;\r
+    sigA |= UINT64_C( 0x0010000000000000 );\r
+    sigZ32 = softfloat_estimateSqrt32( expA, sigA>>21 );\r
+    sigA <<= 9 - ( expA & 1 );\r
+    sigZ =\r
+        softfloat_estimateDiv128To64( sigA, 0, (uint_fast64_t) sigZ32<<32 )\r
+            + ( (uint_fast64_t) sigZ32<<30 );\r
+    if ( ( sigZ & 0x1FF ) <= 5 ) {\r
+        term = softfloat_mul64To128( sigZ, sigZ );\r
+        rem = softfloat_sub128( sigA, 0, term.v64, term.v0 );\r
+        while ( UINT64_C( 0x8000000000000000 ) <= rem.v64 ) {\r
+            --sigZ;\r
+            rem =\r
+                softfloat_add128(\r
+                    rem.v64, rem.v0, sigZ>>63, (uint64_t) ( sigZ<<1 ) );\r
+        }\r
+        sigZ |= ( ( rem.v64 | rem.v0 ) != 0 );\r
+    }\r
+    return softfloat_roundPackToF64( 0, expZ, sigZ );\r
+ invalid:\r
+    softfloat_raiseFlags( softfloat_flag_invalid );\r
+    uiZ = defaultNaNF64UI;\r
+ uiZ:\r
+    uZ.ui = uiZ;\r
+    return uZ.f;\r
+\r
+}\r
+\r

diff --git a/softfloat/f64_sub.cc b/softfloat/f64_sub.cc
new file mode 100755 (executable)
index 0000000..38bd574
--- /dev/null
+++ b/softfloat/f64_sub.cc
@@ -0,0 +1,29 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float64_t f64_sub( float64_t a, float64_t b )
+{
+    union ui64_f64 uA;
+    uint_fast64_t uiA;
+    bool signA;
+    union ui64_f64 uB;
+    uint_fast64_t uiB;
+    bool signB;
+    float64_t ( *magsRoutine )( uint_fast64_t, uint_fast64_t, bool );
+
+    uA.f = a;
+    uiA = uA.ui;
+    signA = signF64UI( uiA );
+    uB.f = b;
+    uiB = uB.ui;
+    signB = signF64UI( uiB );
+    magsRoutine =
+        ( signA == signB ) ? softfloat_subMagsF64 : softfloat_addMagsF64;
+    return magsRoutine( uiA, uiB, signA );
+
+}
+

diff --git a/softfloat/f64_to_f32.cc b/softfloat/f64_to_f32.cc
new file mode 100755 (executable)
index 0000000..395d6c6
--- /dev/null
+++ b/softfloat/f64_to_f32.cc
@@ -0,0 +1,43 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+#include "specialize.h"\r
+#include "softfloat.h"\r
+\r
+float32_t f64_to_f32( float64_t a )\r
+{\r
+    union ui64_f64 uA;\r
+    uint_fast64_t uiA;\r
+    bool sign;\r
+    int_fast16_t exp;\r
+    uint_fast64_t sig;\r
+    uint_fast32_t uiZ, sig32;\r
+    union ui32_f32 uZ;\r
+\r
+    uA.f = a;\r
+    uiA = uA.ui;\r
+    sign = signF64UI( uiA );\r
+    exp = expF64UI( uiA );\r
+    sig = fracF64UI( uiA );\r
+    if ( exp == 0x7FF ) {\r
+        uiZ =\r
+            sig ? softfloat_commonNaNToF32UI(\r
+                      softfloat_f64UIToCommonNaN( uiA ) )\r
+                : packToF32UI( sign, 0xFF, 0 );\r
+        goto uiZ;\r
+    }\r
+    sig32 = softfloat_shortShift64RightJam( sig, 22 );\r
+    if ( ! ( exp | sig32 ) ) {\r
+        uiZ = packToF32UI( sign, 0, 0 );\r
+        goto uiZ;\r
+    }\r
+    return softfloat_roundPackToF32( sign, exp - 0x381, sig32 | 0x40000000 );\r
+ uiZ:\r
+    uZ.ui = uiZ;\r
+    return uZ.f;\r
+\r
+}\r
+\r

diff --git a/softfloat/f64_to_i32.cc b/softfloat/f64_to_i32.cc
new file mode 100755 (executable)
index 0000000..0778a86
--- /dev/null
+++ b/softfloat/f64_to_i32.cc
@@ -0,0 +1,30 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+int_fast32_t f64_to_i32( float64_t a, int_fast8_t roundingMode, bool exact )\r
+{\r
+    union ui64_f64 uA;\r
+    uint_fast64_t uiA;\r
+    bool sign;\r
+    int_fast16_t exp;\r
+    uint_fast64_t sig;\r
+    int_fast16_t shiftCount;\r
+\r
+    uA.f = a;\r
+    uiA = uA.ui;\r
+    sign = signF64UI( uiA );\r
+    exp = expF64UI( uiA );\r
+    sig = fracF64UI( uiA );\r
+    if ( ( exp == 0x7FF ) && sig ) sign = 0;\r
+    if ( exp ) sig |= UINT64_C( 0x0010000000000000 );\r
+    shiftCount = 0x42C - exp;\r
+    if ( 0 < shiftCount ) sig = softfloat_shift64RightJam( sig, shiftCount );\r
+    return softfloat_roundPackToI32( sign, sig, roundingMode, exact );\r
+\r
+}\r
+\r

diff --git a/softfloat/f64_to_i32_r_minMag.cc b/softfloat/f64_to_i32_r_minMag.cc
new file mode 100755 (executable)
index 0000000..39246c2
--- /dev/null
+++ b/softfloat/f64_to_i32_r_minMag.cc
@@ -0,0 +1,50 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+int_fast32_t f64_to_i32_r_minMag( float64_t a, bool exact )\r
+{\r
+    union ui64_f64 uA;\r
+    uint_fast64_t uiA;\r
+    int_fast16_t exp;\r
+    uint_fast64_t sig;\r
+    bool sign;\r
+    int_fast16_t shiftCount;\r
+    uint_fast32_t absZ;\r
+    union { uint32_t ui; int32_t i; } uZ;\r
+    int_fast32_t z;\r
+\r
+    uA.f = a;\r
+    uiA = uA.ui;\r
+    exp = expF64UI( uiA );\r
+    sig = fracF64UI( uiA );\r
+    if ( exp < 0x3FF ) {\r
+        if ( exact && ( exp | sig ) ) {\r
+            softfloat_exceptionFlags |= softfloat_flag_inexact;\r
+        }\r
+        return 0;\r
+    }\r
+    sign = signF64UI( uiA );\r
+    if ( 0x41E < exp ) {\r
+        if ( ( exp == 0x7FF ) && sig ) sign = 0;\r
+        goto invalid;\r
+    }\r
+    sig |= UINT64_C( 0x0010000000000000 );\r
+    shiftCount = 0x433 - exp;\r
+    absZ = sig>>shiftCount;\r
+    uZ.ui = sign ? - absZ : absZ;\r
+    z = uZ.i;\r
+    if ( ( z < 0 ) != sign ) goto invalid;\r
+    if ( exact && ( (uint_fast64_t) absZ<<shiftCount != sig ) ) {\r
+        softfloat_exceptionFlags |= softfloat_flag_inexact;\r
+    }\r
+    return z;\r
+ invalid:\r
+    softfloat_raiseFlags( softfloat_flag_invalid );\r
+    return sign ? -0x7FFFFFFF - 1 : 0x7FFFFFFF;\r
+\r
+}\r
+\r

diff --git a/softfloat/f64_to_i64.cc b/softfloat/f64_to_i64.cc
new file mode 100755 (executable)
index 0000000..89663ee
--- /dev/null
+++ b/softfloat/f64_to_i64.cc
@@ -0,0 +1,46 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+int_fast64_t f64_to_i64( float64_t a, int_fast8_t roundingMode, bool exact )\r
+{\r
+    union ui64_f64 uA;\r
+    uint_fast64_t uiA;\r
+    bool sign;\r
+    int_fast16_t exp;\r
+    uint_fast64_t sig;\r
+    int_fast16_t shiftCount;\r
+    struct uint64_extra sigExtra;\r
+\r
+    uA.f = a;\r
+    uiA = uA.ui;\r
+    sign = signF64UI( uiA );\r
+    exp = expF64UI( uiA );\r
+    sig = fracF64UI( uiA );\r
+    if ( exp ) sig |= UINT64_C( 0x0010000000000000 );\r
+    shiftCount = 0x433 - exp;\r
+    if ( shiftCount <= 0 ) {\r
+        if ( 0x43E < exp ) {\r
+            softfloat_raiseFlags( softfloat_flag_invalid );\r
+            return\r
+                ! sign\r
+                    || ( ( exp == 0x7FF )\r
+                             && ( sig != UINT64_C( 0x0010000000000000 ) ) )\r
+                    ? INT64_C( 0x7FFFFFFFFFFFFFFF )\r
+                    : - INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1;\r
+        }\r
+        sigExtra.v = sig<<( - shiftCount );\r
+        sigExtra.extra = 0;\r
+    } else {\r
+        sigExtra = softfloat_shift64ExtraRightJam( sig, 0, shiftCount );\r
+    }\r
+    return\r
+        softfloat_roundPackToI64(\r
+            sign, sigExtra.v, sigExtra.extra, roundingMode, exact );\r
+\r
+}\r
+\r

diff --git a/softfloat/f64_to_i64_r_minMag.cc b/softfloat/f64_to_i64_r_minMag.cc
new file mode 100755 (executable)
index 0000000..525705b
--- /dev/null
+++ b/softfloat/f64_to_i64_r_minMag.cc
@@ -0,0 +1,52 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+int_fast64_t f64_to_i64_r_minMag( float64_t a, bool exact )\r
+{\r
+    union ui64_f64 uA;\r
+    uint_fast64_t uiA;\r
+    bool sign;\r
+    int_fast16_t exp;\r
+    uint_fast64_t sig;\r
+    int_fast16_t shiftCount;\r
+    int_fast64_t absZ;\r
+\r
+    uA.f = a;\r
+    uiA = uA.ui;\r
+    sign = signF64UI( uiA );\r
+    exp = expF64UI( uiA );\r
+    sig = fracF64UI( uiA );\r
+    shiftCount = exp - 0x433;\r
+    if ( 0 <= shiftCount ) {\r
+        if ( 0x43E <= exp ) {\r
+            if ( uiA != packToF64UI( 1, 0x43E, 0 ) ) {\r
+                softfloat_raiseFlags( softfloat_flag_invalid );\r
+                if ( ! sign || ( ( exp == 0x7FF ) && sig ) ) {\r
+                    return INT64_C( 0x7FFFFFFFFFFFFFFF );\r
+                }\r
+            }\r
+            return - INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1;\r
+        }\r
+        sig |= UINT64_C( 0x0010000000000000 );\r
+        absZ = sig<<shiftCount;\r
+    } else {\r
+        if ( exp < 0x3FF ) {\r
+            if ( exact && ( exp | sig ) ) {\r
+                softfloat_exceptionFlags |= softfloat_flag_inexact;\r
+            }\r
+            return 0;\r
+        }\r
+        sig |= UINT64_C( 0x0010000000000000 );\r
+        absZ = sig>>( - shiftCount );\r
+        if ( exact && (uint64_t) ( sig<<( shiftCount & 63 ) ) ) {\r
+            softfloat_exceptionFlags |= softfloat_flag_inexact;\r
+        }\r
+    }\r
+    return sign ? - absZ : absZ;\r
+\r
+}\r
+\r

diff --git a/softfloat/f64_to_ui32.cc b/softfloat/f64_to_ui32.cc
new file mode 100755 (executable)
index 0000000..b186605
--- /dev/null
+++ b/softfloat/f64_to_ui32.cc
@@ -0,0 +1,29 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+uint_fast32_t f64_to_ui32( float64_t a, int_fast8_t roundingMode, bool exact )\r
+{\r
+    union ui64_f64 uA;\r
+    uint_fast64_t uiA;\r
+    bool sign;\r
+    int_fast16_t exp;\r
+    uint_fast64_t sig;\r
+    int_fast16_t shiftCount;\r
+\r
+    uA.f = a;\r
+    uiA = uA.ui;\r
+    sign = signF64UI( uiA );\r
+    exp = expF64UI( uiA );\r
+    sig = fracF64UI( uiA );\r
+    if ( exp ) sig |= UINT64_C( 0x0010000000000000 );\r
+    shiftCount = 0x42C - exp;\r
+    if ( 0 < shiftCount ) sig = softfloat_shift64RightJam( sig, shiftCount );\r
+    return softfloat_roundPackToUI32( sign, sig, roundingMode, exact );\r
+\r
+}\r
+\r

diff --git a/softfloat/f64_to_ui32_r_minMag.cc b/softfloat/f64_to_ui32_r_minMag.cc
new file mode 100755 (executable)
index 0000000..9f1dd4d
--- /dev/null
+++ b/softfloat/f64_to_ui32_r_minMag.cc
@@ -0,0 +1,40 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+uint_fast32_t f64_to_ui32_r_minMag( float64_t a, bool exact )\r
+{\r
+    union ui64_f64 uA;\r
+    uint_fast64_t uiA;\r
+    int_fast16_t exp;\r
+    uint_fast64_t sig;\r
+    int_fast16_t shiftCount;\r
+    uint_fast32_t z;\r
+\r
+    uA.f = a;\r
+    uiA = uA.ui;\r
+    exp = expF64UI( uiA );\r
+    sig = fracF64UI( uiA );\r
+    if ( exp < 0x3FF ) {\r
+        if ( exact && ( exp | sig ) ) {\r
+            softfloat_exceptionFlags |= softfloat_flag_inexact;\r
+        }\r
+        return 0;\r
+    }\r
+    if ( signF64UI( uiA ) || ( 0x41E < exp ) ) {\r
+        softfloat_raiseFlags( softfloat_flag_invalid );\r
+        return 0xFFFFFFFF;\r
+    }\r
+    sig |= UINT64_C( 0x0010000000000000 );\r
+    shiftCount = 0x433 - exp;\r
+    z = sig>>shiftCount;\r
+    if ( exact && ( (uint_fast64_t) z<<shiftCount != sig ) ) {\r
+        softfloat_exceptionFlags |= softfloat_flag_inexact;\r
+    }\r
+    return z;\r
+\r
+}\r
+\r

diff --git a/softfloat/f64_to_ui64.cc b/softfloat/f64_to_ui64.cc
new file mode 100755 (executable)
index 0000000..9afebd7
--- /dev/null
+++ b/softfloat/f64_to_ui64.cc
@@ -0,0 +1,41 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+uint_fast64_t f64_to_ui64( float64_t a, int_fast8_t roundingMode, bool exact )\r
+{\r
+    union ui64_f64 uA;\r
+    uint_fast64_t uiA;\r
+    bool sign;\r
+    int_fast16_t exp;\r
+    uint_fast64_t sig;\r
+    int_fast16_t shiftCount;\r
+    struct uint64_extra sigExtra;\r
+\r
+    uA.f = a;\r
+    uiA = uA.ui;\r
+    sign = signF64UI( uiA );\r
+    exp = expF64UI( uiA );\r
+    sig = fracF64UI( uiA );\r
+    if ( exp ) sig |= UINT64_C( 0x0010000000000000 );\r
+    shiftCount = 0x433 - exp;\r
+    if ( shiftCount <= 0 ) {\r
+        if ( 0x43E < exp ) {\r
+            softfloat_raiseFlags( softfloat_flag_invalid );\r
+            return UINT64_C( 0xFFFFFFFFFFFFFFFF );\r
+        }\r
+        sigExtra.v = sig<<( - shiftCount );\r
+        sigExtra.extra = 0;\r
+    } else {\r
+        sigExtra = softfloat_shift64ExtraRightJam( sig, 0, shiftCount );\r
+    }\r
+    return\r
+        softfloat_roundPackToUI64(\r
+            sign, sigExtra.v, sigExtra.extra, roundingMode, exact );\r
+\r
+}\r
+\r

diff --git a/softfloat/f64_to_ui64_r_minMag.cc b/softfloat/f64_to_ui64_r_minMag.cc
new file mode 100755 (executable)
index 0000000..a66d3ff
--- /dev/null
+++ b/softfloat/f64_to_ui64_r_minMag.cc
@@ -0,0 +1,45 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+uint_fast64_t f64_to_ui64_r_minMag( float64_t a, bool exact )\r
+{\r
+    union ui64_f64 uA;\r
+    uint_fast64_t uiA;\r
+    int_fast16_t exp;\r
+    uint_fast64_t sig;\r
+    int_fast16_t shiftCount;\r
+    uint_fast64_t z;\r
+\r
+    uA.f = a;\r
+    uiA = uA.ui;\r
+    exp = expF64UI( uiA );\r
+    sig = fracF64UI( uiA );\r
+    if ( exp < 0x3FF ) {\r
+        if ( exact && ( exp | sig ) ) {\r
+            softfloat_exceptionFlags |= softfloat_flag_inexact;\r
+        }\r
+        return 0;\r
+    }\r
+    if ( signF64UI( uiA ) ) goto invalid;\r
+    shiftCount = exp - 0x433;\r
+    if ( 0 <= shiftCount ) {\r
+        if ( 0x43E < exp ) goto invalid;\r
+        z = ( sig | UINT64_C( 0x0010000000000000 ) )<<shiftCount;\r
+    } else {\r
+        sig |= UINT64_C( 0x0010000000000000 );\r
+        z = sig>>( - shiftCount );\r
+        if ( exact && (uint64_t) ( sig<<( shiftCount & 63 ) ) ) {\r
+            softfloat_exceptionFlags |= softfloat_flag_inexact;\r
+        }\r
+    }\r
+    return z;\r
+ invalid:\r
+    softfloat_raiseFlags( softfloat_flag_invalid );\r
+    return UINT64_C( 0xFFFFFFFFFFFFFFFF );\r
+\r
+}\r
+\r

diff --git a/softfloat/i32_to_f32.cc b/softfloat/i32_to_f32.cc
new file mode 100755 (executable)
index 0000000..f51facd
--- /dev/null
+++ b/softfloat/i32_to_f32.cc
@@ -0,0 +1,21 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+float32_t i32_to_f32( int_fast32_t a )\r
+{\r
+    bool sign;\r
+    union ui32_f32 uZ;\r
+\r
+    sign = ( a < 0 );\r
+    if ( ! ( a & 0x7FFFFFFF ) ) {\r
+        uZ.ui = sign ? packToF32UI( 1, 0x9E, 0 ) : 0;\r
+        return uZ.f;\r
+    }\r
+    return softfloat_normRoundPackToF32( sign, 0x9C, sign ? - a : a );\r
+\r
+}\r
+\r

diff --git a/softfloat/i32_to_f64.cc b/softfloat/i32_to_f64.cc
new file mode 100755 (executable)
index 0000000..d42cbe8
--- /dev/null
+++ b/softfloat/i32_to_f64.cc
@@ -0,0 +1,31 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+float64_t i32_to_f64( int_fast32_t a )\r
+{\r
+    uint_fast64_t uiZ;\r
+    bool sign;\r
+    uint_fast32_t absA;\r
+    int shiftCount;\r
+    union ui64_f64 uZ;\r
+\r
+    if ( ! a ) {\r
+        uiZ = 0;\r
+    } else {\r
+        sign = ( a < 0 );\r
+        absA = sign ? - a : a;\r
+        shiftCount = softfloat_countLeadingZeros32( absA ) + 21;\r
+        uiZ =\r
+            packToF64UI(\r
+                sign, 0x432 - shiftCount, (uint_fast64_t) absA<<shiftCount );\r
+    }\r
+    uZ.ui = uiZ;\r
+    return uZ.f;\r
+\r
+}\r
+\r

diff --git a/softfloat/i64_to_f32.cc b/softfloat/i64_to_f32.cc
new file mode 100755 (executable)
index 0000000..4fecbb9
--- /dev/null
+++ b/softfloat/i64_to_f32.cc
@@ -0,0 +1,36 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+float32_t i64_to_f32( int_fast64_t a )\r
+{\r
+    bool sign;\r
+    uint_fast64_t absA;\r
+    int shiftCount;\r
+    union ui32_f32 u;\r
+    uint_fast32_t sig;\r
+\r
+    sign = ( a < 0 );\r
+    absA = sign ? - (uint_fast64_t) a : a;\r
+    shiftCount = softfloat_countLeadingZeros64( absA ) - 40;\r
+    if ( 0 <= shiftCount ) {\r
+        u.ui =\r
+            a ? packToF32UI(\r
+                    sign, 0x95 - shiftCount, (uint_fast32_t) absA<<shiftCount )\r
+                : 0;\r
+        return u.f;\r
+    } else {\r
+        shiftCount += 7;\r
+        sig =\r
+            ( shiftCount < 0 )\r
+                ? softfloat_shortShift64RightJam( absA, - shiftCount )\r
+                : (uint_fast32_t) absA<<shiftCount;\r
+        return softfloat_roundPackToF32( sign, 0x9C - shiftCount, sig );\r
+    }\r
+\r
+}\r
+\r

diff --git a/softfloat/i64_to_f64.cc b/softfloat/i64_to_f64.cc
new file mode 100755 (executable)
index 0000000..1add960
--- /dev/null
+++ b/softfloat/i64_to_f64.cc
@@ -0,0 +1,21 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+float64_t i64_to_f64( int_fast64_t a )\r
+{\r
+    bool sign;\r
+    union ui64_f64 uZ;\r
+\r
+    sign = ( a < 0 );\r
+    if ( ! ( a & UINT64_C( 0x7FFFFFFFFFFFFFFF ) ) ) {\r
+        uZ.ui = sign ? packToF64UI( 1, 0x43E, 0 ) : 0;\r
+        return uZ.f;\r
+    }\r
+    return softfloat_normRoundPackToF64( sign, 0x43C, sign ? - a : a );\r
+\r
+}\r
+\r

diff --git a/softfloat/internals.h b/softfloat/internals.h
new file mode 100755 (executable)
index 0000000..5e6fd76
--- /dev/null
+++ b/softfloat/internals.h
@@ -0,0 +1,232 @@
+\r
+/*** UPDATE COMMENTS. ***/\r
+\r
+#include "softfloat_types.h"\r
+\r
+union ui32_f32 { uint32_t ui; float32_t f; };\r
+union ui64_f64 { uint64_t ui; float64_t f; };\r
+#ifdef LITTLEENDIAN\r
+union ui128_f128 { uint64_t ui0, ui64; float128_t f; };\r
+#else\r
+union ui128_f128 { uint64_t ui64, ui0; float128_t f; };\r
+#endif\r
+\r
+enum {\r
+    softfloat_mulAdd_subC    = 1,\r
+    softfloat_mulAdd_subProd = 2\r
+};\r
+\r
+uint_fast32_t\r
+ softfloat_roundPackToUI32( bool, uint_fast64_t, int_fast8_t, bool );\r
+uint_fast64_t\r
+ softfloat_roundPackToUI64(\r
+     bool, uint_fast64_t, uint_fast64_t, int_fast8_t, bool );\r
+/*----------------------------------------------------------------------------\r
+| Takes a 64-bit fixed-point value `absZ' with binary point between bits 6\r
+| and 7, and returns the properly rounded 32-bit integer corresponding to the\r
+| input.  If `zSign' is 1, the input is negated before being converted to an\r
+| integer.  Bit 63 of `absZ' must be zero.  Ordinarily, the fixed-point input\r
+| is simply rounded to an integer, with the inexact exception raised if the\r
+| input cannot be represented exactly as an integer.  However, if the fixed-\r
+| point input is too large, the invalid exception is raised and the largest\r
+| positive or negative integer is returned.\r
+*----------------------------------------------------------------------------*/\r
+int_fast32_t\r
+ softfloat_roundPackToI32( bool, uint_fast64_t, int_fast8_t, bool );\r
+/*----------------------------------------------------------------------------\r
+| Takes the 128-bit fixed-point value formed by concatenating `absZ0' and\r
+| `absZ1', with binary point between bits 63 and 64 (between the input words),\r
+| and returns the properly rounded 64-bit integer corresponding to the input.\r
+| If `zSign' is 1, the input is negated before being converted to an integer.\r
+| Ordinarily, the fixed-point input is simply rounded to an integer, with\r
+| the inexact exception raised if the input cannot be represented exactly as\r
+| an integer.  However, if the fixed-point input is too large, the invalid\r
+| exception is raised and the largest positive or negative integer is\r
+| returned.\r
+*----------------------------------------------------------------------------*/\r
+int_fast64_t\r
+ softfloat_roundPackToI64(\r
+     bool, uint_fast64_t, uint_fast64_t, int_fast8_t, bool );\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the single-precision floating-point value `a' is a NaN;\r
+| otherwise, returns 0.\r
+*----------------------------------------------------------------------------*/\r
+#define isNaNF32UI( ui ) (0xFF000000<(uint32_t)((uint_fast32_t)(ui)<<1))\r
+/*----------------------------------------------------------------------------\r
+| Returns the sign bit of the single-precision floating-point value `a'.\r
+*----------------------------------------------------------------------------*/\r
+#define signF32UI( a ) ((bool)((uint32_t)(a)>>31))\r
+/*----------------------------------------------------------------------------\r
+| Returns the exponent bits of the single-precision floating-point value `a'.\r
+*----------------------------------------------------------------------------*/\r
+#define expF32UI( a ) ((int_fast16_t)((a)>>23)&0xFF)\r
+/*----------------------------------------------------------------------------\r
+| Returns the fraction bits of the single-precision floating-point value `a'.\r
+*----------------------------------------------------------------------------*/\r
+#define fracF32UI( a ) ((a)&0x007FFFFF)\r
+/*----------------------------------------------------------------------------\r
+| Packs the sign `zSign', exponent `zExp', and significand `zSig' into a\r
+| single-precision floating-point value, returning the result.  After being\r
+| shifted into the proper positions, the three fields are simply added\r
+| together to form the result.  This means that any integer portion of `zSig'\r
+| will be added into the exponent.  Since a properly normalized significand\r
+| will have an integer portion equal to 1, the `zExp' input should be 1 less\r
+| than the desired result exponent whenever `zSig' is a complete, normalized\r
+| significand.\r
+*----------------------------------------------------------------------------*/\r
+#define packToF32UI( sign, exp, sig ) (((uint32_t)(sign)<<31)+((uint32_t)(exp)<<23)+(sig))\r
+\r
+/*----------------------------------------------------------------------------\r
+| Normalizes the subnormal single-precision floating-point value represented\r
+| by the denormalized significand `aSig'.  The normalized exponent and\r
+| significand are stored at the locations pointed to by `zExpPtr' and\r
+| `zSigPtr', respectively.\r
+*----------------------------------------------------------------------------*/\r
+struct exp16_sig32 { int_fast16_t exp; uint_fast32_t sig; };\r
+struct exp16_sig32 softfloat_normSubnormalF32Sig( uint_fast32_t );\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
+| and significand `zSig', and returns the proper single-precision floating-\r
+| point value corresponding to the abstract input.  Ordinarily, the abstract\r
+| value is simply rounded and packed into the single-precision format, with\r
+| the inexact exception raised if the abstract input cannot be represented\r
+| exactly.  However, if the abstract value is too large, the overflow and\r
+| inexact exceptions are raised and an infinity or maximal finite value is\r
+| returned.  If the abstract value is too small, the input value is rounded to\r
+| a subnormal number, and the underflow and inexact exceptions are raised if\r
+| the abstract input cannot be represented exactly as a subnormal single-\r
+| precision floating-point number.\r
+|     The input significand `zSig' has its binary point between bits 30\r
+| and 29, which is 7 bits to the left of the usual location.  This shifted\r
+| significand must be normalized or smaller.  If `zSig' is not normalized,\r
+| `zExp' must be 0; in that case, the result returned is a subnormal number,\r
+| and it must not require rounding.  In the usual case that `zSig' is\r
+| normalized, `zExp' must be 1 less than the ``true'' floating-point exponent.\r
+| The handling of underflow and overflow follows the IEC/IEEE Standard for\r
+| Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+float32_t softfloat_roundPackToF32( bool, int_fast16_t, uint_fast32_t );\r
+/*----------------------------------------------------------------------------\r
+| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
+| and significand `zSig', and returns the proper single-precision floating-\r
+| point value corresponding to the abstract input.  This routine is just like\r
+| `roundAndPackFloat32' except that `zSig' does not have to be normalized.\r
+| Bit 31 of `zSig' must be zero, and `zExp' must be 1 less than the ``true''\r
+| floating-point exponent.\r
+*----------------------------------------------------------------------------*/\r
+float32_t softfloat_normRoundPackToF32( bool, int_fast16_t, uint_fast32_t );\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of adding the absolute values of the single-precision\r
+| floating-point values `a' and `b'.  If `zSign' is 1, the sum is negated\r
+| before being returned.  `zSign' is ignored if the result is a NaN.\r
+| The addition is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+float32_t softfloat_addMagsF32( uint_fast32_t, uint_fast32_t, bool );\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of subtracting the absolute values of the single-\r
+| precision floating-point values `a' and `b'.  If `zSign' is 1, the\r
+| difference is negated before being returned.  `zSign' is ignored if the\r
+| result is a NaN.  The subtraction is performed according to the IEC/IEEE\r
+| Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+float32_t softfloat_subMagsF32( uint_fast32_t, uint_fast32_t, bool );\r
+/*----------------------------------------------------------------------------\r
+*----------------------------------------------------------------------------*/\r
+float32_t\r
+ softfloat_mulAddF32( int, uint_fast32_t, uint_fast32_t, uint_fast32_t );\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the double-precision floating-point value `a' is a NaN;\r
+| otherwise, returns 0.\r
+*----------------------------------------------------------------------------*/\r
+#define isNaNF64UI( ui ) (UINT64_C(0xFFE0000000000000)<(uint64_t)((uint_fast64_t)(ui)<<1))\r
+/*----------------------------------------------------------------------------\r
+| Returns the sign bit of the double-precision floating-point value `a'.\r
+*----------------------------------------------------------------------------*/\r
+#define signF64UI( a ) ((bool)((uint64_t)(a)>>63))\r
+/*----------------------------------------------------------------------------\r
+| Returns the exponent bits of the double-precision floating-point value `a'.\r
+*----------------------------------------------------------------------------*/\r
+#define expF64UI( a ) ((int_fast16_t)((a)>>52)&0x7FF)\r
+/*----------------------------------------------------------------------------\r
+| Returns the fraction bits of the double-precision floating-point value `a'.\r
+*----------------------------------------------------------------------------*/\r
+#define fracF64UI( a ) ((a)&UINT64_C(0x000FFFFFFFFFFFFF))\r
+/*----------------------------------------------------------------------------\r
+| Packs the sign `zSign', exponent `zExp', and significand `zSig' into a\r
+| double-precision floating-point value, returning the result.  After being\r
+| shifted into the proper positions, the three fields are simply added\r
+| together to form the result.  This means that any integer portion of `zSig'\r
+| will be added into the exponent.  Since a properly normalized significand\r
+| will have an integer portion equal to 1, the `zExp' input should be 1 less\r
+| than the desired result exponent whenever `zSig' is a complete, normalized\r
+| significand.\r
+*----------------------------------------------------------------------------*/\r
+#define packToF64UI( sign, exp, sig ) (((uint64_t)(sign)<<63)+((uint64_t)(exp)<<52)+(sig))\r
+\r
+/*----------------------------------------------------------------------------\r
+| Normalizes the subnormal double-precision floating-point value represented\r
+| by the denormalized significand `aSig'.  The normalized exponent and\r
+| significand are stored at the locations pointed to by `zExpPtr' and\r
+| `zSigPtr', respectively.\r
+*----------------------------------------------------------------------------*/\r
+struct exp16_sig64 { int_fast16_t exp; uint_fast64_t sig; };\r
+struct exp16_sig64 softfloat_normSubnormalF64Sig( uint_fast64_t );\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
+| and significand `zSig', and returns the proper double-precision floating-\r
+| point value corresponding to the abstract input.  Ordinarily, the abstract\r
+| value is simply rounded and packed into the double-precision format, with\r
+| the inexact exception raised if the abstract input cannot be represented\r
+| exactly.  However, if the abstract value is too large, the overflow and\r
+| inexact exceptions are raised and an infinity or maximal finite value is\r
+| returned.  If the abstract value is too small, the input value is rounded\r
+| to a subnormal number, and the underflow and inexact exceptions are raised\r
+| if the abstract input cannot be represented exactly as a subnormal double-\r
+| precision floating-point number.\r
+|     The input significand `zSig' has its binary point between bits 62\r
+| and 61, which is 10 bits to the left of the usual location.  This shifted\r
+| significand must be normalized or smaller.  If `zSig' is not normalized,\r
+| `zExp' must be 0; in that case, the result returned is a subnormal number,\r
+| and it must not require rounding.  In the usual case that `zSig' is\r
+| normalized, `zExp' must be 1 less than the ``true'' floating-point exponent.\r
+| The handling of underflow and overflow follows the IEC/IEEE Standard for\r
+| Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+float64_t softfloat_roundPackToF64( bool, int_fast16_t, uint_fast64_t );\r
+/*----------------------------------------------------------------------------\r
+| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
+| and significand `zSig', and returns the proper double-precision floating-\r
+| point value corresponding to the abstract input.  This routine is just like\r
+| `roundAndPackFloat64' except that `zSig' does not have to be normalized.\r
+| Bit 63 of `zSig' must be zero, and `zExp' must be 1 less than the ``true''\r
+| floating-point exponent.\r
+*----------------------------------------------------------------------------*/\r
+float64_t softfloat_normRoundPackToF64( bool, int_fast16_t, uint_fast64_t );\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of adding the absolute values of the double-precision\r
+| floating-point values `a' and `b'.  If `zSign' is 1, the sum is negated\r
+| before being returned.  `zSign' is ignored if the result is a NaN.\r
+| The addition is performed according to the IEC/IEEE Standard for Binary\r
+| Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+float64_t softfloat_addMagsF64( uint_fast64_t, uint_fast64_t, bool );\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of subtracting the absolute values of the double-\r
+| precision floating-point values `a' and `b'.  If `zSign' is 1, the\r
+| difference is negated before being returned.  `zSign' is ignored if the\r
+| result is a NaN.  The subtraction is performed according to the IEC/IEEE\r
+| Standard for Binary Floating-Point Arithmetic.\r
+*----------------------------------------------------------------------------*/\r
+float64_t softfloat_subMagsF64( uint_fast64_t, uint_fast64_t, bool );\r
+/*----------------------------------------------------------------------------\r
+*----------------------------------------------------------------------------*/\r
+float64_t\r
+ softfloat_mulAddF64( int, uint_fast64_t, uint_fast64_t, uint_fast64_t );\r
+\r

diff --git a/softfloat/milieu.h b/softfloat/milieu.h
deleted file mode 100644 (file)
index ab3d371..0000000
--- a/softfloat/milieu.h
+++ /dev/null
@@ -1,68 +0,0 @@
-
-/*----------------------------------------------------------------------------
-| One of the macros `BIGENDIAN' or `LITTLEENDIAN' must be defined.
-*----------------------------------------------------------------------------*/
-#define BIGENDIAN
-
-/*----------------------------------------------------------------------------
-| The macro `BITS64' can be defined to indicate that 64-bit integer types are
-| supported by the compiler.
-*----------------------------------------------------------------------------*/
-#define BITS64
-
-/*----------------------------------------------------------------------------
-| Each of the following `typedef's defines the most convenient type that holds
-| integers of at least as many bits as specified.  For example, `uint8' should
-| be the most convenient type that can hold unsigned integers of as many as
-| 8 bits.  The `flag' type must be able to hold either a 0 or 1.  For most
-| implementations of C, `flag', `uint8', and `int8' should all be `typedef'ed
-| to the same as `int'.
-*----------------------------------------------------------------------------*/
-typedef int flag;
-typedef int uint8;
-typedef int int8;
-typedef int uint16;
-typedef int int16;
-typedef unsigned int uint32;
-typedef signed int int32;
-#ifdef BITS64
-typedef unsigned long long int uint64;
-typedef signed long long int int64;
-#endif
-
-/*----------------------------------------------------------------------------
-| Each of the following `typedef's defines a type that holds integers
-| of _exactly_ the number of bits specified.  For instance, for most
-| implementation of C, `bits16' and `sbits16' should be `typedef'ed to
-| `unsigned short int' and `signed short int' (or `short int'), respectively.
-*----------------------------------------------------------------------------*/
-typedef unsigned char bits8;
-typedef signed char sbits8;
-typedef unsigned short int bits16;
-typedef signed short int sbits16;
-typedef unsigned int bits32;
-typedef signed int sbits32;
-#ifdef BITS64
-typedef unsigned long long int bits64;
-typedef signed long long int sbits64;
-#endif
-
-#ifdef BITS64
-/*----------------------------------------------------------------------------
-| The `LIT64' macro takes as its argument a textual integer literal and
-| if necessary ``marks'' the literal as having a 64-bit integer type.
-| For example, the GNU C Compiler (`gcc') requires that 64-bit literals be
-| appended with the letters `LL' standing for `long long', which is `gcc's
-| name for the 64-bit integer type.  Some compilers may allow `LIT64' to be
-| defined as the identity macro:  `#define LIT64( a ) a'.
-*----------------------------------------------------------------------------*/
-#define LIT64( a ) a##LL
-#endif
-
-/*----------------------------------------------------------------------------
-| The macro `INLINE' can be used before functions that should be inlined.  If
-| a compiler does not support explicit inlining, this macro should be defined
-| to be `static'.
-*----------------------------------------------------------------------------*/
-#define INLINE extern inline
-

diff --git a/softfloat/primitives.h b/softfloat/primitives.h
new file mode 100755 (executable)
index 0000000..71038ea
--- /dev/null
+++ b/softfloat/primitives.h
@@ -0,0 +1,628 @@
+
+/*============================================================================
+
+This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
+Arithmetic Package, Release 3.
+
+*** UPDATE
+
+Written by John R. Hauser.  This work was made possible in part by the
+International Computer Science Institute, located at Suite 600, 1947 Center
+Street, Berkeley, California 94704.  Funding was partially provided by the
+National Science Foundation under grant MIP-9311980.  The original version
+of this code was written as part of a project to build a fixed-point vector
+processor in collaboration with the University of California at Berkeley,
+overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/
+arithmetic/SoftFloat.html'.
+
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
+RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
+INSTITUTE (possibly via similar legal notice) AGAINST ALL LOSSES, COSTS, OR
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
+
+Derivative works are acceptable, even for commercial purposes, so long as
+(1) the source code for the derivative work includes prominent notice that
+the work is derivative, and (2) the source code includes prominent notice with
+these four paragraphs for those parts of this code that are retained.
+
+=============================================================================*/
+
+#include <stdbool.h>
+#include <stdint.h>
+
+/*** CHANGE TO USE `fast' INTEGER TYPES? ***/
+/*** ADD 80-BIT FUNCTIONS? ***/
+
+#ifdef LITTLEENDIAN
+struct uintx80 { uint64_t v0; uint16_t v64; };
+struct uint128 { uint64_t v0, v64; };
+struct uint192 { uint64_t v0, v64, v128; };
+struct uint256 { uint64_t v0, v64, v128, v192; };
+#else
+struct uintx80 { uint16_t v64; uint64_t v0; };
+struct uint128 { uint64_t v64, v0; };
+struct uint192 { uint64_t v128, v64, v0; };
+struct uint256 { uint64_t v256, v128, v64, v0; };
+#endif
+
+struct uint64_extra { uint64_t v, extra; };
+struct uint128_extra { uint64_t v64; uint64_t v0; uint64_t extra; };
+
+
+/*** SHIFT COUNTS CANNOT BE ZERO.  MUST CHECK BEFORE CALLING! ***/
+
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the 128-bit value formed by concatenating `a0' and `a1'
+| is equal to the 128-bit value formed by concatenating `b0' and `b1'.
+| Otherwise, returns 0.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && ( 1 <= INLINE_LEVEL )
+INLINE bool
+ softfloat_eq128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+    { return ( a64 == b64 ) && ( a0 == b0 ); }
+#else
+bool softfloat_eq128( uint64_t, uint64_t, uint64_t, uint64_t );
+#endif
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' is less
+| than or equal to the 128-bit value formed by concatenating `b0' and `b1'.
+| Otherwise, returns 0.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && ( 1 <= INLINE_LEVEL )
+INLINE bool
+ softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+    { return ( a64 < b64 ) || ( ( a64 == b64 ) && ( a0 <= b0 ) ); }
+#else
+bool softfloat_le128( uint64_t, uint64_t, uint64_t, uint64_t );
+#endif
+
+/*----------------------------------------------------------------------------
+| Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' is less
+| than the 128-bit value formed by concatenating `b0' and `b1'.  Otherwise,
+| returns 0.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && ( 1 <= INLINE_LEVEL )
+INLINE bool
+ softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+    { return ( a64 < b64 ) || ( ( a64 == b64 ) && ( a0 < b0 ) ); }
+#else
+bool softfloat_lt128( uint64_t, uint64_t, uint64_t, uint64_t );
+#endif
+
+/*----------------------------------------------------------------------------
+| Shifts the 128-bit value formed by concatenating `a0' and `a1' left by the
+| number of bits given in `count'.  Any bits shifted off are lost.  The value
+| of `count' must be less than 64.  The result is broken into two 64-bit
+| pieces which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && ( 2 <= INLINE_LEVEL )
+INLINE struct uint128
+ softfloat_shortShift128Left( uint64_t a64, uint64_t a0, unsigned int count )
+{
+    struct uint128 z;
+    z.v64 = a64<<count | a0>>( ( - count ) & 63 );
+    z.v0 = a0<<count;
+    return z;
+}
+#else
+struct uint128 softfloat_shortShift128Left( uint64_t, uint64_t, unsigned int );
+#endif
+
+/*----------------------------------------------------------------------------
+| Shifts the 192-bit value formed by concatenating `a0', `a1', and `a2' left
+| by the number of bits given in `count'.  Any bits shifted off are lost.
+| The value of `count' must be less than 64.  The result is broken into three
+| 64-bit pieces which are stored at the locations pointed to by `z0Ptr',
+| `z1Ptr', and `z2Ptr'.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && ( 3 <= INLINE_LEVEL )
+INLINE struct uint192
+ softfloat_shortShift192Left(
+     uint64_t a128, uint64_t a64, uint64_t a0, unsigned int count )
+{
+    unsigned int negCount = - count;
+    struct uint192 z;
+    z.v128 = a128<<count | a64>>( negCount & 63 );
+    z.v64 = a64<<count | a0>>( negCount & 63 );
+    z.v0 = a0<<count;
+    return z;
+}
+#else
+struct uint192
+ softfloat_shortShift192Left( uint64_t, uint64_t, uint64_t, unsigned int );
+#endif
+
+/*----------------------------------------------------------------------------
+| Shifts `a' right by the number of bits given in `count'.  If any nonzero
+| bits are shifted off, they are ``jammed'' into the least significant bit of
+| the result by setting the least significant bit to 1.  The value of `count'
+| can be arbitrarily large; in particular, if `count' is greater than 32, the
+| result will be either 0 or 1, depending on whether `a' is zero or nonzero.
+| The result is stored in the location pointed to by `zPtr'.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && ( 2 <= INLINE_LEVEL )
+INLINE uint32_t softfloat_shift32RightJam( uint32_t a, unsigned int count )
+{
+    return
+        ( count < 32 )
+            ? a>>count | ( (uint32_t) ( a<<( ( - count ) & 31 ) ) != 0 )
+            : ( a != 0 );
+}
+#else
+uint32_t softfloat_shift32RightJam( uint32_t, unsigned int );
+#endif
+
+/*----------------------------------------------------------------------------
+| Shift count is less than 32.
+*----------------------------------------------------------------------------*/
+#if defined INLINE
+INLINE uint32_t softfloat_shortShift32Right1Jam( uint32_t a )
+    { return a>>1 | ( a & 1 ); }
+#else
+uint32_t softfloat_shortShift32Right1Jam( uint32_t );
+#endif
+
+/*----------------------------------------------------------------------------
+| Shifts `a' right by the number of bits given in `count'.  If any nonzero
+| bits are shifted off, they are ``jammed'' into the least significant bit of
+| the result by setting the least significant bit to 1.  The value of `count'
+| can be arbitrarily large; in particular, if `count' is greater than 64, the
+| result will be either 0 or 1, depending on whether `a' is zero or nonzero.
+| The result is stored in the location pointed to by `zPtr'.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && ( 3 <= INLINE_LEVEL )
+INLINE uint64_t softfloat_shift64RightJam( uint64_t a, unsigned int count )
+{
+    return
+        ( count < 64 )
+            ? a>>count | ( (uint64_t) ( a<<( ( - count ) & 63 ) ) != 0 )
+            : ( a != 0 );
+}
+#else
+uint64_t softfloat_shift64RightJam( uint64_t, unsigned int );
+#endif
+
+/*----------------------------------------------------------------------------
+| Shift count is less than 64.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && ( 2 <= INLINE_LEVEL )
+INLINE uint64_t
+ softfloat_shortShift64RightJam( uint64_t a, unsigned int count )
+    { return a>>count | ( ( a & ( ( (uint64_t) 1<<count ) - 1 ) ) != 0 ); }
+#else
+uint64_t softfloat_shortShift64RightJam( uint64_t, unsigned int );
+#endif
+
+/*----------------------------------------------------------------------------
+| Shifts the 128-bit value formed by concatenating `a0' and `a1' right by 64
+| _plus_ the number of bits given in `count'.  The shifted result is at most
+| 64 nonzero bits; this is stored at the location pointed to by `z0Ptr'.  The
+| bits shifted off form a second 64-bit result as follows:  The _last_ bit
+| shifted off is the most-significant bit of the extra result, and the other
+| 63 bits of the extra result are all zero if and only if _all_but_the_last_
+| bits shifted off were all zero.  This extra result is stored in the location
+| pointed to by `z1Ptr'.  The value of `count' can be arbitrarily large.
+|     (This routine makes more sense if `a0' and `a1' are considered to form
+| a fixed-point value with binary point between `a0' and `a1'.  This fixed-
+| point value is shifted right by the number of bits given in `count', and
+| the integer part of the result is returned at the location pointed to by
+| `z0Ptr'.  The fractional part of the result may be slightly corrupted as
+| described above, and is returned at the location pointed to by `z1Ptr'.)
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && ( 3 <= INLINE_LEVEL )
+INLINE struct uint64_extra
+ softfloat_shift64ExtraRightJam(
+     uint64_t a, uint64_t extra, unsigned int count )
+{
+    struct uint64_extra z;
+    if ( count < 64 ) {
+        z.v = a>>count;
+        z.extra = a<<( ( - count ) & 63 );
+    } else {
+        z.v = 0;
+        z.extra = ( count == 64 ) ? a : ( a != 0 );
+    }
+    z.extra |= ( extra != 0 );
+    return z;
+}
+#else
+struct uint64_extra
+ softfloat_shift64ExtraRightJam( uint64_t, uint64_t, unsigned int );
+#endif
+
+/*----------------------------------------------------------------------------
+| Shift count is less than 64.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && ( 2 <= INLINE_LEVEL )
+INLINE struct uint64_extra
+ softfloat_shortShift64ExtraRightJam(
+     uint64_t a, uint64_t extra, unsigned int count )
+{
+    struct uint64_extra z;
+    z.v = a>>count;
+    z.extra = a<<( ( - count ) & 63 ) | ( extra != 0 );
+    return z;
+}
+#else
+struct uint64_extra
+ softfloat_shortShift64ExtraRightJam( uint64_t, uint64_t, unsigned int );
+#endif
+
+/*----------------------------------------------------------------------------
+| Shifts the 128-bit value formed by concatenating `a0' and `a1' right by the
+| number of bits given in `count'.  Any bits shifted off are lost.  The value
+| of `count' can be arbitrarily large; in particular, if `count' is greater
+| than 128, the result will be 0.  The result is broken into two 64-bit pieces
+| which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
+*----------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------
+| Shift count is less than 64.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && ( 2 <= INLINE_LEVEL )
+INLINE struct uint128
+ softfloat_shortShift128Right( uint64_t a64, uint64_t a0, unsigned int count )
+{
+    struct uint128 z;
+    z.v64 = a64>>count;
+    z.v0 = a64<<( ( - count ) & 63 ) | a0>>count;
+    return z;
+}
+#else
+struct uint128
+ softfloat_shortShift128Right( uint64_t, uint64_t, unsigned int );
+#endif
+
+/*----------------------------------------------------------------------------
+| Shifts the 128-bit value formed by concatenating `a0' and `a1' right by the
+| number of bits given in `count'.  If any nonzero bits are shifted off, they
+| are ``jammed'' into the least significant bit of the result by setting the
+| least significant bit to 1.  The value of `count' can be arbitrarily large;
+| in particular, if `count' is greater than 128, the result will be either
+| 0 or 1, depending on whether the concatenation of `a0' and `a1' is zero or
+| nonzero.  The result is broken into two 64-bit pieces which are stored at
+| the locations pointed to by `z0Ptr' and `z1Ptr'.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && ( 4 <= INLINE_LEVEL )
+INLINE struct uint128
+ softfloat_shift128RightJam( uint64_t a64, uint64_t a0, unsigned int count )
+{
+    unsigned int negCount;
+    struct uint128 z;
+    if ( count < 64 ) {
+        negCount = - count;
+        z.v64 = a64>>( count & 63 );
+        z.v0 =
+            a64<<( negCount & 63 ) | a0>>count
+                | ( (uint64_t) ( a0<<( negCount & 63 ) ) != 0 );
+    } else {
+        z.v64 = 0;
+        z.v0 =
+            ( count < 128 )
+                ? a64>>( count & 63 )
+                      | ( ( ( a64 & ( ( (uint64_t) 1<<( count & 63 ) ) - 1 ) )
+                                | a0 )
+                              != 0 )
+                : ( ( a64 | a0 ) != 0 );
+    }
+    return z;
+}
+#else
+struct uint128
+ softfloat_shift128RightJam( uint64_t, uint64_t, unsigned int );
+#endif
+
+/*----------------------------------------------------------------------------
+| Shifts the 192-bit value formed by concatenating `a0', `a1', and `a2' right
+| by 64 _plus_ the number of bits given in `count'.  The shifted result is
+| at most 128 nonzero bits; these are broken into two 64-bit pieces which are
+| stored at the locations pointed to by `z0Ptr' and `z1Ptr'.  The bits shifted
+| off form a third 64-bit result as follows:  The _last_ bit shifted off is
+| the most-significant bit of the extra result, and the other 63 bits of the
+| extra result are all zero if and only if _all_but_the_last_ bits shifted off
+| were all zero.  This extra result is stored in the location pointed to by
+| `z2Ptr'.  The value of `count' can be arbitrarily large.
+|     (This routine makes more sense if `a0', `a1', and `a2' are considered
+| to form a fixed-point value with binary point between `a1' and `a2'.  This
+| fixed-point value is shifted right by the number of bits given in `count',
+| and the integer part of the result is returned at the locations pointed to
+| by `z0Ptr' and `z1Ptr'.  The fractional part of the result may be slightly
+| corrupted as described above, and is returned at the location pointed to by
+| `z2Ptr'.)
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && ( 5 <= INLINE_LEVEL )
+INLINE struct uint128_extra
+ softfloat_shift128ExtraRightJam(
+     uint64_t a64, uint64_t a0, uint64_t extra, unsigned int count )
+{
+    unsigned int negCount = - count;
+    struct uint128_extra z;
+    if ( count < 64 ) {
+        z.v64 = a64>>count;
+        z.v0 = a64<<( negCount & 63 ) | a0>>count;
+        z.extra = a0<<( negCount & 63 );
+    } else {
+        z.v64 = 0;
+        if ( count == 64 ) {
+            z.v0 = a64;
+            z.extra = a0;
+        } else {
+            extra |= a0;
+            if ( count < 128 ) {
+                z.v0 = a64>>( count & 63 );
+                z.extra = a64<<( negCount & 63 );
+            } else {
+                z.v0 = 0;
+                z.extra = ( count == 128 ) ? a64 : ( a64 != 0 );
+            }
+        }
+    }
+    z.extra |= ( extra != 0 );
+    return z;
+}
+#else
+struct uint128_extra
+ softfloat_shift128ExtraRightJam( uint64_t, uint64_t, uint64_t, unsigned int );
+#endif
+
+/*----------------------------------------------------------------------------
+| Shift count is less than 64.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && ( 3 <= INLINE_LEVEL )
+INLINE struct uint128_extra
+ softfloat_shortShift128ExtraRightJam(
+     uint64_t a64, uint64_t a0, uint64_t extra, unsigned int count )
+{
+    unsigned int negCount = - count;
+    struct uint128_extra z;
+    z.v64 = a64>>count;
+    z.v0 = a64<<( negCount & 63 ) | a0>>count;
+    z.extra = a0<<( negCount & 63 ) | ( extra != 0 );
+    return z;
+}
+#else
+struct uint128_extra
+ softfloat_shortShift128ExtraRightJam(
+     uint64_t, uint64_t, uint64_t, unsigned int );
+#endif
+
+extern const uint8_t softfloat_countLeadingZeros8[ 256 ];
+
+/*----------------------------------------------------------------------------
+| Returns the number of leading 0 bits before the most-significant 1 bit of
+| `a'.  If `a' is zero, 32 is returned.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && ( 2 <= INLINE_LEVEL )
+INLINE int softfloat_countLeadingZeros32( uint32_t a )
+{
+    int count = 0;
+    if ( a < 0x10000 ) {
+        count = 16;
+        a <<= 16;
+    }
+    if ( a < 0x1000000 ) {
+        count += 8;
+        a <<= 8;
+    }
+    count += softfloat_countLeadingZeros8[ a>>24 ];
+    return count;
+}
+#else
+int softfloat_countLeadingZeros32( uint32_t );
+#endif
+
+/*----------------------------------------------------------------------------
+| Returns the number of leading 0 bits before the most-significant 1 bit of
+| `a'.  If `a' is zero, 64 is returned.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && ( 4 <= INLINE_LEVEL )
+INLINE int softfloat_countLeadingZeros64( uint64_t a )
+{
+    int count = 32;
+    uint32_t a32 = a;
+    if ( UINT64_C( 0x100000000 ) <= a ) {
+        count = 0;
+        a32 = a>>32;
+    }
+    /*------------------------------------------------------------------------
+    | From here, result is current count + count leading zeros of `a32'.
+    *------------------------------------------------------------------------*/
+    if ( a32 < 0x10000 ) {
+        count += 16;
+        a32 <<= 16;
+    }
+    if ( a32 < 0x1000000 ) {
+        count += 8;
+        a32 <<= 8;
+    }
+    count += softfloat_countLeadingZeros8[ a32>>24 ];
+    return count;
+}
+#else
+int softfloat_countLeadingZeros64( uint64_t );
+#endif
+
+/*----------------------------------------------------------------------------
+| Adds the 128-bit value formed by concatenating `a0' and `a1' to the 128-bit
+| value formed by concatenating `b0' and `b1'.  Addition is modulo 2^128, so
+| any carry out is lost.  The result is broken into two 64-bit pieces which
+| are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && ( 2 <= INLINE_LEVEL )
+INLINE struct uint128
+ softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+{
+    struct uint128 z;
+    z.v0 = a0 + b0;
+    z.v64 = a64 + b64;
+    z.v64 += ( z.v0 < a0 );
+    return z;
+}
+#else
+struct uint128 softfloat_add128( uint64_t, uint64_t, uint64_t, uint64_t );
+#endif
+
+/*----------------------------------------------------------------------------
+| Adds the 192-bit value formed by concatenating `a0', `a1', and `a2' to the
+| 192-bit value formed by concatenating `b0', `b1', and `b2'.  Addition is
+| modulo 2^192, so any carry out is lost.  The result is broken into three
+| 64-bit pieces which are stored at the locations pointed to by `z0Ptr',
+| `z1Ptr', and `z2Ptr'.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && ( 3 <= INLINE_LEVEL )
+INLINE struct uint192
+ softfloat_add192(
+     uint64_t a128,
+     uint64_t a64,
+     uint64_t a0,
+     uint64_t b128,
+     uint64_t b64,
+     uint64_t b0
+ )
+{
+    struct uint192 z;
+    unsigned int carry64, carry128;
+    z.v0 = a0 + b0;
+    carry64 = ( z.v0 < a0 );
+    z.v64 = a64 + b64;
+    carry128 = ( z.v64 < a64 );
+    z.v128 = a128 + b128;
+    z.v64 += carry64;
+    carry128 += ( z.v64 < carry64 );
+    z.v128 += carry128;
+    return z;
+}
+#else
+struct uint192
+ softfloat_add192(
+     uint64_t, uint64_t, uint64_t, uint64_t, uint64_t, uint64_t );
+#endif
+
+/*----------------------------------------------------------------------------
+| Subtracts the 128-bit value formed by concatenating `b0' and `b1' from the
+| 128-bit value formed by concatenating `a0' and `a1'.  Subtraction is modulo
+| 2^128, so any borrow out (carry out) is lost.  The result is broken into two
+| 64-bit pieces which are stored at the locations pointed to by `z0Ptr' and
+| `z1Ptr'.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && ( 2 <= INLINE_LEVEL )
+INLINE struct uint128
+ softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+{
+    struct uint128 z;
+    z.v0 = a0 - b0;
+    z.v64 = a64 - b64;
+    z.v64 -= ( a0 < b0 );
+    return z;
+}
+#else
+struct uint128 softfloat_sub128( uint64_t, uint64_t, uint64_t, uint64_t );
+#endif
+
+/*----------------------------------------------------------------------------
+| Subtracts the 192-bit value formed by concatenating `b0', `b1', and `b2'
+| from the 192-bit value formed by concatenating `a0', `a1', and `a2'.
+| Subtraction is modulo 2^192, so any borrow out (carry out) is lost.  The
+| result is broken into three 64-bit pieces which are stored at the locations
+| pointed to by `z0Ptr', `z1Ptr', and `z2Ptr'.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && ( 3 <= INLINE_LEVEL )
+INLINE struct uint192
+ softfloat_sub192(
+     uint64_t a128,
+     uint64_t a64,
+     uint64_t a0,
+     uint64_t b128,
+     uint64_t b64,
+     uint64_t b0
+ )
+{
+    struct uint192 z;
+    unsigned int borrow64, borrow128;
+    z.v0 = a0 - b0;
+    borrow64 = ( a0 < b0 );
+    z.v64 = a64 - b64;
+    borrow128 = ( a64 < b64 );
+    z.v128 = a128 - b128;
+    borrow128 += ( z.v64 < borrow64 );
+    z.v64 -= borrow64;
+    z.v128 -= borrow128;
+    return z;
+}
+#else
+struct uint192
+ softfloat_sub192(
+     uint64_t, uint64_t, uint64_t, uint64_t, uint64_t, uint64_t );
+#endif
+
+/*----------------------------------------------------------------------------
+| Multiplies `a' by `b' to obtain a 128-bit product.  The product is broken
+| into two 64-bit pieces which are stored at the locations pointed to by
+| `z0Ptr' and `z1Ptr'.
+*----------------------------------------------------------------------------*/
+#if defined INLINE_LEVEL && ( 4 <= INLINE_LEVEL )
+INLINE struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b )
+{
+    uint32_t a32 = a>>32;
+    uint32_t a0 = a;
+    uint32_t b32 = b>>32;
+    uint32_t b0 = b;
+    struct uint128 z;
+    uint64_t mid1, mid2, mid;
+    z.v0 = (uint64_t) a0 * b0;
+    mid1 = (uint64_t) a32 * b0;
+    mid2 = (uint64_t) a0 * b32;
+    z.v64 = (uint64_t) a32 * b32;
+    mid = mid1 + mid2;
+    z.v64 += ( (uint64_t) ( mid < mid1 ) )<<32 | mid>>32;
+    mid <<= 32;
+    z.v0 += mid;
+    z.v64 += ( z.v0 < mid );
+    return z;
+}
+#else
+struct uint128 softfloat_mul64To128( uint64_t, uint64_t );
+#endif
+
+/*----------------------------------------------------------------------------
+| Multiplies the 128-bit value formed by concatenating `a0' and `a1' by
+| `b' to obtain a 192-bit product.  The product is broken into three 64-bit
+| pieces which are stored at the locations pointed to by `z0Ptr', `z1Ptr', and
+| `z2Ptr'.
+*----------------------------------------------------------------------------*/
+struct uint192 softfloat_mul128By64To192( uint64_t, uint64_t, uint64_t );
+/*----------------------------------------------------------------------------
+| Multiplies the 128-bit value formed by concatenating `a0' and `a1' to the
+| 128-bit value formed by concatenating `b0' and `b1' to obtain a 256-bit
+| product.  The product is broken into four 64-bit pieces which are stored at
+| the locations pointed to by `z0Ptr', `z1Ptr', `z2Ptr', and `z3Ptr'.
+*----------------------------------------------------------------------------*/
+struct uint256 softfloat_mul128To256( uint64_t, uint64_t, uint64_t, uint64_t );
+
+/*----------------------------------------------------------------------------
+| Returns an approximation to the 64-bit integer quotient obtained by dividing
+| `b' into the 128-bit value formed by concatenating `a0' and `a1'.  The
+| divisor `b' must be at least 2^63.  If q is the exact quotient truncated
+| toward zero, the approximation returned lies between q and q + 2 inclusive.
+| If the exact quotient q is larger than 64 bits, the maximum positive 64-bit
+| unsigned integer is returned.
+*----------------------------------------------------------------------------*/
+uint64_t softfloat_estimateDiv128To64( uint64_t, uint64_t, uint64_t );
+
+/*----------------------------------------------------------------------------
+| Returns an approximation to the square root of the 32-bit significand given
+| by `a'.  Considered as an integer, `a' must be at least 2^31.  If bit 0 of
+| `aExp' (the least significant bit) is 1, the integer returned approximates
+| 2^31*sqrt(`a'/2^31), where `a' is considered an integer.  If bit 0 of `aExp'
+| is 0, the integer returned approximates 2^31*sqrt(`a'/2^30).  In either
+| case, the approximation returned lies strictly within +/-2 of the exact
+| value.
+*----------------------------------------------------------------------------*/
+uint32_t softfloat_estimateSqrt32( unsigned int, uint32_t );
+

diff --git a/softfloat/s_add128.cc b/softfloat/s_add128.cc
new file mode 100755 (executable)
index 0000000..59c0348
--- /dev/null
+++ b/softfloat/s_add128.cc
@@ -0,0 +1,17 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+\r
+struct uint128\r
+ softfloat_add128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )\r
+{\r
+    struct uint128 z;\r
+\r
+    z.v0 = a0 + b0;\r
+    z.v64 = a64 + b64;\r
+    z.v64 += ( z.v0 < a0 );\r
+    return z;\r
+\r
+}\r
+\r

diff --git a/softfloat/s_add192.cc b/softfloat/s_add192.cc
new file mode 100755 (executable)
index 0000000..543eb5d
--- /dev/null
+++ b/softfloat/s_add192.cc
@@ -0,0 +1,30 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+\r
+struct uint192\r
+ softfloat_add192(\r
+     uint64_t a128,\r
+     uint64_t a64,\r
+     uint64_t a0,\r
+     uint64_t b128,\r
+     uint64_t b64,\r
+     uint64_t b0\r
+ )\r
+{\r
+    struct uint192 z;\r
+    unsigned int carry64, carry128;\r
+\r
+    z.v0 = a0 + b0;\r
+    carry64 = ( z.v0 < a0 );\r
+    z.v64 = a64 + b64;\r
+    carry128 = ( z.v64 < a64 );\r
+    z.v128 = a128 + b128;\r
+    z.v64 += carry64;\r
+    carry128 += ( z.v64 < carry64 );\r
+    z.v128 += carry128;\r
+    return z;\r
+\r
+}\r
+\r

diff --git a/softfloat/s_addMagsF32.cc b/softfloat/s_addMagsF32.cc
new file mode 100755 (executable)
index 0000000..f361e2b
--- /dev/null
+++ b/softfloat/s_addMagsF32.cc
@@ -0,0 +1,75 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+#include "specialize.h"\r
+\r
+float32_t\r
+ softfloat_addMagsF32( uint_fast32_t uiA, uint_fast32_t uiB, bool signZ )\r
+{\r
+    int_fast16_t expA;\r
+    uint_fast32_t sigA;\r
+    int_fast16_t expB;\r
+    uint_fast32_t sigB;\r
+    int_fast16_t expDiff;\r
+    uint_fast32_t uiZ;\r
+    int_fast16_t expZ;\r
+    uint_fast32_t sigZ;\r
+    union ui32_f32 uZ;\r
+\r
+    expA = expF32UI( uiA );\r
+    sigA = fracF32UI( uiA );\r
+    expB = expF32UI( uiB );\r
+    sigB = fracF32UI( uiB );\r
+    expDiff = expA - expB;\r
+    sigA <<= 6;\r
+    sigB <<= 6;\r
+    if ( ! expDiff ) {\r
+        if ( expA == 0xFF ) {\r
+            if ( sigA | sigB ) goto propagateNaN;\r
+            uiZ = uiA;\r
+            goto uiZ;\r
+        }\r
+        if ( ! expA ) {\r
+            uiZ = packToF32UI( signZ, 0, ( uiA + uiB ) & 0x7FFFFFFF );\r
+            goto uiZ;\r
+        }\r
+        expZ = expA;\r
+        sigZ = 0x40000000 + sigA + sigB;\r
+    } else {\r
+        if ( expDiff < 0 ) {\r
+            if ( expB == 0xFF ) {\r
+                if ( sigB ) goto propagateNaN;\r
+                uiZ = packToF32UI( signZ, 0xFF, 0 );\r
+                goto uiZ;\r
+            }\r
+            expZ = expB;\r
+            sigA += expA ? 0x20000000 : sigA;\r
+            sigA = softfloat_shift32RightJam( sigA, - expDiff );\r
+        } else {\r
+            if ( expA == 0xFF ) {\r
+                if ( sigA ) goto propagateNaN;\r
+                uiZ = uiA;\r
+                goto uiZ;\r
+            }\r
+            expZ = expA;\r
+            sigB += expB ? 0x20000000 : sigB;\r
+            sigB = softfloat_shift32RightJam( sigB, expDiff );\r
+        }\r
+        sigZ = 0x20000000 + sigA + sigB;\r
+        if ( sigZ < 0x40000000 ) {\r
+            --expZ;\r
+            sigZ <<= 1;\r
+        }\r
+    }\r
+    return softfloat_roundPackToF32( signZ, expZ, sigZ );\r
+ propagateNaN:\r
+    uiZ = softfloat_propagateNaNF32UI( uiA, uiB );\r
+ uiZ:\r
+    uZ.ui = uiZ;\r
+    return uZ.f;\r
+\r
+}\r
+\r

diff --git a/softfloat/s_addMagsF64.cc b/softfloat/s_addMagsF64.cc
new file mode 100755 (executable)
index 0000000..a81c3e4
--- /dev/null
+++ b/softfloat/s_addMagsF64.cc
@@ -0,0 +1,77 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "internals.h"
+#include "specialize.h"
+
+float64_t
+ softfloat_addMagsF64( uint_fast64_t uiA, uint_fast64_t uiB, bool signZ )
+{
+    int_fast16_t expA;
+    uint_fast64_t sigA;
+    int_fast16_t expB;
+    uint_fast64_t sigB;
+    int_fast16_t expDiff;
+    uint_fast64_t uiZ;
+    int_fast16_t expZ;
+    uint_fast64_t sigZ;
+    union ui64_f64 uZ;
+
+    expA = expF64UI( uiA );
+    sigA = fracF64UI( uiA );
+    expB = expF64UI( uiB );
+    sigB = fracF64UI( uiB );
+    expDiff = expA - expB;
+    sigA <<= 9;
+    sigB <<= 9;
+    if ( ! expDiff ) {
+        if ( expA == 0x7FF ) {
+            if ( sigA | sigB ) goto propagateNaN;
+            uiZ = uiA;
+            goto uiZ;
+        }
+        if ( ! expA ) {
+            uiZ =
+                packToF64UI(
+                    signZ, 0, ( uiA + uiB ) & UINT64_C( 0x7FFFFFFFFFFFFFFF ) );
+            goto uiZ;
+        }
+        expZ = expA;
+        sigZ = UINT64_C( 0x4000000000000000 ) + sigA + sigB;
+    } else {
+        if ( expDiff < 0 ) {
+            if ( expB == 0x7FF ) {
+                if ( sigB ) goto propagateNaN;
+                uiZ = packToF64UI( signZ, 0x7FF, 0 );
+                goto uiZ;
+            }
+            expZ = expB;
+            sigA += expA ? UINT64_C( 0x2000000000000000 ) : sigA;
+            sigA = softfloat_shift64RightJam( sigA, - expDiff );
+        } else {
+            if ( expA == 0x7FF ) {
+                if ( sigA ) goto propagateNaN;
+                uiZ = uiA;
+                goto uiZ;
+            }
+            expZ = expA;
+            sigB += expB ? UINT64_C( 0x2000000000000000 ) : sigB;
+            sigB = softfloat_shift64RightJam( sigB, expDiff );
+        }
+        sigZ = UINT64_C( 0x2000000000000000 ) + sigA + sigB;
+        if ( sigZ < UINT64_C( 0x4000000000000000 ) ) {
+            --expZ;
+            sigZ <<= 1;
+        }
+    }
+    return softfloat_roundPackToF64( signZ, expZ, sigZ );
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF64UI( uiA, uiB );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+

diff --git a/softfloat/s_countLeadingZeros32.cc b/softfloat/s_countLeadingZeros32.cc
new file mode 100755 (executable)
index 0000000..0bd17e1
--- /dev/null
+++ b/softfloat/s_countLeadingZeros32.cc
@@ -0,0 +1,22 @@
+
+#include <stdint.h>
+#include "primitives.h"
+
+int softfloat_countLeadingZeros32( uint32_t a )
+{
+    int count;
+
+    count = 0;
+    if ( a < 0x10000 ) {
+        count = 16;
+        a <<= 16;
+    }
+    if ( a < 0x1000000 ) {
+        count += 8;
+        a <<= 8;
+    }
+    count += softfloat_countLeadingZeros8[ a>>24 ];
+    return count;
+
+}
+

diff --git a/softfloat/s_countLeadingZeros64.cc b/softfloat/s_countLeadingZeros64.cc
new file mode 100755 (executable)
index 0000000..79f4280
--- /dev/null
+++ b/softfloat/s_countLeadingZeros64.cc
@@ -0,0 +1,32 @@
+
+#include <stdint.h>
+#include "primitives.h"
+#include "platform.h"
+
+int softfloat_countLeadingZeros64( uint64_t a )
+{
+    int count;
+    uint32_t a32;
+
+    count = 32;
+    a32 = a;
+    if ( UINT64_C( 0x100000000 ) <= a ) {
+        count = 0;
+        a32 = a>>32;
+    }
+    /*------------------------------------------------------------------------
+    | From here, result is current count + count leading zeros of `a32'.
+    *------------------------------------------------------------------------*/
+    if ( a32 < 0x10000 ) {
+        count += 16;
+        a32 <<= 16;
+    }
+    if ( a32 < 0x1000000 ) {
+        count += 8;
+        a32 <<= 8;
+    }
+    count += softfloat_countLeadingZeros8[ a32>>24 ];
+    return count;
+
+}
+

diff --git a/softfloat/s_countLeadingZeros8.cc b/softfloat/s_countLeadingZeros8.cc
new file mode 100755 (executable)
index 0000000..4eca7e9
--- /dev/null
+++ b/softfloat/s_countLeadingZeros8.cc
@@ -0,0 +1,24 @@
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+
+const uint8_t softfloat_countLeadingZeros8[ 256 ] = {
+    8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4,
+    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+

diff --git a/softfloat/s_eq128.cc b/softfloat/s_eq128.cc
new file mode 100755 (executable)
index 0000000..7261dc4
--- /dev/null
+++ b/softfloat/s_eq128.cc
@@ -0,0 +1,13 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+
+bool softfloat_eq128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )
+{
+
+    return ( a64 == b64 ) && ( a0 == b0 );
+
+}
+

diff --git a/softfloat/s_estimateDiv128To64.cc b/softfloat/s_estimateDiv128To64.cc
new file mode 100755 (executable)
index 0000000..f8610a2
--- /dev/null
+++ b/softfloat/s_estimateDiv128To64.cc
@@ -0,0 +1,28 @@
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+
+uint64_t softfloat_estimateDiv128To64( uint64_t a64, uint64_t a0, uint64_t b )
+{
+    uint32_t b32;
+    uint64_t z;
+    struct uint128 term, rem;
+    uint64_t rem32;
+
+    if ( b <= a64 ) return UINT64_C( 0xFFFFFFFFFFFFFFFF );
+    b32 = b>>32;
+    z = ( (uint64_t) b32<<32 <= a64 ) ? UINT64_C( 0xFFFFFFFF00000000 )
+            : ( a64 / b32 )<<32;
+    term = softfloat_mul64To128( b, z );
+    rem = softfloat_sub128( a64, a0, term.v64, term.v0 );
+    while ( UINT64_C( 0x8000000000000000 ) <= rem.v64 ) {
+        z -= UINT64_C( 0x100000000 );
+        rem = softfloat_add128( rem.v64, rem.v0, b32, (uint64_t) ( b<<32 ) );
+    }
+    rem32 = ( rem.v64<<32 ) | ( rem.v0>>32 );
+    z |= ( (uint64_t) b32<<32 <= rem32 ) ? 0xFFFFFFFF : rem32 / b32;
+    return z;
+
+}
+

diff --git a/softfloat/s_estimateSqrt32.cc b/softfloat/s_estimateSqrt32.cc
new file mode 100755 (executable)
index 0000000..e22a9dc
--- /dev/null
+++ b/softfloat/s_estimateSqrt32.cc
@@ -0,0 +1,37 @@
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+
+uint32_t softfloat_estimateSqrt32( unsigned int expA, uint32_t a )
+{
+    static const uint16_t sqrtOddAdjustments[] = {
+        0x0004, 0x0022, 0x005D, 0x00B1, 0x011D, 0x019F, 0x0236, 0x02E0,
+        0x039C, 0x0468, 0x0545, 0x0631, 0x072B, 0x0832, 0x0946, 0x0A67
+    };
+    static const uint16_t sqrtEvenAdjustments[] = {
+        0x0A2D, 0x08AF, 0x075A, 0x0629, 0x051A, 0x0429, 0x0356, 0x029E,
+        0x0200, 0x0179, 0x0109, 0x00AF, 0x0068, 0x0034, 0x0012, 0x0002
+    };
+    int index;
+    uint32_t z;
+    union { uint32_t ui; int32_t i; } u32;
+
+    index = ( a>>27 ) & 15;
+    if ( expA & 1 ) {
+        z = 0x4000 + ( a>>17 ) - sqrtOddAdjustments[ index ];
+        z = ( ( a / z )<<14 ) + ( z<<15 );
+        a >>= 1;
+    } else {
+        z = 0x8000 + ( a>>17 ) - sqrtEvenAdjustments[ index ];
+        z = a / z + z;
+        z = ( 0x20000 <= z ) ? 0xFFFF8000 : z<<15;
+        if ( z <= a ) {
+            u32.ui = a;
+            return u32.i>>1;
+        }
+    }
+    return (uint32_t) ( ( (uint64_t) a<<31 ) / z ) + ( z>>1 );
+
+}
+

diff --git a/softfloat/s_le128.cc b/softfloat/s_le128.cc
new file mode 100755 (executable)
index 0000000..83b1d7f
--- /dev/null
+++ b/softfloat/s_le128.cc
@@ -0,0 +1,13 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+\r
+bool softfloat_le128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )\r
+{\r
+\r
+    return ( a64 < b64 ) || ( ( a64 == b64 ) && ( a0 <= b0 ) );\r
+\r
+}\r
+\r

diff --git a/softfloat/s_lt128.cc b/softfloat/s_lt128.cc
new file mode 100755 (executable)
index 0000000..33a3df4
--- /dev/null
+++ b/softfloat/s_lt128.cc
@@ -0,0 +1,13 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+\r
+bool softfloat_lt128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )\r
+{\r
+\r
+    return ( a64 < b64 ) || ( ( a64 == b64 ) && ( a0 < b0 ) );\r
+\r
+}\r
+\r

diff --git a/softfloat/s_mul128By64To192.cc b/softfloat/s_mul128By64To192.cc
new file mode 100755 (executable)
index 0000000..dfa8825
--- /dev/null
+++ b/softfloat/s_mul128By64To192.cc
@@ -0,0 +1,20 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+\r
+struct uint192\r
+ softfloat_mul128By64To192( uint64_t a64, uint64_t a0, uint64_t b )\r
+{\r
+    struct uint128 p0, p64;\r
+    struct uint192 z;\r
+\r
+    p0 = softfloat_mul64To128( a0, b );\r
+    z.v0 = p0.v0;\r
+    p64 = softfloat_mul64To128( a64, b );\r
+    z.v64 = p64.v0 + p0.v64;\r
+    z.v128 = p64.v64 + ( z.v64 < p64.v0 );\r
+    return z;\r
+\r
+}\r
+\r

diff --git a/softfloat/s_mul128To256.cc b/softfloat/s_mul128To256.cc
new file mode 100755 (executable)
index 0000000..a96cd94
--- /dev/null
+++ b/softfloat/s_mul128To256.cc
@@ -0,0 +1,28 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+\r
+struct uint256\r
+ softfloat_mul128To256( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )\r
+{\r
+    struct uint128 p0, p64, p128;\r
+    struct uint256 z;\r
+\r
+    p0 = softfloat_mul64To128( a0, b0 );\r
+    z.v0 = p0.v0;\r
+    p64 = softfloat_mul64To128( a64, b0 );\r
+    z.v64 = p64.v0 + p0.v64;\r
+    z.v128 = p64.v64 + ( z.v64 < p64.v0 );\r
+    p128 = softfloat_mul64To128( a64, b64 );\r
+    z.v128 += p128.v0;\r
+    z.v192 = p128.v64 + ( z.v128 < p128.v0 );\r
+    p64 = softfloat_mul64To128( a0, b64 );\r
+    z.v64 += p64.v0;\r
+    p64.v64 += ( z.v64 < p64.v0 );\r
+    z.v128 += p64.v64;\r
+    z.v192 += ( z.v128 < p64.v64 );\r
+    return z;\r
+\r
+}\r
+\r

diff --git a/softfloat/s_mul64To128.cc b/softfloat/s_mul64To128.cc
new file mode 100755 (executable)
index 0000000..c17780b
--- /dev/null
+++ b/softfloat/s_mul64To128.cc
@@ -0,0 +1,28 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+\r
+struct uint128 softfloat_mul64To128( uint64_t a, uint64_t b )\r
+{\r
+    uint32_t a32, a0, b32, b0;\r
+    struct uint128 z;\r
+    uint64_t mid1, mid2, mid;\r
+\r
+    a32 = a>>32;\r
+    a0 = a;\r
+    b32 = b>>32;\r
+    b0 = b;\r
+    z.v0 = (uint64_t) a0 * b0;\r
+    mid1 = (uint64_t) a32 * b0;\r
+    mid2 = (uint64_t) a0 * b32;\r
+    z.v64 = (uint64_t) a32 * b32;\r
+    mid = mid1 + mid2;\r
+    z.v64 += ( (uint64_t) ( mid < mid1 ) )<<32 | mid>>32;\r
+    mid <<= 32;\r
+    z.v0 += mid;\r
+    z.v64 += ( z.v0 < mid );\r
+    return z;\r
+\r
+}\r
+\r

diff --git a/softfloat/s_mulAddF32.cc b/softfloat/s_mulAddF32.cc
new file mode 100755 (executable)
index 0000000..e55a0ba
--- /dev/null
+++ b/softfloat/s_mulAddF32.cc
@@ -0,0 +1,171 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+#include "specialize.h"\r
+#include "softfloat.h"\r
+\r
+float32_t\r
+ softfloat_mulAddF32(\r
+     int op, uint_fast32_t uiA, uint_fast32_t uiB, uint_fast32_t uiC )\r
+{\r
+    bool signA;\r
+    int_fast16_t expA;\r
+    uint_fast32_t sigA;\r
+    bool signB;\r
+    int_fast16_t expB;\r
+    uint_fast32_t sigB;\r
+    bool signC;\r
+    int_fast16_t expC;\r
+    uint_fast32_t sigC;\r
+    bool signProd;\r
+    uint_fast32_t magBits, uiZ;\r
+    struct exp16_sig32 normExpSig;\r
+    int_fast16_t expProd;\r
+    uint_fast64_t sigProd;\r
+    bool signZ;\r
+    int_fast16_t expZ;\r
+    uint_fast32_t sigZ;\r
+    int_fast16_t expDiff;\r
+    uint_fast64_t sigZ64, sigC64;\r
+    int shiftCount;\r
+    union ui32_f32 uZ;\r
+\r
+    signA = signF32UI( uiA );\r
+    expA = expF32UI( uiA );\r
+    sigA = fracF32UI( uiA );\r
+    signB = signF32UI( uiB );\r
+    expB = expF32UI( uiB );\r
+    sigB = fracF32UI( uiB );\r
+    signC = signF32UI( uiC ) ^ ( op == softfloat_mulAdd_subC );\r
+    expC = expF32UI( uiC );\r
+    sigC = fracF32UI( uiC );\r
+    signProd = signA ^ signB ^ ( op == softfloat_mulAdd_subProd );\r
+    if ( expA == 0xFF ) {\r
+        if ( sigA || ( ( expB == 0xFF ) && sigB ) ) goto propagateNaN_ABC;\r
+        magBits = expB | sigB;\r
+        goto infProdArg;\r
+    }\r
+    if ( expB == 0xFF ) {\r
+        if ( sigB ) goto propagateNaN_ABC;\r
+        magBits = expA | sigA;\r
+        goto infProdArg;\r
+    }\r
+    if ( expC == 0xFF ) {\r
+        if ( sigC ) {\r
+            uiZ = 0;\r
+            goto propagateNaN_ZC;\r
+        }\r
+        uiZ = uiC;\r
+        goto uiZ;\r
+    }\r
+    if ( ! expA ) {\r
+        if ( ! sigA ) goto zeroProd;\r
+        normExpSig = softfloat_normSubnormalF32Sig( sigA );\r
+        expA = normExpSig.exp;\r
+        sigA = normExpSig.sig;\r
+    }\r
+    if ( ! expB ) {\r
+        if ( ! sigB ) goto zeroProd;\r
+        normExpSig = softfloat_normSubnormalF32Sig( sigB );\r
+        expB = normExpSig.exp;\r
+        sigB = normExpSig.sig;\r
+    }\r
+    expProd = expA + expB - 0x7E;\r
+    sigA = ( sigA | 0x00800000 )<<7;\r
+    sigB = ( sigB | 0x00800000 )<<7;\r
+    sigProd = (uint_fast64_t) sigA * sigB;\r
+    if ( sigProd < UINT64_C( 0x2000000000000000 ) ) {\r
+        --expProd;\r
+        sigProd <<= 1;\r
+    }\r
+    signZ = signProd;\r
+    if ( ! expC ) {\r
+        if ( ! sigC ) {\r
+            expZ = expProd - 1;\r
+            sigZ = softfloat_shortShift64RightJam( sigProd, 31 );\r
+            goto roundPack;\r
+        }\r
+        normExpSig = softfloat_normSubnormalF32Sig( sigC );\r
+        expC = normExpSig.exp;\r
+        sigC = normExpSig.sig;\r
+    }\r
+    sigC = ( sigC | 0x00800000 )<<6;\r
+    expDiff = expProd - expC;\r
+    if ( signProd == signC ) {\r
+        if ( expDiff <= 0 ) {\r
+            expZ = expC;\r
+            sigZ = sigC + softfloat_shift64RightJam( sigProd, 32 - expDiff );\r
+        } else {\r
+            expZ = expProd;\r
+            sigZ64 =\r
+                sigProd\r
+                    + softfloat_shift64RightJam(\r
+                          (uint_fast64_t) sigC<<32, expDiff );\r
+            sigZ = softfloat_shortShift64RightJam( sigZ64, 32 );\r
+        }\r
+        if ( sigZ < 0x40000000 ) {\r
+            --expZ;\r
+            sigZ <<= 1;\r
+        }\r
+    } else {\r
+/*** OPTIMIZE BETTER? ***/\r
+        sigC64 = (uint_fast64_t) sigC<<32;\r
+        if ( expDiff < 0 ) {\r
+            signZ = signC;\r
+            expZ = expC;\r
+            sigZ64 = sigC64 - softfloat_shift64RightJam( sigProd, - expDiff );\r
+        } else if ( ! expDiff ) {\r
+            expZ = expProd;\r
+            sigZ64 = sigProd - sigC64;\r
+            if ( ! sigZ64 ) goto completeCancellation;\r
+            if ( sigZ64 & UINT64_C( 0x8000000000000000 ) ) {\r
+                signZ ^= 1;\r
+                sigZ64 = - sigZ64;\r
+            }\r
+        } else {\r
+            expZ = expProd;\r
+            sigZ64 = sigProd - softfloat_shift64RightJam( sigC64, expDiff );\r
+        }\r
+        shiftCount = softfloat_countLeadingZeros64( sigZ64 ) - 1;\r
+        expZ -= shiftCount;\r
+        shiftCount -= 32;\r
+        if ( shiftCount < 0 ) {\r
+            sigZ = softfloat_shortShift64RightJam( sigZ64, - shiftCount );\r
+        } else {\r
+            sigZ = (uint_fast32_t) sigZ64<<shiftCount;\r
+        }\r
+    }\r
+ roundPack:\r
+    return softfloat_roundPackToF32( signZ, expZ, sigZ );\r
+ propagateNaN_ABC:\r
+    uiZ = softfloat_propagateNaNF32UI( uiA, uiB );\r
+    goto propagateNaN_ZC;\r
+ infProdArg:\r
+    if ( magBits ) {\r
+        uiZ = packToF32UI( signProd, 0xFF, 0 );\r
+        if ( expC != 0xFF ) goto uiZ;\r
+        if ( sigC ) goto propagateNaN_ZC;\r
+        if ( signProd == signC ) goto uiZ;\r
+    }\r
+ invalid:\r
+    softfloat_raiseFlags( softfloat_flag_invalid );\r
+    uiZ = defaultNaNF32UI;\r
+ propagateNaN_ZC:\r
+    uiZ = softfloat_propagateNaNF32UI( uiZ, uiC );\r
+    goto uiZ;\r
+ zeroProd:\r
+    uiZ = uiC;\r
+    if ( ! ( expC | sigC ) && ( signProd != signC ) ) {\r
+ completeCancellation:\r
+        uiZ =\r
+            packToF32UI( softfloat_roundingMode == softfloat_round_min, 0, 0 );\r
+    }\r
+ uiZ:\r
+    uZ.ui = uiZ;\r
+    return uZ.f;\r
+\r
+}\r
+\r

diff --git a/softfloat/s_mulAddF64.cc b/softfloat/s_mulAddF64.cc
new file mode 100755 (executable)
index 0000000..01ba3b4
--- /dev/null
+++ b/softfloat/s_mulAddF64.cc
@@ -0,0 +1,188 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+#include "specialize.h"\r
+#include "softfloat.h"\r
+\r
+float64_t\r
+ softfloat_mulAddF64(\r
+     int op, uint_fast64_t uiA, uint_fast64_t uiB, uint_fast64_t uiC )\r
+{\r
+    bool signA;\r
+    int_fast16_t expA;\r
+    uint_fast64_t sigA;\r
+    bool signB;\r
+    int_fast16_t expB;\r
+    uint_fast64_t sigB;\r
+    bool signC;\r
+    int_fast16_t expC;\r
+    uint_fast64_t sigC;\r
+    bool signProd;\r
+    uint_fast64_t magBits, uiZ;\r
+    struct exp16_sig64 normExpSig;\r
+    int_fast16_t expProd;\r
+    struct uint128 sigProd;\r
+    bool signZ;\r
+    int_fast16_t expZ;\r
+    uint_fast64_t sigZ;\r
+    int_fast16_t expDiff;\r
+    struct uint128 sigC128, sigZ128;\r
+    int shiftCount;\r
+    union ui64_f64 uZ;\r
+\r
+    signA = signF64UI( uiA );\r
+    expA = expF64UI( uiA );\r
+    sigA = fracF64UI( uiA );\r
+    signB = signF64UI( uiB );\r
+    expB = expF64UI( uiB );\r
+    sigB = fracF64UI( uiB );\r
+    signC = signF64UI( uiC ) ^ ( op == softfloat_mulAdd_subC );\r
+    expC = expF64UI( uiC );\r
+    sigC = fracF64UI( uiC );\r
+    signProd = signA ^ signB ^ ( op == softfloat_mulAdd_subProd );\r
+    if ( expA == 0x7FF ) {\r
+        if ( sigA || ( ( expB == 0x7FF ) && sigB ) ) goto propagateNaN_ABC;\r
+        magBits = expB | sigB;\r
+        goto infProdArg;\r
+    }\r
+    if ( expB == 0x7FF ) {\r
+        if ( sigB ) goto propagateNaN_ABC;\r
+        magBits = expA | sigA;\r
+        goto infProdArg;\r
+    }\r
+    if ( expC == 0x7FF ) {\r
+        if ( sigC ) {\r
+            uiZ = 0;\r
+            goto propagateNaN_ZC;\r
+        }\r
+        uiZ = uiC;\r
+        goto uiZ;\r
+    }\r
+    if ( ! expA ) {\r
+        if ( ! sigA ) goto zeroProd;\r
+        normExpSig = softfloat_normSubnormalF64Sig( sigA );\r
+        expA = normExpSig.exp;\r
+        sigA = normExpSig.sig;\r
+    }\r
+    if ( ! expB ) {\r
+        if ( ! sigB ) goto zeroProd;\r
+        normExpSig = softfloat_normSubnormalF64Sig( sigB );\r
+        expB = normExpSig.exp;\r
+        sigB = normExpSig.sig;\r
+    }\r
+    expProd = expA + expB - 0x3FE;\r
+    sigA = ( sigA | UINT64_C( 0x0010000000000000 ) )<<10;\r
+    sigB = ( sigB | UINT64_C( 0x0010000000000000 ) )<<10;\r
+    sigProd = softfloat_mul64To128( sigA, sigB );\r
+    if ( sigProd.v64 < UINT64_C( 0x2000000000000000 ) ) {\r
+        --expProd;\r
+        sigProd = softfloat_shortShift128Left( sigProd.v64, sigProd.v0, 1 );\r
+    }\r
+    signZ = signProd;\r
+    if ( ! expC ) {\r
+        if ( ! sigC ) {\r
+            expZ = expProd - 1;\r
+            sigZ = sigProd.v64<<1 | ( sigProd.v0 != 0 );\r
+            goto roundPack;\r
+        }\r
+        normExpSig = softfloat_normSubnormalF64Sig( sigC );\r
+        expC = normExpSig.exp;\r
+        sigC = normExpSig.sig;\r
+    }\r
+    sigC = ( sigC | UINT64_C( 0x0010000000000000 ) )<<9;\r
+    expDiff = expProd - expC;\r
+    if ( signProd == signC ) {\r
+        if ( expDiff <= 0 ) {\r
+            expZ = expC;\r
+            if ( expDiff ) {\r
+                sigProd.v64 =\r
+                    softfloat_shift64RightJam( sigProd.v64, - expDiff );\r
+            }\r
+            sigZ = ( sigC + sigProd.v64 ) | ( sigProd.v0 != 0 );\r
+        } else {\r
+            expZ = expProd;\r
+            sigC128 = softfloat_shift128RightJam( sigC, 0, expDiff );\r
+            sigZ128 =\r
+                softfloat_add128(\r
+                    sigProd.v64, sigProd.v0, sigC128.v64, sigC128.v0 );\r
+            sigZ = sigZ128.v64 | ( sigZ128.v0 != 0 );\r
+        }\r
+        if ( sigZ < UINT64_C( 0x4000000000000000 ) ) {\r
+            --expZ;\r
+            sigZ <<= 1;\r
+        }\r
+    } else {\r
+/*** OPTIMIZE BETTER? ***/\r
+        if ( expDiff < 0 ) {\r
+            signZ = signC;\r
+            expZ = expC;\r
+            sigProd =\r
+                softfloat_shift128RightJam(\r
+                    sigProd.v64, sigProd.v0, - expDiff );\r
+            sigZ128 = softfloat_sub128( sigC, 0, sigProd.v64, sigProd.v0 );\r
+        } else if ( ! expDiff ) {\r
+            expZ = expProd;\r
+            sigZ128 = softfloat_sub128( sigProd.v64, sigProd.v0, sigC, 0 );\r
+            if ( ! ( sigZ128.v64 | sigZ128.v0 ) ) goto completeCancellation;\r
+            if ( sigZ128.v64 & UINT64_C( 0x8000000000000000 ) ) {\r
+                signZ ^= 1;\r
+                sigZ128 = softfloat_sub128( 0, 0, sigZ128.v64, sigZ128.v0 );\r
+            }\r
+        } else {\r
+            expZ = expProd;\r
+            sigC128 = softfloat_shift128RightJam( sigC, 0, expDiff );\r
+            sigZ128 =\r
+                softfloat_sub128(\r
+                    sigProd.v64, sigProd.v0, sigC128.v64, sigC128.v0 );\r
+        }\r
+        if ( ! sigZ128.v64 ) {\r
+            expZ -= 64;\r
+            sigZ128.v64 = sigZ128.v0;\r
+            sigZ128.v0 = 0;\r
+        }\r
+        shiftCount = softfloat_countLeadingZeros64( sigZ128.v64 ) - 1;\r
+        expZ -= shiftCount;\r
+        if ( shiftCount < 0 ) {\r
+            sigZ = softfloat_shortShift64RightJam( sigZ128.v64, - shiftCount );\r
+        } else {\r
+            sigZ128 =\r
+                softfloat_shortShift128Left(\r
+                    sigZ128.v64, sigZ128.v0, shiftCount );\r
+            sigZ = sigZ128.v64;\r
+        }\r
+        sigZ |= ( sigZ128.v0 != 0 );\r
+    }\r
+ roundPack:\r
+    return softfloat_roundPackToF64( signZ, expZ, sigZ );\r
+ propagateNaN_ABC:\r
+    uiZ = softfloat_propagateNaNF64UI( uiA, uiB );\r
+    goto propagateNaN_ZC;\r
+ infProdArg:\r
+    if ( magBits ) {\r
+        uiZ = packToF64UI( signProd, 0x7FF, 0 );\r
+        if ( expC != 0x7FF ) goto uiZ;\r
+        if ( sigC ) goto propagateNaN_ZC;\r
+        if ( signProd == signC ) goto uiZ;\r
+    }\r
+ invalid:\r
+    softfloat_raiseFlags( softfloat_flag_invalid );\r
+    uiZ = defaultNaNF64UI;\r
+ propagateNaN_ZC:\r
+    uiZ = softfloat_propagateNaNF64UI( uiZ, uiC );\r
+    goto uiZ;\r
+ zeroProd:\r
+    uiZ = uiC;\r
+    if ( ! ( expC | sigC ) && ( signProd != signC ) ) {\r
+ completeCancellation:\r
+        uiZ =\r
+            packToF64UI( softfloat_roundingMode == softfloat_round_min, 0, 0 );\r
+    }\r
+ uiZ:\r
+    uZ.ui = uiZ;\r
+    return uZ.f;\r
+\r
+}\r
+\r

diff --git a/softfloat/s_normRoundPackToF32.cc b/softfloat/s_normRoundPackToF32.cc
new file mode 100755 (executable)
index 0000000..2e6f4b0
--- /dev/null
+++ b/softfloat/s_normRoundPackToF32.cc
@@ -0,0 +1,24 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+\r
+float32_t\r
+ softfloat_normRoundPackToF32( bool sign, int_fast16_t exp, uint_fast32_t sig )\r
+{\r
+    int shiftCount;\r
+    union ui32_f32 uZ;\r
+\r
+    shiftCount = softfloat_countLeadingZeros32( sig ) - 1;\r
+    exp -= shiftCount;\r
+    if ( ( 7 <= shiftCount ) && ( (uint16_t) exp < 0xFD ) ) {\r
+        uZ.ui = packToF32UI( sign, sig ? exp : 0, sig<<( shiftCount - 7 ) );\r
+        return uZ.f;\r
+    } else {\r
+        return softfloat_roundPackToF32( sign, exp, sig<<shiftCount );\r
+    }\r
+\r
+}\r
+\r

diff --git a/softfloat/s_normRoundPackToF64.cc b/softfloat/s_normRoundPackToF64.cc
new file mode 100755 (executable)
index 0000000..64dced4
--- /dev/null
+++ b/softfloat/s_normRoundPackToF64.cc
@@ -0,0 +1,24 @@
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+\r
+float64_t\r
+ softfloat_normRoundPackToF64( bool sign, int_fast16_t exp, uint_fast64_t sig )\r
+{\r
+    int shiftCount;\r
+    union ui64_f64 uZ;\r
+\r
+    shiftCount = softfloat_countLeadingZeros64( sig ) - 1;\r
+    exp -= shiftCount;\r
+    if ( ( 10 <= shiftCount ) && ( (uint16_t) exp < 0x7FD ) ) {\r
+        uZ.ui = packToF64UI( sign, sig ? exp : 0, sig<<( shiftCount - 10 ) );\r
+        return uZ.f;\r
+    } else {\r
+        return softfloat_roundPackToF64( sign, exp, sig<<shiftCount );\r
+    }\r
+\r
+}\r
+\r

diff --git a/softfloat/s_normSubnormalF32Sig.cc b/softfloat/s_normSubnormalF32Sig.cc
new file mode 100755 (executable)
index 0000000..b98eb86
--- /dev/null
+++ b/softfloat/s_normSubnormalF32Sig.cc
@@ -0,0 +1,18 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+\r
+struct exp16_sig32 softfloat_normSubnormalF32Sig( uint_fast32_t sig )\r
+{\r
+    int shiftCount;\r
+    struct exp16_sig32 z;\r
+\r
+    shiftCount = softfloat_countLeadingZeros32( sig ) - 8;\r
+    z.exp = 1 - shiftCount;\r
+    z.sig = sig<<shiftCount;\r
+    return z;\r
+\r
+}\r
+\r

diff --git a/softfloat/s_normSubnormalF64Sig.cc b/softfloat/s_normSubnormalF64Sig.cc
new file mode 100755 (executable)
index 0000000..45a7c9e
--- /dev/null
+++ b/softfloat/s_normSubnormalF64Sig.cc
@@ -0,0 +1,18 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+\r
+struct exp16_sig64 softfloat_normSubnormalF64Sig( uint_fast64_t sig )\r
+{\r
+    int shiftCount;\r
+    struct exp16_sig64 z;\r
+\r
+    shiftCount = softfloat_countLeadingZeros64( sig ) - 11;\r
+    z.exp = 1 - shiftCount;\r
+    z.sig = sig<<shiftCount;\r
+    return z;\r
+\r
+}\r
+\r

diff --git a/softfloat/s_roundPackToF32.cc b/softfloat/s_roundPackToF32.cc
new file mode 100755 (executable)
index 0000000..11764f1
--- /dev/null
+++ b/softfloat/s_roundPackToF32.cc
@@ -0,0 +1,65 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float32_t
+ softfloat_roundPackToF32( bool sign, int_fast16_t exp, uint_fast32_t sig )
+{
+    int roundingMode;
+    bool roundNearestEven;
+    int roundIncrement, roundBits;
+    bool isTiny;
+    uint_fast32_t uiZ;
+    union ui32_f32 uZ;
+
+    roundingMode = softfloat_roundingMode;
+    roundNearestEven = ( roundingMode == softfloat_round_nearest_even );
+    roundIncrement = 0x40;
+    if (
+           ! roundNearestEven
+        && ( roundingMode != softfloat_round_nearest_maxMag )
+    ) {
+        roundIncrement =
+               ( roundingMode == softfloat_round_minMag )
+            || ( roundingMode
+                     == ( sign ? softfloat_round_max : softfloat_round_min ) )
+                ? 0
+                : 0x7F;
+    }
+    roundBits = sig & 0x7F;
+    if ( 0xFD <= (uint16_t) exp ) {
+        if ( exp < 0 ) {
+            isTiny =
+                   ( softfloat_detectTininess
+                         == softfloat_tininess_beforeRounding )
+                || ( exp < -1 )
+                || ( sig + roundIncrement < 0x80000000 );
+            sig = softfloat_shift32RightJam( sig, - exp );
+            exp = 0;
+            roundBits = sig & 0x7F;
+            if ( isTiny && roundBits ) {
+                softfloat_raiseFlags( softfloat_flag_underflow );
+            }
+        } else if (
+            ( 0xFD < exp ) || ( 0x80000000 <= sig + roundIncrement )
+        ) {
+            softfloat_raiseFlags(
+                softfloat_flag_overflow | softfloat_flag_inexact );
+            uiZ = packToF32UI( sign, 0xFF, 0 ) - ! roundIncrement;
+            goto uiZ;
+        }
+    }
+    if ( roundBits ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+    sig = ( sig + roundIncrement )>>7;
+    sig &= ~ ( ! ( roundBits ^ 0x40 ) & roundNearestEven );
+    uiZ = packToF32UI( sign, sig ? exp : 0, sig );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+

diff --git a/softfloat/s_roundPackToF64.cc b/softfloat/s_roundPackToF64.cc
new file mode 100755 (executable)
index 0000000..fb0ef1d
--- /dev/null
+++ b/softfloat/s_roundPackToF64.cc
@@ -0,0 +1,66 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "internals.h"
+#include "softfloat.h"
+
+float64_t
+ softfloat_roundPackToF64( bool sign, int_fast16_t exp, uint_fast64_t sig )
+{
+    int roundingMode;
+    bool roundNearestEven;
+    int roundIncrement, roundBits;
+    bool isTiny;
+    uint_fast64_t uiZ;
+    union ui64_f64 uZ;
+
+    roundingMode = softfloat_roundingMode;
+    roundNearestEven = ( roundingMode == softfloat_round_nearest_even );
+    roundIncrement = 0x200;
+    if (
+           ! roundNearestEven
+        && ( roundingMode != softfloat_round_nearest_maxMag )
+    ) {
+        roundIncrement =
+               ( roundingMode == softfloat_round_minMag )
+            || ( roundingMode
+                     == ( sign ? softfloat_round_max : softfloat_round_min ) )
+                ? 0
+                : 0x3FF;
+    }
+    roundBits = sig & 0x3FF;
+    if ( 0x7FD <= (uint16_t) exp ) {
+        if ( exp < 0 ) {
+            isTiny =
+                   ( softfloat_detectTininess
+                         == softfloat_tininess_beforeRounding )
+                || ( exp < -1 )
+                || ( sig + roundIncrement < UINT64_C( 0x8000000000000000 ) );
+            sig = softfloat_shift64RightJam( sig, - exp );
+            exp = 0;
+            roundBits = sig & 0x3FF;
+            if ( isTiny && roundBits ) {
+                softfloat_raiseFlags( softfloat_flag_underflow );
+            }
+        } else if (
+            ( 0x7FD < exp )
+                || ( UINT64_C( 0x8000000000000000 ) <= sig + roundIncrement )
+        ) {
+            softfloat_raiseFlags(
+                softfloat_flag_overflow | softfloat_flag_inexact );
+            uiZ = packToF64UI( sign, 0x7FF, 0 ) - ! roundIncrement;
+            goto uiZ;
+        }
+    }
+    if ( roundBits ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+    sig = ( sig + roundIncrement )>>10;
+    sig &= ~ ( ! ( roundBits ^ 0x200 ) & roundNearestEven );
+    uiZ = packToF64UI( sign, sig ? exp : 0, sig );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+

diff --git a/softfloat/s_roundPackToI32.cc b/softfloat/s_roundPackToI32.cc
new file mode 100755 (executable)
index 0000000..1c91497
--- /dev/null
+++ b/softfloat/s_roundPackToI32.cc
@@ -0,0 +1,48 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+int_fast32_t
+ softfloat_roundPackToI32(
+     bool sign, uint_fast64_t sig, int_fast8_t roundingMode, bool exact )
+{
+    bool roundNearestEven;
+    int roundIncrement, roundBits;
+    uint_fast32_t sig32;
+    union { uint32_t ui; int32_t i; } uZ;
+    int_fast32_t z;
+
+    roundNearestEven = ( roundingMode == softfloat_round_nearest_even );
+    roundIncrement = 0x40;
+    if (
+           ! roundNearestEven
+        && ( roundingMode != softfloat_round_nearest_maxMag )
+    ) {
+        roundIncrement =
+               ( roundingMode == softfloat_round_minMag )
+            || ( roundingMode
+                     == ( sign ? softfloat_round_max : softfloat_round_min ) )
+                ? 0
+                : 0x7F;
+    }
+    roundBits = sig & 0x7F;
+    sig += roundIncrement;
+    if ( sig & UINT64_C( 0xFFFFFF8000000000 ) ) goto invalid;
+    sig32 = sig>>7;
+    sig32 &= ~ ( ! ( roundBits ^ 0x40 ) & roundNearestEven );
+    uZ.ui = sign ? - sig32 : sig32;
+    z = uZ.i;
+    if ( z && ( ( z < 0 ) ^ sign ) ) goto invalid;
+    if ( exact && roundBits ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    return z;
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    return sign ? -0x7FFFFFFF - 1 : 0x7FFFFFFF;
+
+}
+

diff --git a/softfloat/s_roundPackToI64.cc b/softfloat/s_roundPackToI64.cc
new file mode 100755 (executable)
index 0000000..b2f5d63
--- /dev/null
+++ b/softfloat/s_roundPackToI64.cc
@@ -0,0 +1,52 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+int_fast64_t
+ softfloat_roundPackToI64(
+     bool sign,
+     uint_fast64_t sig64,
+     uint_fast64_t sig0,
+     int_fast8_t roundingMode,
+     bool exact
+ )
+{
+    bool roundNearestEven, increment;
+    union { uint64_t ui; int64_t i; } uZ;
+    int_fast64_t z;
+
+    roundNearestEven = ( roundingMode == softfloat_round_nearest_even );
+    increment = ( UINT64_C( 0x8000000000000000 ) <= sig0 );
+    if (
+           ! roundNearestEven
+        && ( roundingMode != softfloat_round_nearest_maxMag )
+    ) {
+        increment =
+               ( roundingMode != softfloat_round_minMag )
+            && ( roundingMode
+                     == ( sign ? softfloat_round_min : softfloat_round_max ) )
+            && sig0;
+    }
+    if ( increment ) {
+        ++sig64;
+        if ( ! sig64 ) goto invalid;
+        sig64 &=
+            ~ ( ! ( sig0 & UINT64_C( 0x7FFFFFFFFFFFFFFF ) )
+                    & roundNearestEven );
+    }
+    uZ.ui = sign ? - sig64 : sig64;
+    z = uZ.i;
+    if ( z && ( ( z < 0 ) ^ sign ) ) goto invalid;
+    if ( exact && sig0 ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+    return z;
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    return
+        sign ? - INT64_C( 0x7FFFFFFFFFFFFFFF ) - 1
+            : INT64_C( 0x7FFFFFFFFFFFFFFF );
+
+}
+

diff --git a/softfloat/s_roundPackToUI32.cc b/softfloat/s_roundPackToUI32.cc
new file mode 100755 (executable)
index 0000000..ab44ec7
--- /dev/null
+++ b/softfloat/s_roundPackToUI32.cc
@@ -0,0 +1,44 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+uint_fast32_t
+ softfloat_roundPackToUI32(
+     bool sign, uint_fast64_t sig, int_fast8_t roundingMode, bool exact )
+{
+    bool roundNearestEven;
+    int roundIncrement, roundBits;
+    uint_fast32_t z;
+
+    roundNearestEven = ( roundingMode == softfloat_round_nearest_even );
+    roundIncrement = 0x40;
+    if (
+           ! roundNearestEven
+        && ( roundingMode != softfloat_round_nearest_maxMag )
+    ) {
+        roundIncrement =
+               ( roundingMode == softfloat_round_minMag )
+            || ( roundingMode
+                     == ( sign ? softfloat_round_max : softfloat_round_min ) )
+                ? 0
+                : 0x7F;
+    }
+    roundBits = sig & 0x7F;
+    sig += roundIncrement;
+    if ( sig & UINT64_C( 0xFFFFFF8000000000 ) ) goto invalid;
+    z = sig>>7;
+    z &= ~ ( ! ( roundBits ^ 0x40 ) & roundNearestEven );
+    if ( sign && z ) goto invalid;
+    if ( exact && roundBits ) {
+        softfloat_exceptionFlags |= softfloat_flag_inexact;
+    }
+    return z;
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    return 0xFFFFFFFF;
+
+}
+

diff --git a/softfloat/s_roundPackToUI64.cc b/softfloat/s_roundPackToUI64.cc
new file mode 100755 (executable)
index 0000000..d42266f
--- /dev/null
+++ b/softfloat/s_roundPackToUI64.cc
@@ -0,0 +1,46 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "softfloat.h"
+
+uint_fast64_t
+ softfloat_roundPackToUI64(
+     bool sign,
+     uint_fast64_t sig64,
+     uint_fast64_t sig0,
+     int_fast8_t roundingMode,
+     bool exact
+ )
+{
+    bool roundNearestEven, increment;
+
+    roundNearestEven = ( roundingMode == softfloat_round_nearest_even );
+    increment = ( UINT64_C( 0x8000000000000000 ) <= sig0 );
+    if (
+           ! roundNearestEven
+        && ( roundingMode != softfloat_round_nearest_maxMag )
+    ) {
+        increment =
+               ( roundingMode != softfloat_round_minMag )
+            && ( roundingMode
+                     == ( sign ? softfloat_round_min : softfloat_round_max ) )
+            && sig0;
+    }
+    if ( increment ) {
+        ++sig64;
+        if ( ! sig64 ) goto invalid;
+        sig64 &=
+            ~ ( ! ( sig0 & UINT64_C( 0x7FFFFFFFFFFFFFFF ) )
+                    & roundNearestEven );
+    }
+    if ( sign && sig64 ) goto invalid;
+    if ( exact && sig0 ) softfloat_exceptionFlags |= softfloat_flag_inexact;
+    return sig64;
+ invalid:
+    softfloat_raiseFlags( softfloat_flag_invalid );
+    return UINT64_C( 0xFFFFFFFFFFFFFFFF );
+
+}
+

diff --git a/softfloat/s_shift128ExtraRightJam.cc b/softfloat/s_shift128ExtraRightJam.cc
new file mode 100755 (executable)
index 0000000..6c57974
--- /dev/null
+++ b/softfloat/s_shift128ExtraRightJam.cc
@@ -0,0 +1,38 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+\r
+struct uint128_extra\r
+ softfloat_shift128ExtraRightJam(\r
+     uint64_t a64, uint64_t a0, uint64_t extra, unsigned int count )\r
+{\r
+    unsigned int negCount;\r
+    struct uint128_extra z;\r
+\r
+    negCount = - count;\r
+    if ( count < 64 ) {\r
+        z.v64 = a64>>count;\r
+        z.v0 = a64<<( negCount & 63 ) | a0>>count;\r
+        z.extra = a0<<( negCount & 63 );\r
+    } else {\r
+        z.v64 = 0;\r
+        if ( count == 64 ) {\r
+            z.v0 = a64;\r
+            z.extra = a0;\r
+        } else {\r
+            extra |= a0;\r
+            if ( count < 128 ) {\r
+                z.v0 = a64>>( count & 63 );\r
+                z.extra = a64<<( negCount & 63 );\r
+            } else {\r
+                z.v0 = 0;\r
+                z.extra = ( count == 128 ) ? a64 : ( a64 != 0 );\r
+            }\r
+        }\r
+    }\r
+    z.extra |= ( extra != 0 );\r
+    return z;\r
+\r
+}\r
+\r

diff --git a/softfloat/s_shift128RightJam.cc b/softfloat/s_shift128RightJam.cc
new file mode 100755 (executable)
index 0000000..5a4e188
--- /dev/null
+++ b/softfloat/s_shift128RightJam.cc
@@ -0,0 +1,31 @@
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+
+struct uint128
+ softfloat_shift128RightJam( uint64_t a64, uint64_t a0, unsigned int count )
+{
+    unsigned int negCount;
+    struct uint128 z;
+
+    if ( count < 64 ) {
+        negCount = - count;
+        z.v64 = a64>>( count & 63 );
+        z.v0 =
+            a64<<( negCount & 63 ) | a0>>count
+                | ( (uint64_t) ( a0<<( negCount & 63 ) ) != 0 );
+    } else {
+        z.v64 = 0;
+        z.v0 =
+            ( count < 128 )
+                ? a64>>( count & 63 )
+                      | ( ( ( a64 & ( ( (uint64_t) 1<<( count & 63 ) ) - 1 ) )
+                                | a0 )
+                              != 0 )
+                : ( ( a64 | a0 ) != 0 );
+    }
+    return z;
+
+}
+

diff --git a/softfloat/s_shift32RightJam.cc b/softfloat/s_shift32RightJam.cc
new file mode 100755 (executable)
index 0000000..b697a34
--- /dev/null
+++ b/softfloat/s_shift32RightJam.cc
@@ -0,0 +1,15 @@
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+
+uint32_t softfloat_shift32RightJam( uint32_t a, unsigned int count )
+{
+
+    return
+        ( count < 32 )
+            ? a>>count | ( (uint32_t) ( a<<( ( - count ) & 31 ) ) != 0 )
+            : ( a != 0 );
+
+}
+

diff --git a/softfloat/s_shift64ExtraRightJam.cc b/softfloat/s_shift64ExtraRightJam.cc
new file mode 100755 (executable)
index 0000000..167ea54
--- /dev/null
+++ b/softfloat/s_shift64ExtraRightJam.cc
@@ -0,0 +1,23 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+\r
+struct uint64_extra\r
+ softfloat_shift64ExtraRightJam(\r
+     uint64_t a, uint64_t extra, unsigned int count )\r
+{\r
+    struct uint64_extra z;\r
+\r
+    if ( count < 64 ) {\r
+        z.v = a>>count;\r
+        z.extra = a<<( ( - count ) & 63 );\r
+    } else {\r
+        z.v = 0;\r
+        z.extra = ( count == 64 ) ? a : ( a != 0 );\r
+    }\r
+    z.extra |= ( extra != 0 );\r
+    return z;\r
+\r
+}\r
+\r

diff --git a/softfloat/s_shift64RightJam.cc b/softfloat/s_shift64RightJam.cc
new file mode 100755 (executable)
index 0000000..ebebb61
--- /dev/null
+++ b/softfloat/s_shift64RightJam.cc
@@ -0,0 +1,15 @@
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+
+uint64_t softfloat_shift64RightJam( uint64_t a, unsigned int count )
+{
+
+    return
+        ( count < 64 )
+            ? a>>count | ( (uint64_t) ( a<<( ( - count ) & 63 ) ) != 0 )
+            : ( a != 0 );
+
+}
+

diff --git a/softfloat/s_shortShift128ExtraRightJam.cc b/softfloat/s_shortShift128ExtraRightJam.cc
new file mode 100755 (executable)
index 0000000..c772740
--- /dev/null
+++ b/softfloat/s_shortShift128ExtraRightJam.cc
@@ -0,0 +1,20 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+\r
+struct uint128_extra\r
+ softfloat_shortShift128ExtraRightJam(\r
+     uint64_t a64, uint64_t a0, uint64_t extra, unsigned int count )\r
+{\r
+    unsigned int negCount;\r
+    struct uint128_extra z;\r
+\r
+    negCount = - count;\r
+    z.v64 = a64>>count;\r
+    z.v0 = a64<<( negCount & 63 ) | a0>>count;\r
+    z.extra = a0<<( negCount & 63 ) | ( extra != 0 );\r
+    return z;\r
+\r
+}\r
+\r

diff --git a/softfloat/s_shortShift128Left.cc b/softfloat/s_shortShift128Left.cc
new file mode 100755 (executable)
index 0000000..9c29988
--- /dev/null
+++ b/softfloat/s_shortShift128Left.cc
@@ -0,0 +1,16 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+\r
+struct uint128\r
+ softfloat_shortShift128Left( uint64_t a64, uint64_t a0, unsigned int count )\r
+{\r
+    struct uint128 z;\r
+\r
+    z.v64 = a64<<count | a0>>( ( - count ) & 63 );\r
+    z.v0 = a0<<count;\r
+    return z;\r
+\r
+}\r
+\r

diff --git a/softfloat/s_shortShift128Right.cc b/softfloat/s_shortShift128Right.cc
new file mode 100755 (executable)
index 0000000..f7f4ce8
--- /dev/null
+++ b/softfloat/s_shortShift128Right.cc
@@ -0,0 +1,16 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+\r
+struct uint128\r
+ softfloat_shortShift128Right( uint64_t a64, uint64_t a0, unsigned int count )\r
+{\r
+    struct uint128 z;\r
+\r
+    z.v64 = a64>>count;\r
+    z.v0 = a64<<( ( - count ) & 63 ) | a0>>count;\r
+    return z;\r
+\r
+}\r
+\r

diff --git a/softfloat/s_shortShift192Left.cc b/softfloat/s_shortShift192Left.cc
new file mode 100755 (executable)
index 0000000..cf1e55d
--- /dev/null
+++ b/softfloat/s_shortShift192Left.cc
@@ -0,0 +1,20 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+\r
+struct uint192\r
+ softfloat_shortShift192Left(\r
+     uint64_t a128, uint64_t a64, uint64_t a0, unsigned int count )\r
+{\r
+    unsigned int negCount;\r
+    struct uint192 z;\r
+\r
+    negCount = - count;\r
+    z.v128 = a128<<count | a64>>( negCount & 63 );\r
+    z.v64 = a64<<count | a0>>( negCount & 63 );\r
+    z.v0 = a0<<count;\r
+    return z;\r
+\r
+}\r
+\r

diff --git a/softfloat/s_shortShift32Right1Jam.cc b/softfloat/s_shortShift32Right1Jam.cc
new file mode 100755 (executable)
index 0000000..db4c304
--- /dev/null
+++ b/softfloat/s_shortShift32Right1Jam.cc
@@ -0,0 +1,12 @@
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+
+uint32_t softfloat_shortShift32Right1Jam( uint32_t a )
+{
+
+    return a>>1 | ( a & 1 );
+
+}
+

diff --git a/softfloat/s_shortShift64ExtraRightJam.cc b/softfloat/s_shortShift64ExtraRightJam.cc
new file mode 100755 (executable)
index 0000000..b861c67
--- /dev/null
+++ b/softfloat/s_shortShift64ExtraRightJam.cc
@@ -0,0 +1,17 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+\r
+struct uint64_extra\r
+ softfloat_shortShift64ExtraRightJam(\r
+     uint64_t a, uint64_t extra, unsigned int count )\r
+{\r
+    struct uint64_extra z;\r
+\r
+    z.v = a>>count;\r
+    z.extra = a<<( ( - count ) & 63 ) | ( extra != 0 );\r
+    return z;\r
+\r
+}\r
+\r

diff --git a/softfloat/s_shortShift64RightJam.cc b/softfloat/s_shortShift64RightJam.cc
new file mode 100755 (executable)
index 0000000..0da6c93
--- /dev/null
+++ b/softfloat/s_shortShift64RightJam.cc
@@ -0,0 +1,12 @@
+
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+
+uint64_t softfloat_shortShift64RightJam( uint64_t a, unsigned int count )
+{
+
+    return a>>count | ( ( a & ( ( (uint64_t) 1<<count ) - 1 ) ) != 0 );
+
+}
+

diff --git a/softfloat/s_sub128.cc b/softfloat/s_sub128.cc
new file mode 100755 (executable)
index 0000000..0c4f181
--- /dev/null
+++ b/softfloat/s_sub128.cc
@@ -0,0 +1,17 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+\r
+struct uint128\r
+ softfloat_sub128( uint64_t a64, uint64_t a0, uint64_t b64, uint64_t b0 )\r
+{\r
+    struct uint128 z;\r
+\r
+    z.v0 = a0 - b0;\r
+    z.v64 = a64 - b64;\r
+    z.v64 -= ( a0 < b0 );\r
+    return z;\r
+\r
+}\r
+\r

diff --git a/softfloat/s_sub192.cc b/softfloat/s_sub192.cc
new file mode 100755 (executable)
index 0000000..96f21c9
--- /dev/null
+++ b/softfloat/s_sub192.cc
@@ -0,0 +1,30 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+\r
+struct uint192\r
+ softfloat_sub192(\r
+     uint64_t a128,\r
+     uint64_t a64,\r
+     uint64_t a0,\r
+     uint64_t b128,\r
+     uint64_t b64,\r
+     uint64_t b0\r
+ )\r
+{\r
+    struct uint192 z;\r
+    unsigned int borrow64, borrow128;\r
+\r
+    z.v0 = a0 - b0;\r
+    borrow64 = ( a0 < b0 );\r
+    z.v64 = a64 - b64;\r
+    borrow128 = ( a64 < b64 );\r
+    z.v128 = a128 - b128;\r
+    borrow128 += ( z.v64 < borrow64 );\r
+    z.v64 -= borrow64;\r
+    z.v128 -= borrow128;\r
+    return z;\r
+\r
+}\r
+\r

diff --git a/softfloat/s_subMagsF32.cc b/softfloat/s_subMagsF32.cc
new file mode 100755 (executable)
index 0000000..0c83b02
--- /dev/null
+++ b/softfloat/s_subMagsF32.cc
@@ -0,0 +1,81 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float32_t
+ softfloat_subMagsF32( uint_fast32_t uiA, uint_fast32_t uiB, bool signZ )
+{
+    int_fast16_t expA;
+    uint_fast32_t sigA;
+    int_fast16_t expB;
+    uint_fast32_t sigB;
+    int_fast16_t expDiff;
+    uint_fast32_t uiZ;
+    int_fast16_t expZ;
+    uint_fast32_t sigZ;
+    union ui32_f32 uZ;
+
+    expA = expF32UI( uiA );
+    sigA = fracF32UI( uiA );
+    expB = expF32UI( uiB );
+    sigB = fracF32UI( uiB );
+    expDiff = expA - expB;
+    sigA <<= 7;
+    sigB <<= 7;
+    if ( 0 < expDiff ) goto expABigger;
+    if ( expDiff < 0 ) goto expBBigger;
+    if ( expA == 0xFF ) {
+        if ( sigA | sigB ) goto propagateNaN;
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        uiZ = defaultNaNF32UI;
+        goto uiZ;
+    }
+    if ( ! expA ) {
+        expA = 1;
+        expB = 1;
+    }
+    if ( sigB < sigA ) goto aBigger;
+    if ( sigA < sigB ) goto bBigger;
+    uiZ = packToF32UI( softfloat_roundingMode == softfloat_round_min, 0, 0 );
+    goto uiZ;
+ expBBigger:
+    if ( expB == 0xFF ) {
+        if ( sigB ) goto propagateNaN;
+        uiZ = packToF32UI( signZ ^ 1, 0xFF, 0 );
+        goto uiZ;
+    }
+    sigA += expA ? 0x40000000 : sigA;
+    sigA = softfloat_shift32RightJam( sigA, - expDiff );
+    sigB |= 0x40000000;
+ bBigger:
+    signZ ^= 1;
+    expZ = expB;
+    sigZ = sigB - sigA;
+    goto normRoundPack;
+ expABigger:
+    if ( expA == 0xFF ) {
+        if ( sigA ) goto propagateNaN;
+        uiZ = uiA;
+        goto uiZ;
+    }
+    sigB += expB ? 0x40000000 : sigB;
+    sigB = softfloat_shift32RightJam( sigB, expDiff );
+    sigA |= 0x40000000;
+ aBigger:
+    expZ = expA;
+    sigZ = sigA - sigB;
+ normRoundPack:
+    return softfloat_normRoundPackToF32( signZ, expZ - 1, sigZ );
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF32UI( uiA, uiB );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+

diff --git a/softfloat/s_subMagsF64.cc b/softfloat/s_subMagsF64.cc
new file mode 100755 (executable)
index 0000000..45b81ba
--- /dev/null
+++ b/softfloat/s_subMagsF64.cc
@@ -0,0 +1,81 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "primitives.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+float64_t
+ softfloat_subMagsF64( uint_fast64_t uiA, uint_fast64_t uiB, bool signZ )
+{
+    int_fast16_t expA;
+    uint_fast64_t sigA;
+    int_fast16_t expB;
+    uint_fast64_t sigB;
+    int_fast16_t expDiff;
+    uint_fast64_t uiZ;
+    int_fast16_t expZ;
+    uint_fast64_t sigZ;
+    union ui64_f64 uZ;
+
+    expA = expF64UI( uiA );
+    sigA = fracF64UI( uiA );
+    expB = expF64UI( uiB );
+    sigB = fracF64UI( uiB );
+    expDiff = expA - expB;
+    sigA <<= 10;
+    sigB <<= 10;
+    if ( 0 < expDiff ) goto expABigger;
+    if ( expDiff < 0 ) goto expBBigger;
+    if ( expA == 0x7FF ) {
+        if ( sigA | sigB ) goto propagateNaN;
+        softfloat_raiseFlags( softfloat_flag_invalid );
+        uiZ = defaultNaNF64UI;
+        goto uiZ;
+    }
+    if ( ! expA ) {
+        expA = 1;
+        expB = 1;
+    }
+    if ( sigB < sigA ) goto aBigger;
+    if ( sigA < sigB ) goto bBigger;
+    uiZ = packToF64UI( softfloat_roundingMode == softfloat_round_min, 0, 0 );
+    goto uiZ;
+ expBBigger:
+    if ( expB == 0x7FF ) {
+        if ( sigB ) goto propagateNaN;
+        uiZ = packToF64UI( signZ ^ 1, 0x7FF, 0 );
+        goto uiZ;
+    }
+    sigA += expA ? UINT64_C( 0x4000000000000000 ) : sigA;
+    sigA = softfloat_shift64RightJam( sigA, - expDiff );
+    sigB |= UINT64_C( 0x4000000000000000 );
+ bBigger:
+    signZ ^= 1;
+    expZ = expB;
+    sigZ = sigB - sigA;
+    goto normRoundPack;
+ expABigger:
+    if ( expA == 0x7FF ) {
+        if ( sigA ) goto propagateNaN;
+        uiZ = uiA;
+        goto uiZ;
+    }
+    sigB += expB ? UINT64_C( 0x4000000000000000 ) : sigB;
+    sigB = softfloat_shift64RightJam( sigB, expDiff );
+    sigA |= UINT64_C( 0x4000000000000000 );
+ aBigger:
+    expZ = expA;
+    sigZ = sigA - sigB;
+ normRoundPack:
+    return softfloat_normRoundPackToF64( signZ, expZ - 1, sigZ );
+ propagateNaN:
+    uiZ = softfloat_propagateNaNF64UI( uiA, uiB );
+ uiZ:
+    uZ.ui = uiZ;
+    return uZ.f;
+
+}
+

diff --git a/softfloat/softfloat-header b/softfloat/softfloat-header
deleted file mode 100644 (file)
index eb5303a..0000000
--- a/softfloat/softfloat-header
+++ /dev/null
@@ -1,259 +0,0 @@
-
-/*============================================================================
-
-This C header file is part of the SoftFloat IEC/IEEE Floating-point Arithmetic
-Package, Release 2b.
-
-Written by John R. Hauser.  This work was made possible in part by the
-International Computer Science Institute, located at Suite 600, 1947 Center
-Street, Berkeley, California 94704.  Funding was partially provided by the
-National Science Foundation under grant MIP-9311980.  The original version
-of this code was written as part of a project to build a fixed-point vector
-processor in collaboration with the University of California at Berkeley,
-overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
-is available through the Web page `http://www.cs.berkeley.edu/~jhauser/
-arithmetic/SoftFloat.html'.
-
-THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has
-been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
-RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
-AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
-COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
-EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
-INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR
-OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
-
-Derivative works are acceptable, even for commercial purposes, so long as
-(1) the source code for the derivative work includes prominent notice that
-the work is derivative, and (2) the source code includes prominent notice with
-these four paragraphs for those parts of this code that are retained.
-
-=============================================================================*/
-
-/*----------------------------------------------------------------------------
-| The macro `FLOATX80' must be defined to enable the extended double-precision
-| floating-point format `floatx80'.  If this macro is not defined, the
-| `floatx80' type will not be defined, and none of the functions that either
-| input or output the `floatx80' type will be defined.  The same applies to
-| the `FLOAT128' macro and the quadruple-precision format `float128'.
-*----------------------------------------------------------------------------*/
-#define FLOATX80
-#define FLOAT128
-
-/*----------------------------------------------------------------------------
-| Software IEC/IEEE floating-point types.
-*----------------------------------------------------------------------------*/
-typedef unsigned int float32;
-typedef unsigned long long float64;
-#ifdef FLOATX80
-typedef struct {
-    unsigned short high;
-    unsigned long long low;
-} floatx80;
-#endif
-#ifdef FLOAT128
-typedef struct {
-    unsigned long long high, low;
-} float128;
-#endif
-
-/*----------------------------------------------------------------------------
-| Software IEC/IEEE floating-point underflow tininess-detection mode.
-*----------------------------------------------------------------------------*/
-extern int float_detect_tininess;
-enum {
-    float_tininess_after_rounding  = 0,
-    float_tininess_before_rounding = 1
-};
-
-/*----------------------------------------------------------------------------
-| Software IEC/IEEE floating-point rounding mode.
-*----------------------------------------------------------------------------*/
-extern int float_rounding_mode;
-enum {
-    float_round_nearest_even = 0,
-    float_round_to_zero      = 1,
-    float_round_up           = 2,
-    float_round_down         = 3
-};
-
-/*----------------------------------------------------------------------------
-| Software IEC/IEEE floating-point exception flags.
-*----------------------------------------------------------------------------*/
-extern int float_exception_flags;
-enum {
-    float_flag_inexact   =  1,
-    float_flag_divbyzero =  2,
-    float_flag_underflow =  4,
-    float_flag_overflow  =  8,
-    float_flag_invalid   = 16
-};
-
-/*----------------------------------------------------------------------------
-| Routine to raise any or all of the software IEC/IEEE floating-point
-| exception flags.
-*----------------------------------------------------------------------------*/
-void float_raise( int );
-
-/*----------------------------------------------------------------------------
-| Software IEC/IEEE integer-to-floating-point conversion routines.
-*----------------------------------------------------------------------------*/
-float32 int32_to_float32( int );
-float64 int32_to_float64( int );
-#ifdef FLOATX80
-floatx80 int32_to_floatx80( int );
-#endif
-#ifdef FLOAT128
-float128 int32_to_float128( int );
-#endif
-float32 int64_to_float32( long long );
-float64 int64_to_float64( long long );
-#ifdef FLOATX80
-floatx80 int64_to_floatx80( long long );
-#endif
-#ifdef FLOAT128
-float128 int64_to_float128( long long );
-#endif
-
-/*----------------------------------------------------------------------------
-| Software IEC/IEEE single-precision conversion routines.
-*----------------------------------------------------------------------------*/
-int float32_to_int32( float32 );
-int float32_to_int32_round_to_zero( float32 );
-long long float32_to_int64( float32 );
-long long float32_to_int64_round_to_zero( float32 );
-float64 float32_to_float64( float32 );
-#ifdef FLOATX80
-floatx80 float32_to_floatx80( float32 );
-#endif
-#ifdef FLOAT128
-float128 float32_to_float128( float32 );
-#endif
-
-/*----------------------------------------------------------------------------
-| Software IEC/IEEE single-precision operations.
-*----------------------------------------------------------------------------*/
-float32 float32_round_to_int( float32 );
-float32 float32_add( float32, float32 );
-float32 float32_sub( float32, float32 );
-float32 float32_mul( float32, float32 );
-float32 float32_div( float32, float32 );
-float32 float32_rem( float32, float32 );
-float32 float32_sqrt( float32 );
-int float32_eq( float32, float32 );
-int float32_le( float32, float32 );
-int float32_lt( float32, float32 );
-int float32_eq_signaling( float32, float32 );
-int float32_le_quiet( float32, float32 );
-int float32_lt_quiet( float32, float32 );
-int float32_is_signaling_nan( float32 );
-
-/*----------------------------------------------------------------------------
-| Software IEC/IEEE double-precision conversion routines.
-*----------------------------------------------------------------------------*/
-int float64_to_int32( float64 );
-int float64_to_int32_round_to_zero( float64 );
-long long float64_to_int64( float64 );
-long long float64_to_int64_round_to_zero( float64 );
-float32 float64_to_float32( float64 );
-#ifdef FLOATX80
-floatx80 float64_to_floatx80( float64 );
-#endif
-#ifdef FLOAT128
-float128 float64_to_float128( float64 );
-#endif
-
-/*----------------------------------------------------------------------------
-| Software IEC/IEEE double-precision operations.
-*----------------------------------------------------------------------------*/
-float64 float64_round_to_int( float64 );
-float64 float64_add( float64, float64 );
-float64 float64_sub( float64, float64 );
-float64 float64_mul( float64, float64 );
-float64 float64_div( float64, float64 );
-float64 float64_rem( float64, float64 );
-float64 float64_sqrt( float64 );
-int float64_eq( float64, float64 );
-int float64_le( float64, float64 );
-int float64_lt( float64, float64 );
-int float64_eq_signaling( float64, float64 );
-int float64_le_quiet( float64, float64 );
-int float64_lt_quiet( float64, float64 );
-int float64_is_signaling_nan( float64 );
-
-#ifdef FLOATX80
-
-/*----------------------------------------------------------------------------
-| Software IEC/IEEE extended double-precision conversion routines.
-*----------------------------------------------------------------------------*/
-int floatx80_to_int32( floatx80 );
-int floatx80_to_int32_round_to_zero( floatx80 );
-long long floatx80_to_int64( floatx80 );
-long long floatx80_to_int64_round_to_zero( floatx80 );
-float32 floatx80_to_float32( floatx80 );
-float64 floatx80_to_float64( floatx80 );
-#ifdef FLOAT128
-float128 floatx80_to_float128( floatx80 );
-#endif
-
-/*----------------------------------------------------------------------------
-| Software IEC/IEEE extended double-precision rounding precision.  Valid
-| values are 32, 64, and 80.
-*----------------------------------------------------------------------------*/
-extern int floatx80_rounding_precision;
-
-/*----------------------------------------------------------------------------
-| Software IEC/IEEE extended double-precision operations.
-*----------------------------------------------------------------------------*/
-floatx80 floatx80_round_to_int( floatx80 );
-floatx80 floatx80_add( floatx80, floatx80 );
-floatx80 floatx80_sub( floatx80, floatx80 );
-floatx80 floatx80_mul( floatx80, floatx80 );
-floatx80 floatx80_div( floatx80, floatx80 );
-floatx80 floatx80_rem( floatx80, floatx80 );
-floatx80 floatx80_sqrt( floatx80 );
-int floatx80_eq( floatx80, floatx80 );
-int floatx80_le( floatx80, floatx80 );
-int floatx80_lt( floatx80, floatx80 );
-int floatx80_eq_signaling( floatx80, floatx80 );
-int floatx80_le_quiet( floatx80, floatx80 );
-int floatx80_lt_quiet( floatx80, floatx80 );
-int floatx80_is_signaling_nan( floatx80 );
-
-#endif
-
-#ifdef FLOAT128
-
-/*----------------------------------------------------------------------------
-| Software IEC/IEEE quadruple-precision conversion routines.
-*----------------------------------------------------------------------------*/
-int float128_to_int32( float128 );
-int float128_to_int32_round_to_zero( float128 );
-long long float128_to_int64( float128 );
-long long float128_to_int64_round_to_zero( float128 );
-float32 float128_to_float32( float128 );
-float64 float128_to_float64( float128 );
-#ifdef FLOATX80
-floatx80 float128_to_floatx80( float128 );
-#endif
-
-/*----------------------------------------------------------------------------
-| Software IEC/IEEE quadruple-precision operations.
-*----------------------------------------------------------------------------*/
-float128 float128_round_to_int( float128 );
-float128 float128_add( float128, float128 );
-float128 float128_sub( float128, float128 );
-float128 float128_mul( float128, float128 );
-float128 float128_div( float128, float128 );
-float128 float128_rem( float128, float128 );
-float128 float128_sqrt( float128 );
-int float128_eq( float128, float128 );
-int float128_le( float128, float128 );
-int float128_lt( float128, float128 );
-int float128_eq_signaling( float128, float128 );
-int float128_le_quiet( float128, float128 );
-int float128_lt_quiet( float128, float128 );
-int float128_is_signaling_nan( float128 );
-
-#endif
-

diff --git a/softfloat/softfloat-macros b/softfloat/softfloat-macros
deleted file mode 100644 (file)
index d289328..0000000
--- a/softfloat/softfloat-macros
+++ /dev/null
@@ -1,720 +0,0 @@
-\r
-/*============================================================================\r
-\r
-This C source fragment is part of the SoftFloat IEC/IEEE Floating-point\r
-Arithmetic Package, Release 2b.\r
-\r
-Written by John R. Hauser.  This work was made possible in part by the\r
-International Computer Science Institute, located at Suite 600, 1947 Center\r
-Street, Berkeley, California 94704.  Funding was partially provided by the\r
-National Science Foundation under grant MIP-9311980.  The original version\r
-of this code was written as part of a project to build a fixed-point vector\r
-processor in collaboration with the University of California at Berkeley,\r
-overseen by Profs. Nelson Morgan and John Wawrzynek.  More information\r
-is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
-arithmetic/SoftFloat.html'.\r
-\r
-THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has\r
-been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
-RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
-AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
-COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
-EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
-INSTITUTE (possibly via similar legal notice) AGAINST ALL LOSSES, COSTS, OR\r
-OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
-\r
-Derivative works are acceptable, even for commercial purposes, so long as\r
-(1) the source code for the derivative work includes prominent notice that\r
-the work is derivative, and (2) the source code includes prominent notice with\r
-these four paragraphs for those parts of this code that are retained.\r
-\r
-=============================================================================*/\r
-\r
-/*----------------------------------------------------------------------------\r
-| Shifts `a' right by the number of bits given in `count'.  If any nonzero\r
-| bits are shifted off, they are ``jammed'' into the least significant bit of\r
-| the result by setting the least significant bit to 1.  The value of `count'\r
-| can be arbitrarily large; in particular, if `count' is greater than 32, the\r
-| result will be either 0 or 1, depending on whether `a' is zero or nonzero.\r
-| The result is stored in the location pointed to by `zPtr'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE void shift32RightJamming( bits32 a, int16 count, bits32 *zPtr )\r
-{\r
-    bits32 z;\r
-\r
-    if ( count == 0 ) {\r
-        z = a;\r
-    }\r
-    else if ( count < 32 ) {\r
-        z = ( a>>count ) | ( ( a<<( ( - count ) & 31 ) ) != 0 );\r
-    }\r
-    else {\r
-        z = ( a != 0 );\r
-    }\r
-    *zPtr = z;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Shifts `a' right by the number of bits given in `count'.  If any nonzero\r
-| bits are shifted off, they are ``jammed'' into the least significant bit of\r
-| the result by setting the least significant bit to 1.  The value of `count'\r
-| can be arbitrarily large; in particular, if `count' is greater than 64, the\r
-| result will be either 0 or 1, depending on whether `a' is zero or nonzero.\r
-| The result is stored in the location pointed to by `zPtr'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE void shift64RightJamming( bits64 a, int16 count, bits64 *zPtr )\r
-{\r
-    bits64 z;\r
-\r
-    if ( count == 0 ) {\r
-        z = a;\r
-    }\r
-    else if ( count < 64 ) {\r
-        z = ( a>>count ) | ( ( a<<( ( - count ) & 63 ) ) != 0 );\r
-    }\r
-    else {\r
-        z = ( a != 0 );\r
-    }\r
-    *zPtr = z;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Shifts the 128-bit value formed by concatenating `a0' and `a1' right by 64\r
-| _plus_ the number of bits given in `count'.  The shifted result is at most\r
-| 64 nonzero bits; this is stored at the location pointed to by `z0Ptr'.  The\r
-| bits shifted off form a second 64-bit result as follows:  The _last_ bit\r
-| shifted off is the most-significant bit of the extra result, and the other\r
-| 63 bits of the extra result are all zero if and only if _all_but_the_last_\r
-| bits shifted off were all zero.  This extra result is stored in the location\r
-| pointed to by `z1Ptr'.  The value of `count' can be arbitrarily large.\r
-|     (This routine makes more sense if `a0' and `a1' are considered to form\r
-| a fixed-point value with binary point between `a0' and `a1'.  This fixed-\r
-| point value is shifted right by the number of bits given in `count', and\r
-| the integer part of the result is returned at the location pointed to by\r
-| `z0Ptr'.  The fractional part of the result may be slightly corrupted as\r
-| described above, and is returned at the location pointed to by `z1Ptr'.)\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE void\r
- shift64ExtraRightJamming(\r
-     bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )\r
-{\r
-    bits64 z0, z1;\r
-    int8 negCount = ( - count ) & 63;\r
-\r
-    if ( count == 0 ) {\r
-        z1 = a1;\r
-        z0 = a0;\r
-    }\r
-    else if ( count < 64 ) {\r
-        z1 = ( a0<<negCount ) | ( a1 != 0 );\r
-        z0 = a0>>count;\r
-    }\r
-    else {\r
-        if ( count == 64 ) {\r
-            z1 = a0 | ( a1 != 0 );\r
-        }\r
-        else {\r
-            z1 = ( ( a0 | a1 ) != 0 );\r
-        }\r
-        z0 = 0;\r
-    }\r
-    *z1Ptr = z1;\r
-    *z0Ptr = z0;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Shifts the 128-bit value formed by concatenating `a0' and `a1' right by the\r
-| number of bits given in `count'.  Any bits shifted off are lost.  The value\r
-| of `count' can be arbitrarily large; in particular, if `count' is greater\r
-| than 128, the result will be 0.  The result is broken into two 64-bit pieces\r
-| which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE void\r
- shift128Right(\r
-     bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )\r
-{\r
-    bits64 z0, z1;\r
-    int8 negCount = ( - count ) & 63;\r
-\r
-    if ( count == 0 ) {\r
-        z1 = a1;\r
-        z0 = a0;\r
-    }\r
-    else if ( count < 64 ) {\r
-        z1 = ( a0<<negCount ) | ( a1>>count );\r
-        z0 = a0>>count;\r
-    }\r
-    else {\r
-        z1 = ( count < 64 ) ? ( a0>>( count & 63 ) ) : 0;\r
-        z0 = 0;\r
-    }\r
-    *z1Ptr = z1;\r
-    *z0Ptr = z0;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Shifts the 128-bit value formed by concatenating `a0' and `a1' right by the\r
-| number of bits given in `count'.  If any nonzero bits are shifted off, they\r
-| are ``jammed'' into the least significant bit of the result by setting the\r
-| least significant bit to 1.  The value of `count' can be arbitrarily large;\r
-| in particular, if `count' is greater than 128, the result will be either\r
-| 0 or 1, depending on whether the concatenation of `a0' and `a1' is zero or\r
-| nonzero.  The result is broken into two 64-bit pieces which are stored at\r
-| the locations pointed to by `z0Ptr' and `z1Ptr'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE void\r
- shift128RightJamming(\r
-     bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )\r
-{\r
-    bits64 z0, z1;\r
-    int8 negCount = ( - count ) & 63;\r
-\r
-    if ( count == 0 ) {\r
-        z1 = a1;\r
-        z0 = a0;\r
-    }\r
-    else if ( count < 64 ) {\r
-        z1 = ( a0<<negCount ) | ( a1>>count ) | ( ( a1<<negCount ) != 0 );\r
-        z0 = a0>>count;\r
-    }\r
-    else {\r
-        if ( count == 64 ) {\r
-            z1 = a0 | ( a1 != 0 );\r
-        }\r
-        else if ( count < 128 ) {\r
-            z1 = ( a0>>( count & 63 ) ) | ( ( ( a0<<negCount ) | a1 ) != 0 );\r
-        }\r
-        else {\r
-            z1 = ( ( a0 | a1 ) != 0 );\r
-        }\r
-        z0 = 0;\r
-    }\r
-    *z1Ptr = z1;\r
-    *z0Ptr = z0;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Shifts the 192-bit value formed by concatenating `a0', `a1', and `a2' right\r
-| by 64 _plus_ the number of bits given in `count'.  The shifted result is\r
-| at most 128 nonzero bits; these are broken into two 64-bit pieces which are\r
-| stored at the locations pointed to by `z0Ptr' and `z1Ptr'.  The bits shifted\r
-| off form a third 64-bit result as follows:  The _last_ bit shifted off is\r
-| the most-significant bit of the extra result, and the other 63 bits of the\r
-| extra result are all zero if and only if _all_but_the_last_ bits shifted off\r
-| were all zero.  This extra result is stored in the location pointed to by\r
-| `z2Ptr'.  The value of `count' can be arbitrarily large.\r
-|     (This routine makes more sense if `a0', `a1', and `a2' are considered\r
-| to form a fixed-point value with binary point between `a1' and `a2'.  This\r
-| fixed-point value is shifted right by the number of bits given in `count',\r
-| and the integer part of the result is returned at the locations pointed to\r
-| by `z0Ptr' and `z1Ptr'.  The fractional part of the result may be slightly\r
-| corrupted as described above, and is returned at the location pointed to by\r
-| `z2Ptr'.)\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE void\r
- shift128ExtraRightJamming(\r
-     bits64 a0,\r
-     bits64 a1,\r
-     bits64 a2,\r
-     int16 count,\r
-     bits64 *z0Ptr,\r
-     bits64 *z1Ptr,\r
-     bits64 *z2Ptr\r
- )\r
-{\r
-    bits64 z0, z1, z2;\r
-    int8 negCount = ( - count ) & 63;\r
-\r
-    if ( count == 0 ) {\r
-        z2 = a2;\r
-        z1 = a1;\r
-        z0 = a0;\r
-    }\r
-    else {\r
-        if ( count < 64 ) {\r
-            z2 = a1<<negCount;\r
-            z1 = ( a0<<negCount ) | ( a1>>count );\r
-            z0 = a0>>count;\r
-        }\r
-        else {\r
-            if ( count == 64 ) {\r
-                z2 = a1;\r
-                z1 = a0;\r
-            }\r
-            else {\r
-                a2 |= a1;\r
-                if ( count < 128 ) {\r
-                    z2 = a0<<negCount;\r
-                    z1 = a0>>( count & 63 );\r
-                }\r
-                else {\r
-                    z2 = ( count == 128 ) ? a0 : ( a0 != 0 );\r
-                    z1 = 0;\r
-                }\r
-            }\r
-            z0 = 0;\r
-        }\r
-        z2 |= ( a2 != 0 );\r
-    }\r
-    *z2Ptr = z2;\r
-    *z1Ptr = z1;\r
-    *z0Ptr = z0;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Shifts the 128-bit value formed by concatenating `a0' and `a1' left by the\r
-| number of bits given in `count'.  Any bits shifted off are lost.  The value\r
-| of `count' must be less than 64.  The result is broken into two 64-bit\r
-| pieces which are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE void\r
- shortShift128Left(\r
-     bits64 a0, bits64 a1, int16 count, bits64 *z0Ptr, bits64 *z1Ptr )\r
-{\r
-\r
-    *z1Ptr = a1<<count;\r
-    *z0Ptr =\r
-        ( count == 0 ) ? a0 : ( a0<<count ) | ( a1>>( ( - count ) & 63 ) );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Shifts the 192-bit value formed by concatenating `a0', `a1', and `a2' left\r
-| by the number of bits given in `count'.  Any bits shifted off are lost.\r
-| The value of `count' must be less than 64.  The result is broken into three\r
-| 64-bit pieces which are stored at the locations pointed to by `z0Ptr',\r
-| `z1Ptr', and `z2Ptr'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE void\r
- shortShift192Left(\r
-     bits64 a0,\r
-     bits64 a1,\r
-     bits64 a2,\r
-     int16 count,\r
-     bits64 *z0Ptr,\r
-     bits64 *z1Ptr,\r
-     bits64 *z2Ptr\r
- )\r
-{\r
-    bits64 z0, z1, z2;\r
-    int8 negCount;\r
-\r
-    z2 = a2<<count;\r
-    z1 = a1<<count;\r
-    z0 = a0<<count;\r
-    if ( 0 < count ) {\r
-        negCount = ( ( - count ) & 63 );\r
-        z1 |= a2>>negCount;\r
-        z0 |= a1>>negCount;\r
-    }\r
-    *z2Ptr = z2;\r
-    *z1Ptr = z1;\r
-    *z0Ptr = z0;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Adds the 128-bit value formed by concatenating `a0' and `a1' to the 128-bit\r
-| value formed by concatenating `b0' and `b1'.  Addition is modulo 2^128, so\r
-| any carry out is lost.  The result is broken into two 64-bit pieces which\r
-| are stored at the locations pointed to by `z0Ptr' and `z1Ptr'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE void\r
- add128(\r
-     bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 *z0Ptr, bits64 *z1Ptr )\r
-{\r
-    bits64 z1;\r
-\r
-    z1 = a1 + b1;\r
-    *z1Ptr = z1;\r
-    *z0Ptr = a0 + b0 + ( z1 < a1 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Adds the 192-bit value formed by concatenating `a0', `a1', and `a2' to the\r
-| 192-bit value formed by concatenating `b0', `b1', and `b2'.  Addition is\r
-| modulo 2^192, so any carry out is lost.  The result is broken into three\r
-| 64-bit pieces which are stored at the locations pointed to by `z0Ptr',\r
-| `z1Ptr', and `z2Ptr'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE void\r
- add192(\r
-     bits64 a0,\r
-     bits64 a1,\r
-     bits64 a2,\r
-     bits64 b0,\r
-     bits64 b1,\r
-     bits64 b2,\r
-     bits64 *z0Ptr,\r
-     bits64 *z1Ptr,\r
-     bits64 *z2Ptr\r
- )\r
-{\r
-    bits64 z0, z1, z2;\r
-    int8 carry0, carry1;\r
-\r
-    z2 = a2 + b2;\r
-    carry1 = ( z2 < a2 );\r
-    z1 = a1 + b1;\r
-    carry0 = ( z1 < a1 );\r
-    z0 = a0 + b0;\r
-    z1 += carry1;\r
-    z0 += ( z1 < carry1 );\r
-    z0 += carry0;\r
-    *z2Ptr = z2;\r
-    *z1Ptr = z1;\r
-    *z0Ptr = z0;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Subtracts the 128-bit value formed by concatenating `b0' and `b1' from the\r
-| 128-bit value formed by concatenating `a0' and `a1'.  Subtraction is modulo\r
-| 2^128, so any borrow out (carry out) is lost.  The result is broken into two\r
-| 64-bit pieces which are stored at the locations pointed to by `z0Ptr' and\r
-| `z1Ptr'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE void\r
- sub128(\r
-     bits64 a0, bits64 a1, bits64 b0, bits64 b1, bits64 *z0Ptr, bits64 *z1Ptr )\r
-{\r
-\r
-    *z1Ptr = a1 - b1;\r
-    *z0Ptr = a0 - b0 - ( a1 < b1 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Subtracts the 192-bit value formed by concatenating `b0', `b1', and `b2'\r
-| from the 192-bit value formed by concatenating `a0', `a1', and `a2'.\r
-| Subtraction is modulo 2^192, so any borrow out (carry out) is lost.  The\r
-| result is broken into three 64-bit pieces which are stored at the locations\r
-| pointed to by `z0Ptr', `z1Ptr', and `z2Ptr'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE void\r
- sub192(\r
-     bits64 a0,\r
-     bits64 a1,\r
-     bits64 a2,\r
-     bits64 b0,\r
-     bits64 b1,\r
-     bits64 b2,\r
-     bits64 *z0Ptr,\r
-     bits64 *z1Ptr,\r
-     bits64 *z2Ptr\r
- )\r
-{\r
-    bits64 z0, z1, z2;\r
-    int8 borrow0, borrow1;\r
-\r
-    z2 = a2 - b2;\r
-    borrow1 = ( a2 < b2 );\r
-    z1 = a1 - b1;\r
-    borrow0 = ( a1 < b1 );\r
-    z0 = a0 - b0;\r
-    z0 -= ( z1 < borrow1 );\r
-    z1 -= borrow1;\r
-    z0 -= borrow0;\r
-    *z2Ptr = z2;\r
-    *z1Ptr = z1;\r
-    *z0Ptr = z0;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Multiplies `a' by `b' to obtain a 128-bit product.  The product is broken\r
-| into two 64-bit pieces which are stored at the locations pointed to by\r
-| `z0Ptr' and `z1Ptr'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE void mul64To128( bits64 a, bits64 b, bits64 *z0Ptr, bits64 *z1Ptr )\r
-{\r
-    bits32 aHigh, aLow, bHigh, bLow;\r
-    bits64 z0, zMiddleA, zMiddleB, z1;\r
-\r
-    aLow = a;\r
-    aHigh = a>>32;\r
-    bLow = b;\r
-    bHigh = b>>32;\r
-    z1 = ( (bits64) aLow ) * bLow;\r
-    zMiddleA = ( (bits64) aLow ) * bHigh;\r
-    zMiddleB = ( (bits64) aHigh ) * bLow;\r
-    z0 = ( (bits64) aHigh ) * bHigh;\r
-    zMiddleA += zMiddleB;\r
-    z0 += ( ( (bits64) ( zMiddleA < zMiddleB ) )<<32 ) + ( zMiddleA>>32 );\r
-    zMiddleA <<= 32;\r
-    z1 += zMiddleA;\r
-    z0 += ( z1 < zMiddleA );\r
-    *z1Ptr = z1;\r
-    *z0Ptr = z0;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Multiplies the 128-bit value formed by concatenating `a0' and `a1' by\r
-| `b' to obtain a 192-bit product.  The product is broken into three 64-bit\r
-| pieces which are stored at the locations pointed to by `z0Ptr', `z1Ptr', and\r
-| `z2Ptr'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE void\r
- mul128By64To192(\r
-     bits64 a0,\r
-     bits64 a1,\r
-     bits64 b,\r
-     bits64 *z0Ptr,\r
-     bits64 *z1Ptr,\r
-     bits64 *z2Ptr\r
- )\r
-{\r
-    bits64 z0, z1, z2, more1;\r
-\r
-    mul64To128( a1, b, &z1, &z2 );\r
-    mul64To128( a0, b, &z0, &more1 );\r
-    add128( z0, more1, 0, z1, &z0, &z1 );\r
-    *z2Ptr = z2;\r
-    *z1Ptr = z1;\r
-    *z0Ptr = z0;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Multiplies the 128-bit value formed by concatenating `a0' and `a1' to the\r
-| 128-bit value formed by concatenating `b0' and `b1' to obtain a 256-bit\r
-| product.  The product is broken into four 64-bit pieces which are stored at\r
-| the locations pointed to by `z0Ptr', `z1Ptr', `z2Ptr', and `z3Ptr'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE void\r
- mul128To256(\r
-     bits64 a0,\r
-     bits64 a1,\r
-     bits64 b0,\r
-     bits64 b1,\r
-     bits64 *z0Ptr,\r
-     bits64 *z1Ptr,\r
-     bits64 *z2Ptr,\r
-     bits64 *z3Ptr\r
- )\r
-{\r
-    bits64 z0, z1, z2, z3;\r
-    bits64 more1, more2;\r
-\r
-    mul64To128( a1, b1, &z2, &z3 );\r
-    mul64To128( a1, b0, &z1, &more2 );\r
-    add128( z1, more2, 0, z2, &z1, &z2 );\r
-    mul64To128( a0, b0, &z0, &more1 );\r
-    add128( z0, more1, 0, z1, &z0, &z1 );\r
-    mul64To128( a0, b1, &more1, &more2 );\r
-    add128( more1, more2, 0, z2, &more1, &z2 );\r
-    add128( z0, z1, 0, more1, &z0, &z1 );\r
-    *z3Ptr = z3;\r
-    *z2Ptr = z2;\r
-    *z1Ptr = z1;\r
-    *z0Ptr = z0;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns an approximation to the 64-bit integer quotient obtained by dividing\r
-| `b' into the 128-bit value formed by concatenating `a0' and `a1'.  The\r
-| divisor `b' must be at least 2^63.  If q is the exact quotient truncated\r
-| toward zero, the approximation returned lies between q and q + 2 inclusive.\r
-| If the exact quotient q is larger than 64 bits, the maximum positive 64-bit\r
-| unsigned integer is returned.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static bits64 estimateDiv128To64( bits64 a0, bits64 a1, bits64 b )\r
-{\r
-    bits64 b0, b1;\r
-    bits64 rem0, rem1, term0, term1;\r
-    bits64 z;\r
-\r
-    if ( b <= a0 ) return LIT64( 0xFFFFFFFFFFFFFFFF );\r
-    b0 = b>>32;\r
-    z = ( b0<<32 <= a0 ) ? LIT64( 0xFFFFFFFF00000000 ) : ( a0 / b0 )<<32;\r
-    mul64To128( b, z, &term0, &term1 );\r
-    sub128( a0, a1, term0, term1, &rem0, &rem1 );\r
-    while ( ( (sbits64) rem0 ) < 0 ) {\r
-        z -= LIT64( 0x100000000 );\r
-        b1 = b<<32;\r
-        add128( rem0, rem1, b0, b1, &rem0, &rem1 );\r
-    }\r
-    rem0 = ( rem0<<32 ) | ( rem1>>32 );\r
-    z |= ( b0<<32 <= rem0 ) ? 0xFFFFFFFF : rem0 / b0;\r
-    return z;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns an approximation to the square root of the 32-bit significand given\r
-| by `a'.  Considered as an integer, `a' must be at least 2^31.  If bit 0 of\r
-| `aExp' (the least significant bit) is 1, the integer returned approximates\r
-| 2^31*sqrt(`a'/2^31), where `a' is considered an integer.  If bit 0 of `aExp'\r
-| is 0, the integer returned approximates 2^31*sqrt(`a'/2^30).  In either\r
-| case, the approximation returned lies strictly within +/-2 of the exact\r
-| value.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static bits32 estimateSqrt32( int16 aExp, bits32 a )\r
-{\r
-    static const bits16 sqrtOddAdjustments[] = {\r
-        0x0004, 0x0022, 0x005D, 0x00B1, 0x011D, 0x019F, 0x0236, 0x02E0,\r
-        0x039C, 0x0468, 0x0545, 0x0631, 0x072B, 0x0832, 0x0946, 0x0A67\r
-    };\r
-    static const bits16 sqrtEvenAdjustments[] = {\r
-        0x0A2D, 0x08AF, 0x075A, 0x0629, 0x051A, 0x0429, 0x0356, 0x029E,\r
-        0x0200, 0x0179, 0x0109, 0x00AF, 0x0068, 0x0034, 0x0012, 0x0002\r
-    };\r
-    int8 index;\r
-    bits32 z;\r
-\r
-    index = ( a>>27 ) & 15;\r
-    if ( aExp & 1 ) {\r
-        z = 0x4000 + ( a>>17 ) - sqrtOddAdjustments[ index ];\r
-        z = ( ( a / z )<<14 ) + ( z<<15 );\r
-        a >>= 1;\r
-    }\r
-    else {\r
-        z = 0x8000 + ( a>>17 ) - sqrtEvenAdjustments[ index ];\r
-        z = a / z + z;\r
-        z = ( 0x20000 <= z ) ? 0xFFFF8000 : ( z<<15 );\r
-        if ( z <= a ) return (bits32) ( ( (sbits32) a )>>1 );\r
-    }\r
-    return ( (bits32) ( ( ( (bits64) a )<<31 ) / z ) ) + ( z>>1 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the number of leading 0 bits before the most-significant 1 bit of\r
-| `a'.  If `a' is zero, 32 is returned.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static int8 countLeadingZeros32( bits32 a )\r
-{\r
-    static const int8 countLeadingZerosHigh[] = {\r
-        8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4,\r
-        3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,\r
-        2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\r
-        2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\r
-        1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\r
-        1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\r
-        1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\r
-        1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\r
-        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r
-        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r
-        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r
-        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r
-        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r
-        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r
-        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r
-        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0\r
-    };\r
-    int8 shiftCount;\r
-\r
-    shiftCount = 0;\r
-    if ( a < 0x10000 ) {\r
-        shiftCount += 16;\r
-        a <<= 16;\r
-    }\r
-    if ( a < 0x1000000 ) {\r
-        shiftCount += 8;\r
-        a <<= 8;\r
-    }\r
-    shiftCount += countLeadingZerosHigh[ a>>24 ];\r
-    return shiftCount;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the number of leading 0 bits before the most-significant 1 bit of\r
-| `a'.  If `a' is zero, 64 is returned.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static int8 countLeadingZeros64( bits64 a )\r
-{\r
-    int8 shiftCount;\r
-\r
-    shiftCount = 0;\r
-    if ( a < ( (bits64) 1 )<<32 ) {\r
-        shiftCount += 32;\r
-    }\r
-    else {\r
-        a >>= 32;\r
-    }\r
-    shiftCount += countLeadingZeros32( a );\r
-    return shiftCount;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the 128-bit value formed by concatenating `a0' and `a1'\r
-| is equal to the 128-bit value formed by concatenating `b0' and `b1'.\r
-| Otherwise, returns 0.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE flag eq128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )\r
-{\r
-\r
-    return ( a0 == b0 ) && ( a1 == b1 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' is less\r
-| than or equal to the 128-bit value formed by concatenating `b0' and `b1'.\r
-| Otherwise, returns 0.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE flag le128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )\r
-{\r
-\r
-    return ( a0 < b0 ) || ( ( a0 == b0 ) && ( a1 <= b1 ) );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' is less\r
-| than the 128-bit value formed by concatenating `b0' and `b1'.  Otherwise,\r
-| returns 0.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE flag lt128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )\r
-{\r
-\r
-    return ( a0 < b0 ) || ( ( a0 == b0 ) && ( a1 < b1 ) );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the 128-bit value formed by concatenating `a0' and `a1' is\r
-| not equal to the 128-bit value formed by concatenating `b0' and `b1'.\r
-| Otherwise, returns 0.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE flag ne128( bits64 a0, bits64 a1, bits64 b0, bits64 b1 )\r
-{\r
-\r
-    return ( a0 != b0 ) || ( a1 != b1 );\r
-\r
-}\r
-\r

diff --git a/softfloat/softfloat-specialize b/softfloat/softfloat-specialize
deleted file mode 100644 (file)
index 28bd4fe..0000000
--- a/softfloat/softfloat-specialize
+++ /dev/null
@@ -1,412 +0,0 @@
-
-/*============================================================================
-
-This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
-Arithmetic Package, Release 2b.
-
-Written by John R. Hauser.  This work was made possible in part by the
-International Computer Science Institute, located at Suite 600, 1947 Center
-Street, Berkeley, California 94704.  Funding was partially provided by the
-National Science Foundation under grant MIP-9311980.  The original version
-of this code was written as part of a project to build a fixed-point vector
-processor in collaboration with the University of California at Berkeley,
-overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
-is available through the Web page `http://www.cs.berkeley.edu/~jhauser/
-arithmetic/SoftFloat.html'.
-
-THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has
-been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
-RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
-AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
-COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
-EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
-INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR
-OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
-
-Derivative works are acceptable, even for commercial purposes, so long as
-(1) the source code for the derivative work includes prominent notice that
-the work is derivative, and (2) the source code includes prominent notice with
-these four paragraphs for those parts of this code that are retained.
-
-=============================================================================*/
-
-/*----------------------------------------------------------------------------
-| Underflow tininess-detection mode, statically initialized to default value.
-| (The declaration in `softfloat.h' must match the `int8' type here.)
-*----------------------------------------------------------------------------*/
-int8 float_detect_tininess = float_tininess_before_rounding;
-
-/*----------------------------------------------------------------------------
-| Raises the exceptions specified by `flags'.  Floating-point traps can be
-| defined here if desired.  It is currently not possible for such a trap
-| to substitute a result value.  If traps are not implemented, this routine
-| should be simply `float_exception_flags |= flags;'.
-*----------------------------------------------------------------------------*/
-
-void float_raise( int8 flags )
-{
-
-    float_exception_flags |= flags;
-
-}
-
-/*----------------------------------------------------------------------------
-| Internal canonical NaN format.
-*----------------------------------------------------------------------------*/
-typedef struct {
-    flag sign;
-    bits64 high, low;
-} commonNaNT;
-
-/*----------------------------------------------------------------------------
-| The pattern for a default generated single-precision NaN.
-*----------------------------------------------------------------------------*/
-#define float32_default_nan 0x7FFFFFFF
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the single-precision floating-point value `a' is a NaN;
-| otherwise returns 0.
-*----------------------------------------------------------------------------*/
-
-flag float32_is_nan( float32 a )
-{
-
-    return ( 0xFF000000 < (bits32) ( a<<1 ) );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the single-precision floating-point value `a' is a signaling
-| NaN; otherwise returns 0.
-*----------------------------------------------------------------------------*/
-
-flag float32_is_signaling_nan( float32 a )
-{
-
-    return ( ( ( a>>22 ) & 0x1FF ) == 0x1FE ) && ( a & 0x003FFFFF );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the single-precision floating-point NaN
-| `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid
-| exception is raised.
-*----------------------------------------------------------------------------*/
-
-static commonNaNT float32ToCommonNaN( float32 a )
-{
-    commonNaNT z;
-
-    if ( float32_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
-    z.sign = a>>31;
-    z.low = 0;
-    z.high = ( (bits64) a )<<41;
-    return z;
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the canonical NaN `a' to the single-
-| precision floating-point format.
-*----------------------------------------------------------------------------*/
-
-static float32 commonNaNToFloat32( commonNaNT a )
-{
-
-    return ( ( (bits32) a.sign )<<31 ) | 0x7FC00000 | ( a.high>>41 );
-
-}
-
-/*----------------------------------------------------------------------------
-| Takes two single-precision floating-point values `a' and `b', one of which
-| is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a
-| signaling NaN, the invalid exception is raised.
-*----------------------------------------------------------------------------*/
-
-static float32 propagateFloat32NaN( float32 a, float32 b )
-{
-    flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
-
-    aIsNaN = float32_is_nan( a );
-    aIsSignalingNaN = float32_is_signaling_nan( a );
-    bIsNaN = float32_is_nan( b );
-    bIsSignalingNaN = float32_is_signaling_nan( b );
-    a |= 0x00400000;
-    b |= 0x00400000;
-    if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );
-    return bIsSignalingNaN ? b : aIsSignalingNaN ? a : bIsNaN ? b : a;
-
-}
-
-/*----------------------------------------------------------------------------
-| The pattern for a default generated double-precision NaN.
-*----------------------------------------------------------------------------*/
-#define float64_default_nan LIT64( 0x7FFFFFFFFFFFFFFF )
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the double-precision floating-point value `a' is a NaN;
-| otherwise returns 0.
-*----------------------------------------------------------------------------*/
-
-flag float64_is_nan( float64 a )
-{
-
-    return ( LIT64( 0xFFE0000000000000 ) < (bits64) ( a<<1 ) );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the double-precision floating-point value `a' is a signaling
-| NaN; otherwise returns 0.
-*----------------------------------------------------------------------------*/
-
-flag float64_is_signaling_nan( float64 a )
-{
-
-    return
-           ( ( ( a>>51 ) & 0xFFF ) == 0xFFE )
-        && ( a & LIT64( 0x0007FFFFFFFFFFFF ) );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the double-precision floating-point NaN
-| `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid
-| exception is raised.
-*----------------------------------------------------------------------------*/
-
-static commonNaNT float64ToCommonNaN( float64 a )
-{
-    commonNaNT z;
-
-    if ( float64_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
-    z.sign = a>>63;
-    z.low = 0;
-    z.high = a<<12;
-    return z;
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the canonical NaN `a' to the double-
-| precision floating-point format.
-*----------------------------------------------------------------------------*/
-
-static float64 commonNaNToFloat64( commonNaNT a )
-{
-
-    return
-          ( ( (bits64) a.sign )<<63 )
-        | LIT64( 0x7FF8000000000000 )
-        | ( a.high>>12 );
-
-}
-
-/*----------------------------------------------------------------------------
-| Takes two double-precision floating-point values `a' and `b', one of which
-| is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a
-| signaling NaN, the invalid exception is raised.
-*----------------------------------------------------------------------------*/
-
-static float64 propagateFloat64NaN( float64 a, float64 b )
-{
-    flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
-
-    aIsNaN = float64_is_nan( a );
-    aIsSignalingNaN = float64_is_signaling_nan( a );
-    bIsNaN = float64_is_nan( b );
-    bIsSignalingNaN = float64_is_signaling_nan( b );
-    a |= LIT64( 0x0008000000000000 );
-    b |= LIT64( 0x0008000000000000 );
-    if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );
-    return bIsSignalingNaN ? b : aIsSignalingNaN ? a : bIsNaN ? b : a;
-
-}
-
-#ifdef FLOATX80
-
-/*----------------------------------------------------------------------------
-| The pattern for a default generated extended double-precision NaN.  The
-| `high' and `low' values hold the most- and least-significant bits,
-| respectively.
-*----------------------------------------------------------------------------*/
-#define floatx80_default_nan_high 0x7FFF
-#define floatx80_default_nan_low  LIT64( 0xFFFFFFFFFFFFFFFF )
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the extended double-precision floating-point value `a' is a
-| NaN; otherwise returns 0.
-*----------------------------------------------------------------------------*/
-
-flag floatx80_is_nan( floatx80 a )
-{
-
-    return ( ( a.high & 0x7FFF ) == 0x7FFF ) && (bits64) ( a.low<<1 );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the extended double-precision floating-point value `a' is a
-| signaling NaN; otherwise returns 0.
-*----------------------------------------------------------------------------*/
-
-flag floatx80_is_signaling_nan( floatx80 a )
-{
-    bits64 aLow;
-
-    aLow = a.low & ~ LIT64( 0x4000000000000000 );
-    return
-           ( ( a.high & 0x7FFF ) == 0x7FFF )
-        && (bits64) ( aLow<<1 )
-        && ( a.low == aLow );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the extended double-precision floating-
-| point NaN `a' to the canonical NaN format.  If `a' is a signaling NaN, the
-| invalid exception is raised.
-*----------------------------------------------------------------------------*/
-
-static commonNaNT floatx80ToCommonNaN( floatx80 a )
-{
-    commonNaNT z;
-
-    if ( floatx80_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
-    z.sign = a.high>>15;
-    z.low = 0;
-    z.high = a.low<<1;
-    return z;
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the canonical NaN `a' to the extended
-| double-precision floating-point format.
-*----------------------------------------------------------------------------*/
-
-static floatx80 commonNaNToFloatx80( commonNaNT a )
-{
-    floatx80 z;
-
-    z.low = LIT64( 0xC000000000000000 ) | ( a.high>>1 );
-    z.high = ( ( (bits16) a.sign )<<15 ) | 0x7FFF;
-    return z;
-
-}
-
-/*----------------------------------------------------------------------------
-| Takes two extended double-precision floating-point values `a' and `b', one
-| of which is a NaN, and returns the appropriate NaN result.  If either `a' or
-| `b' is a signaling NaN, the invalid exception is raised.
-*----------------------------------------------------------------------------*/
-
-static floatx80 propagateFloatx80NaN( floatx80 a, floatx80 b )
-{
-    flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
-
-    aIsNaN = floatx80_is_nan( a );
-    aIsSignalingNaN = floatx80_is_signaling_nan( a );
-    bIsNaN = floatx80_is_nan( b );
-    bIsSignalingNaN = floatx80_is_signaling_nan( b );
-    a.low |= LIT64( 0xC000000000000000 );
-    b.low |= LIT64( 0xC000000000000000 );
-    if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );
-    return bIsSignalingNaN ? b : aIsSignalingNaN ? a : bIsNaN ? b : a;
-
-}
-
-#endif
-
-#ifdef FLOAT128
-
-/*----------------------------------------------------------------------------
-| The pattern for a default generated quadruple-precision NaN.  The `high' and
-| `low' values hold the most- and least-significant bits, respectively.
-*----------------------------------------------------------------------------*/
-#define float128_default_nan_high LIT64( 0x7FFFFFFFFFFFFFFF )
-#define float128_default_nan_low  LIT64( 0xFFFFFFFFFFFFFFFF )
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the quadruple-precision floating-point value `a' is a NaN;
-| otherwise returns 0.
-*----------------------------------------------------------------------------*/
-
-flag float128_is_nan( float128 a )
-{
-
-    return
-           ( LIT64( 0xFFFE000000000000 ) <= (bits64) ( a.high<<1 ) )
-        && ( a.low || ( a.high & LIT64( 0x0000FFFFFFFFFFFF ) ) );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns 1 if the quadruple-precision floating-point value `a' is a
-| signaling NaN; otherwise returns 0.
-*----------------------------------------------------------------------------*/
-
-flag float128_is_signaling_nan( float128 a )
-{
-
-    return
-           ( ( ( a.high>>47 ) & 0xFFFF ) == 0xFFFE )
-        && ( a.low || ( a.high & LIT64( 0x00007FFFFFFFFFFF ) ) );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the quadruple-precision floating-point NaN
-| `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid
-| exception is raised.
-*----------------------------------------------------------------------------*/
-
-static commonNaNT float128ToCommonNaN( float128 a )
-{
-    commonNaNT z;
-
-    if ( float128_is_signaling_nan( a ) ) float_raise( float_flag_invalid );
-    z.sign = a.high>>63;
-    shortShift128Left( a.high, a.low, 16, &z.high, &z.low );
-    return z;
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of converting the canonical NaN `a' to the quadruple-
-| precision floating-point format.
-*----------------------------------------------------------------------------*/
-
-static float128 commonNaNToFloat128( commonNaNT a )
-{
-    float128 z;
-
-    shift128Right( a.high, a.low, 16, &z.high, &z.low );
-    z.high |= ( ( (bits64) a.sign )<<63 ) | LIT64( 0x7FFF800000000000 );
-    return z;
-
-}
-
-/*----------------------------------------------------------------------------
-| Takes two quadruple-precision floating-point values `a' and `b', one of
-| which is a NaN, and returns the appropriate NaN result.  If either `a' or
-| `b' is a signaling NaN, the invalid exception is raised.
-*----------------------------------------------------------------------------*/
-
-static float128 propagateFloat128NaN( float128 a, float128 b )
-{
-    flag aIsNaN, aIsSignalingNaN, bIsNaN, bIsSignalingNaN;
-
-    aIsNaN = float128_is_nan( a );
-    aIsSignalingNaN = float128_is_signaling_nan( a );
-    bIsNaN = float128_is_nan( b );
-    bIsSignalingNaN = float128_is_signaling_nan( b );
-    a.high |= LIT64( 0x0000800000000000 );
-    b.high |= LIT64( 0x0000800000000000 );
-    if ( aIsSignalingNaN | bIsSignalingNaN ) float_raise( float_flag_invalid );
-    return bIsSignalingNaN ? b : aIsSignalingNaN ? a : bIsNaN ? b : a;
-
-}
-
-#endif
-

diff --git a/softfloat/softfloat.c b/softfloat/softfloat.c
deleted file mode 100644 (file)
index 0d09b40..0000000
--- a/softfloat/softfloat.c
+++ /dev/null
@@ -1,5188 +0,0 @@
-\r
-/*============================================================================\r
-\r
-This C source file is part of the SoftFloat IEC/IEEE Floating-point Arithmetic\r
-Package, Release 2b.\r
-\r
-Written by John R. Hauser.  This work was made possible in part by the\r
-International Computer Science Institute, located at Suite 600, 1947 Center\r
-Street, Berkeley, California 94704.  Funding was partially provided by the\r
-National Science Foundation under grant MIP-9311980.  The original version\r
-of this code was written as part of a project to build a fixed-point vector\r
-processor in collaboration with the University of California at Berkeley,\r
-overseen by Profs. Nelson Morgan and John Wawrzynek.  More information\r
-is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
-arithmetic/SoftFloat.html'.\r
-\r
-THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has\r
-been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
-RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
-AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
-COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
-EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
-INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
-OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
-\r
-Derivative works are acceptable, even for commercial purposes, so long as\r
-(1) the source code for the derivative work includes prominent notice that\r
-the work is derivative, and (2) the source code includes prominent notice with\r
-these four paragraphs for those parts of this code that are retained.\r
-\r
-=============================================================================*/\r
-\r
-#include "milieu.h"\r
-#include "softfloat.h"\r
-\r
-/*----------------------------------------------------------------------------\r
-| Floating-point rounding mode, extended double-precision rounding precision,\r
-| and exception flags.\r
-*----------------------------------------------------------------------------*/\r
-int8 float_rounding_mode = float_round_nearest_even;\r
-int8 float_exception_flags = 0;\r
-#ifdef FLOATX80\r
-int8 floatx80_rounding_precision = 80;\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------\r
-| Primitive arithmetic functions, including multi-word arithmetic, and\r
-| division and square root approximations.  (Can be specialized to target if\r
-| desired.)\r
-*----------------------------------------------------------------------------*/\r
-#include "softfloat-macros"\r
-\r
-/*----------------------------------------------------------------------------\r
-| Functions and definitions to determine:  (1) whether tininess for underflow\r
-| is detected before or after rounding by default, (2) what (if anything)\r
-| happens when exceptions are raised, (3) how signaling NaNs are distinguished\r
-| from quiet NaNs, (4) the default generated quiet NaNs, and (5) how NaNs\r
-| are propagated from function inputs to output.  These details are target-\r
-| specific.\r
-*----------------------------------------------------------------------------*/\r
-#include "softfloat-specialize"\r
-\r
-/*----------------------------------------------------------------------------\r
-| Takes a 64-bit fixed-point value `absZ' with binary point between bits 6\r
-| and 7, and returns the properly rounded 32-bit integer corresponding to the\r
-| input.  If `zSign' is 1, the input is negated before being converted to an\r
-| integer.  Bit 63 of `absZ' must be zero.  Ordinarily, the fixed-point input\r
-| is simply rounded to an integer, with the inexact exception raised if the\r
-| input cannot be represented exactly as an integer.  However, if the fixed-\r
-| point input is too large, the invalid exception is raised and the largest\r
-| positive or negative integer is returned.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static int32 roundAndPackInt32( flag zSign, bits64 absZ )\r
-{\r
-    int8 roundingMode;\r
-    flag roundNearestEven;\r
-    int8 roundIncrement, roundBits;\r
-    int32 z;\r
-\r
-    roundingMode = float_rounding_mode;\r
-    roundNearestEven = ( roundingMode == float_round_nearest_even );\r
-    roundIncrement = 0x40;\r
-    if ( ! roundNearestEven ) {\r
-        if ( roundingMode == float_round_to_zero ) {\r
-            roundIncrement = 0;\r
-        }\r
-        else {\r
-            roundIncrement = 0x7F;\r
-            if ( zSign ) {\r
-                if ( roundingMode == float_round_up ) roundIncrement = 0;\r
-            }\r
-            else {\r
-                if ( roundingMode == float_round_down ) roundIncrement = 0;\r
-            }\r
-        }\r
-    }\r
-    roundBits = absZ & 0x7F;\r
-    absZ = ( absZ + roundIncrement )>>7;\r
-    absZ &= ~ ( ( ( roundBits ^ 0x40 ) == 0 ) & roundNearestEven );\r
-    z = absZ;\r
-    if ( zSign ) z = - z;\r
-    if ( ( absZ>>32 ) || ( z && ( ( z < 0 ) ^ zSign ) ) ) {\r
-        float_raise( float_flag_invalid );\r
-        return zSign ? (sbits32) 0x80000000 : 0x7FFFFFFF;\r
-    }\r
-    if ( roundBits ) float_exception_flags |= float_flag_inexact;\r
-    return z;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Takes the 128-bit fixed-point value formed by concatenating `absZ0' and\r
-| `absZ1', with binary point between bits 63 and 64 (between the input words),\r
-| and returns the properly rounded 64-bit integer corresponding to the input.\r
-| If `zSign' is 1, the input is negated before being converted to an integer.\r
-| Ordinarily, the fixed-point input is simply rounded to an integer, with\r
-| the inexact exception raised if the input cannot be represented exactly as\r
-| an integer.  However, if the fixed-point input is too large, the invalid\r
-| exception is raised and the largest positive or negative integer is\r
-| returned.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static int64 roundAndPackInt64( flag zSign, bits64 absZ0, bits64 absZ1 )\r
-{\r
-    int8 roundingMode;\r
-    flag roundNearestEven, increment;\r
-    int64 z;\r
-\r
-    roundingMode = float_rounding_mode;\r
-    roundNearestEven = ( roundingMode == float_round_nearest_even );\r
-    increment = ( (sbits64) absZ1 < 0 );\r
-    if ( ! roundNearestEven ) {\r
-        if ( roundingMode == float_round_to_zero ) {\r
-            increment = 0;\r
-        }\r
-        else {\r
-            if ( zSign ) {\r
-                increment = ( roundingMode == float_round_down ) && absZ1;\r
-            }\r
-            else {\r
-                increment = ( roundingMode == float_round_up ) && absZ1;\r
-            }\r
-        }\r
-    }\r
-    if ( increment ) {\r
-        ++absZ0;\r
-        if ( absZ0 == 0 ) goto overflow;\r
-        absZ0 &= ~ ( ( (bits64) ( absZ1<<1 ) == 0 ) & roundNearestEven );\r
-    }\r
-    z = absZ0;\r
-    if ( zSign ) z = - z;\r
-    if ( z && ( ( z < 0 ) ^ zSign ) ) {\r
- overflow:\r
-        float_raise( float_flag_invalid );\r
-        return\r
-              zSign ? (sbits64) LIT64( 0x8000000000000000 )\r
-            : LIT64( 0x7FFFFFFFFFFFFFFF );\r
-    }\r
-    if ( absZ1 ) float_exception_flags |= float_flag_inexact;\r
-    return z;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the fraction bits of the single-precision floating-point value `a'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE bits32 extractFloat32Frac( float32 a )\r
-{\r
-\r
-    return a & 0x007FFFFF;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the exponent bits of the single-precision floating-point value `a'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE int16 extractFloat32Exp( float32 a )\r
-{\r
-\r
-    return ( a>>23 ) & 0xFF;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the sign bit of the single-precision floating-point value `a'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE flag extractFloat32Sign( float32 a )\r
-{\r
-\r
-    return a>>31;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Normalizes the subnormal single-precision floating-point value represented\r
-| by the denormalized significand `aSig'.  The normalized exponent and\r
-| significand are stored at the locations pointed to by `zExpPtr' and\r
-| `zSigPtr', respectively.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static void\r
- normalizeFloat32Subnormal( bits32 aSig, int16 *zExpPtr, bits32 *zSigPtr )\r
-{\r
-    int8 shiftCount;\r
-\r
-    shiftCount = countLeadingZeros32( aSig ) - 8;\r
-    *zSigPtr = aSig<<shiftCount;\r
-    *zExpPtr = 1 - shiftCount;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Packs the sign `zSign', exponent `zExp', and significand `zSig' into a\r
-| single-precision floating-point value, returning the result.  After being\r
-| shifted into the proper positions, the three fields are simply added\r
-| together to form the result.  This means that any integer portion of `zSig'\r
-| will be added into the exponent.  Since a properly normalized significand\r
-| will have an integer portion equal to 1, the `zExp' input should be 1 less\r
-| than the desired result exponent whenever `zSig' is a complete, normalized\r
-| significand.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE float32 packFloat32( flag zSign, int16 zExp, bits32 zSig )\r
-{\r
-\r
-    return ( ( (bits32) zSign )<<31 ) + ( ( (bits32) zExp )<<23 ) + zSig;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
-| and significand `zSig', and returns the proper single-precision floating-\r
-| point value corresponding to the abstract input.  Ordinarily, the abstract\r
-| value is simply rounded and packed into the single-precision format, with\r
-| the inexact exception raised if the abstract input cannot be represented\r
-| exactly.  However, if the abstract value is too large, the overflow and\r
-| inexact exceptions are raised and an infinity or maximal finite value is\r
-| returned.  If the abstract value is too small, the input value is rounded to\r
-| a subnormal number, and the underflow and inexact exceptions are raised if\r
-| the abstract input cannot be represented exactly as a subnormal single-\r
-| precision floating-point number.\r
-|     The input significand `zSig' has its binary point between bits 30\r
-| and 29, which is 7 bits to the left of the usual location.  This shifted\r
-| significand must be normalized or smaller.  If `zSig' is not normalized,\r
-| `zExp' must be 0; in that case, the result returned is a subnormal number,\r
-| and it must not require rounding.  In the usual case that `zSig' is\r
-| normalized, `zExp' must be 1 less than the ``true'' floating-point exponent.\r
-| The handling of underflow and overflow follows the IEC/IEEE Standard for\r
-| Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static float32 roundAndPackFloat32( flag zSign, int16 zExp, bits32 zSig )\r
-{\r
-    int8 roundingMode;\r
-    flag roundNearestEven;\r
-    int8 roundIncrement, roundBits;\r
-    flag isTiny;\r
-\r
-    roundingMode = float_rounding_mode;\r
-    roundNearestEven = ( roundingMode == float_round_nearest_even );\r
-    roundIncrement = 0x40;\r
-    if ( ! roundNearestEven ) {\r
-        if ( roundingMode == float_round_to_zero ) {\r
-            roundIncrement = 0;\r
-        }\r
-        else {\r
-            roundIncrement = 0x7F;\r
-            if ( zSign ) {\r
-                if ( roundingMode == float_round_up ) roundIncrement = 0;\r
-            }\r
-            else {\r
-                if ( roundingMode == float_round_down ) roundIncrement = 0;\r
-            }\r
-        }\r
-    }\r
-    roundBits = zSig & 0x7F;\r
-    if ( 0xFD <= (bits16) zExp ) {\r
-        if (    ( 0xFD < zExp )\r
-             || (    ( zExp == 0xFD )\r
-                  && ( (sbits32) ( zSig + roundIncrement ) < 0 ) )\r
-           ) {\r
-            float_raise( float_flag_overflow | float_flag_inexact );\r
-            return packFloat32( zSign, 0xFF, 0 ) - ( roundIncrement == 0 );\r
-        }\r
-        if ( zExp < 0 ) {\r
-            isTiny =\r
-                   ( float_detect_tininess == float_tininess_before_rounding )\r
-                || ( zExp < -1 )\r
-                || ( zSig + roundIncrement < 0x80000000 );\r
-            shift32RightJamming( zSig, - zExp, &zSig );\r
-            zExp = 0;\r
-            roundBits = zSig & 0x7F;\r
-            if ( isTiny && roundBits ) float_raise( float_flag_underflow );\r
-        }\r
-    }\r
-    if ( roundBits ) float_exception_flags |= float_flag_inexact;\r
-    zSig = ( zSig + roundIncrement )>>7;\r
-    zSig &= ~ ( ( ( roundBits ^ 0x40 ) == 0 ) & roundNearestEven );\r
-    if ( zSig == 0 ) zExp = 0;\r
-    return packFloat32( zSign, zExp, zSig );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
-| and significand `zSig', and returns the proper single-precision floating-\r
-| point value corresponding to the abstract input.  This routine is just like\r
-| `roundAndPackFloat32' except that `zSig' does not have to be normalized.\r
-| Bit 31 of `zSig' must be zero, and `zExp' must be 1 less than the ``true''\r
-| floating-point exponent.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static float32\r
- normalizeRoundAndPackFloat32( flag zSign, int16 zExp, bits32 zSig )\r
-{\r
-    int8 shiftCount;\r
-\r
-    shiftCount = countLeadingZeros32( zSig ) - 1;\r
-    return roundAndPackFloat32( zSign, zExp - shiftCount, zSig<<shiftCount );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the fraction bits of the double-precision floating-point value `a'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE bits64 extractFloat64Frac( float64 a )\r
-{\r
-\r
-    return a & LIT64( 0x000FFFFFFFFFFFFF );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the exponent bits of the double-precision floating-point value `a'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE int16 extractFloat64Exp( float64 a )\r
-{\r
-\r
-    return ( a>>52 ) & 0x7FF;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the sign bit of the double-precision floating-point value `a'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE flag extractFloat64Sign( float64 a )\r
-{\r
-\r
-    return a>>63;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Normalizes the subnormal double-precision floating-point value represented\r
-| by the denormalized significand `aSig'.  The normalized exponent and\r
-| significand are stored at the locations pointed to by `zExpPtr' and\r
-| `zSigPtr', respectively.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static void\r
- normalizeFloat64Subnormal( bits64 aSig, int16 *zExpPtr, bits64 *zSigPtr )\r
-{\r
-    int8 shiftCount;\r
-\r
-    shiftCount = countLeadingZeros64( aSig ) - 11;\r
-    *zSigPtr = aSig<<shiftCount;\r
-    *zExpPtr = 1 - shiftCount;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Packs the sign `zSign', exponent `zExp', and significand `zSig' into a\r
-| double-precision floating-point value, returning the result.  After being\r
-| shifted into the proper positions, the three fields are simply added\r
-| together to form the result.  This means that any integer portion of `zSig'\r
-| will be added into the exponent.  Since a properly normalized significand\r
-| will have an integer portion equal to 1, the `zExp' input should be 1 less\r
-| than the desired result exponent whenever `zSig' is a complete, normalized\r
-| significand.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE float64 packFloat64( flag zSign, int16 zExp, bits64 zSig )\r
-{\r
-\r
-    return ( ( (bits64) zSign )<<63 ) + ( ( (bits64) zExp )<<52 ) + zSig;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
-| and significand `zSig', and returns the proper double-precision floating-\r
-| point value corresponding to the abstract input.  Ordinarily, the abstract\r
-| value is simply rounded and packed into the double-precision format, with\r
-| the inexact exception raised if the abstract input cannot be represented\r
-| exactly.  However, if the abstract value is too large, the overflow and\r
-| inexact exceptions are raised and an infinity or maximal finite value is\r
-| returned.  If the abstract value is too small, the input value is rounded\r
-| to a subnormal number, and the underflow and inexact exceptions are raised\r
-| if the abstract input cannot be represented exactly as a subnormal double-\r
-| precision floating-point number.\r
-|     The input significand `zSig' has its binary point between bits 62\r
-| and 61, which is 10 bits to the left of the usual location.  This shifted\r
-| significand must be normalized or smaller.  If `zSig' is not normalized,\r
-| `zExp' must be 0; in that case, the result returned is a subnormal number,\r
-| and it must not require rounding.  In the usual case that `zSig' is\r
-| normalized, `zExp' must be 1 less than the ``true'' floating-point exponent.\r
-| The handling of underflow and overflow follows the IEC/IEEE Standard for\r
-| Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static float64 roundAndPackFloat64( flag zSign, int16 zExp, bits64 zSig )\r
-{\r
-    int8 roundingMode;\r
-    flag roundNearestEven;\r
-    int16 roundIncrement, roundBits;\r
-    flag isTiny;\r
-\r
-    roundingMode = float_rounding_mode;\r
-    roundNearestEven = ( roundingMode == float_round_nearest_even );\r
-    roundIncrement = 0x200;\r
-    if ( ! roundNearestEven ) {\r
-        if ( roundingMode == float_round_to_zero ) {\r
-            roundIncrement = 0;\r
-        }\r
-        else {\r
-            roundIncrement = 0x3FF;\r
-            if ( zSign ) {\r
-                if ( roundingMode == float_round_up ) roundIncrement = 0;\r
-            }\r
-            else {\r
-                if ( roundingMode == float_round_down ) roundIncrement = 0;\r
-            }\r
-        }\r
-    }\r
-    roundBits = zSig & 0x3FF;\r
-    if ( 0x7FD <= (bits16) zExp ) {\r
-        if (    ( 0x7FD < zExp )\r
-             || (    ( zExp == 0x7FD )\r
-                  && ( (sbits64) ( zSig + roundIncrement ) < 0 ) )\r
-           ) {\r
-            float_raise( float_flag_overflow | float_flag_inexact );\r
-            return packFloat64( zSign, 0x7FF, 0 ) - ( roundIncrement == 0 );\r
-        }\r
-        if ( zExp < 0 ) {\r
-            isTiny =\r
-                   ( float_detect_tininess == float_tininess_before_rounding )\r
-                || ( zExp < -1 )\r
-                || ( zSig + roundIncrement < LIT64( 0x8000000000000000 ) );\r
-            shift64RightJamming( zSig, - zExp, &zSig );\r
-            zExp = 0;\r
-            roundBits = zSig & 0x3FF;\r
-            if ( isTiny && roundBits ) float_raise( float_flag_underflow );\r
-        }\r
-    }\r
-    if ( roundBits ) float_exception_flags |= float_flag_inexact;\r
-    zSig = ( zSig + roundIncrement )>>10;\r
-    zSig &= ~ ( ( ( roundBits ^ 0x200 ) == 0 ) & roundNearestEven );\r
-    if ( zSig == 0 ) zExp = 0;\r
-    return packFloat64( zSign, zExp, zSig );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
-| and significand `zSig', and returns the proper double-precision floating-\r
-| point value corresponding to the abstract input.  This routine is just like\r
-| `roundAndPackFloat64' except that `zSig' does not have to be normalized.\r
-| Bit 63 of `zSig' must be zero, and `zExp' must be 1 less than the ``true''\r
-| floating-point exponent.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static float64\r
- normalizeRoundAndPackFloat64( flag zSign, int16 zExp, bits64 zSig )\r
-{\r
-    int8 shiftCount;\r
-\r
-    shiftCount = countLeadingZeros64( zSig ) - 1;\r
-    return roundAndPackFloat64( zSign, zExp - shiftCount, zSig<<shiftCount );\r
-\r
-}\r
-\r
-#ifdef FLOATX80\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the fraction bits of the extended double-precision floating-point\r
-| value `a'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE bits64 extractFloatx80Frac( floatx80 a )\r
-{\r
-\r
-    return a.low;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the exponent bits of the extended double-precision floating-point\r
-| value `a'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE int32 extractFloatx80Exp( floatx80 a )\r
-{\r
-\r
-    return a.high & 0x7FFF;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the sign bit of the extended double-precision floating-point value\r
-| `a'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE flag extractFloatx80Sign( floatx80 a )\r
-{\r
-\r
-    return a.high>>15;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Normalizes the subnormal extended double-precision floating-point value\r
-| represented by the denormalized significand `aSig'.  The normalized exponent\r
-| and significand are stored at the locations pointed to by `zExpPtr' and\r
-| `zSigPtr', respectively.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static void\r
- normalizeFloatx80Subnormal( bits64 aSig, int32 *zExpPtr, bits64 *zSigPtr )\r
-{\r
-    int8 shiftCount;\r
-\r
-    shiftCount = countLeadingZeros64( aSig );\r
-    *zSigPtr = aSig<<shiftCount;\r
-    *zExpPtr = 1 - shiftCount;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Packs the sign `zSign', exponent `zExp', and significand `zSig' into an\r
-| extended double-precision floating-point value, returning the result.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE floatx80 packFloatx80( flag zSign, int32 zExp, bits64 zSig )\r
-{\r
-    floatx80 z;\r
-\r
-    z.low = zSig;\r
-    z.high = ( ( (bits16) zSign )<<15 ) + zExp;\r
-    return z;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
-| and extended significand formed by the concatenation of `zSig0' and `zSig1',\r
-| and returns the proper extended double-precision floating-point value\r
-| corresponding to the abstract input.  Ordinarily, the abstract value is\r
-| rounded and packed into the extended double-precision format, with the\r
-| inexact exception raised if the abstract input cannot be represented\r
-| exactly.  However, if the abstract value is too large, the overflow and\r
-| inexact exceptions are raised and an infinity or maximal finite value is\r
-| returned.  If the abstract value is too small, the input value is rounded to\r
-| a subnormal number, and the underflow and inexact exceptions are raised if\r
-| the abstract input cannot be represented exactly as a subnormal extended\r
-| double-precision floating-point number.\r
-|     If `roundingPrecision' is 32 or 64, the result is rounded to the same\r
-| number of bits as single or double precision, respectively.  Otherwise, the\r
-| result is rounded to the full precision of the extended double-precision\r
-| format.\r
-|     The input significand must be normalized or smaller.  If the input\r
-| significand is not normalized, `zExp' must be 0; in that case, the result\r
-| returned is a subnormal number, and it must not require rounding.  The\r
-| handling of underflow and overflow follows the IEC/IEEE Standard for Binary\r
-| Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static floatx80\r
- roundAndPackFloatx80(\r
-     int8 roundingPrecision, flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1\r
- )\r
-{\r
-    int8 roundingMode;\r
-    flag roundNearestEven, increment, isTiny;\r
-    int64 roundIncrement, roundMask, roundBits;\r
-\r
-    roundingMode = float_rounding_mode;\r
-    roundNearestEven = ( roundingMode == float_round_nearest_even );\r
-    if ( roundingPrecision == 80 ) goto precision80;\r
-    if ( roundingPrecision == 64 ) {\r
-        roundIncrement = LIT64( 0x0000000000000400 );\r
-        roundMask = LIT64( 0x00000000000007FF );\r
-    }\r
-    else if ( roundingPrecision == 32 ) {\r
-        roundIncrement = LIT64( 0x0000008000000000 );\r
-        roundMask = LIT64( 0x000000FFFFFFFFFF );\r
-    }\r
-    else {\r
-        goto precision80;\r
-    }\r
-    zSig0 |= ( zSig1 != 0 );\r
-    if ( ! roundNearestEven ) {\r
-        if ( roundingMode == float_round_to_zero ) {\r
-            roundIncrement = 0;\r
-        }\r
-        else {\r
-            roundIncrement = roundMask;\r
-            if ( zSign ) {\r
-                if ( roundingMode == float_round_up ) roundIncrement = 0;\r
-            }\r
-            else {\r
-                if ( roundingMode == float_round_down ) roundIncrement = 0;\r
-            }\r
-        }\r
-    }\r
-    roundBits = zSig0 & roundMask;\r
-    if ( 0x7FFD <= (bits32) ( zExp - 1 ) ) {\r
-        if (    ( 0x7FFE < zExp )\r
-             || ( ( zExp == 0x7FFE ) && ( zSig0 + roundIncrement < zSig0 ) )\r
-           ) {\r
-            goto overflow;\r
-        }\r
-        if ( zExp <= 0 ) {\r
-            isTiny =\r
-                   ( float_detect_tininess == float_tininess_before_rounding )\r
-                || ( zExp < 0 )\r
-                || ( zSig0 <= zSig0 + roundIncrement );\r
-            shift64RightJamming( zSig0, 1 - zExp, &zSig0 );\r
-            zExp = 0;\r
-            roundBits = zSig0 & roundMask;\r
-            if ( isTiny && roundBits ) float_raise( float_flag_underflow );\r
-            if ( roundBits ) float_exception_flags |= float_flag_inexact;\r
-            zSig0 += roundIncrement;\r
-            if ( (sbits64) zSig0 < 0 ) zExp = 1;\r
-            roundIncrement = roundMask + 1;\r
-            if ( roundNearestEven && ( roundBits<<1 == roundIncrement ) ) {\r
-                roundMask |= roundIncrement;\r
-            }\r
-            zSig0 &= ~ roundMask;\r
-            return packFloatx80( zSign, zExp, zSig0 );\r
-        }\r
-    }\r
-    if ( roundBits ) float_exception_flags |= float_flag_inexact;\r
-    zSig0 += roundIncrement;\r
-    if ( zSig0 < roundIncrement ) {\r
-        ++zExp;\r
-        zSig0 = LIT64( 0x8000000000000000 );\r
-    }\r
-    roundIncrement = roundMask + 1;\r
-    if ( roundNearestEven && ( roundBits<<1 == roundIncrement ) ) {\r
-        roundMask |= roundIncrement;\r
-    }\r
-    zSig0 &= ~ roundMask;\r
-    if ( zSig0 == 0 ) zExp = 0;\r
-    return packFloatx80( zSign, zExp, zSig0 );\r
- precision80:\r
-    increment = ( (sbits64) zSig1 < 0 );\r
-    if ( ! roundNearestEven ) {\r
-        if ( roundingMode == float_round_to_zero ) {\r
-            increment = 0;\r
-        }\r
-        else {\r
-            if ( zSign ) {\r
-                increment = ( roundingMode == float_round_down ) && zSig1;\r
-            }\r
-            else {\r
-                increment = ( roundingMode == float_round_up ) && zSig1;\r
-            }\r
-        }\r
-    }\r
-    if ( 0x7FFD <= (bits32) ( zExp - 1 ) ) {\r
-        if (    ( 0x7FFE < zExp )\r
-             || (    ( zExp == 0x7FFE )\r
-                  && ( zSig0 == LIT64( 0xFFFFFFFFFFFFFFFF ) )\r
-                  && increment\r
-                )\r
-           ) {\r
-            roundMask = 0;\r
- overflow:\r
-            float_raise( float_flag_overflow | float_flag_inexact );\r
-            if (    ( roundingMode == float_round_to_zero )\r
-                 || ( zSign && ( roundingMode == float_round_up ) )\r
-                 || ( ! zSign && ( roundingMode == float_round_down ) )\r
-               ) {\r
-                return packFloatx80( zSign, 0x7FFE, ~ roundMask );\r
-            }\r
-            return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );\r
-        }\r
-        if ( zExp <= 0 ) {\r
-            isTiny =\r
-                   ( float_detect_tininess == float_tininess_before_rounding )\r
-                || ( zExp < 0 )\r
-                || ! increment\r
-                || ( zSig0 < LIT64( 0xFFFFFFFFFFFFFFFF ) );\r
-            shift64ExtraRightJamming( zSig0, zSig1, 1 - zExp, &zSig0, &zSig1 );\r
-            zExp = 0;\r
-            if ( isTiny && zSig1 ) float_raise( float_flag_underflow );\r
-            if ( zSig1 ) float_exception_flags |= float_flag_inexact;\r
-            if ( roundNearestEven ) {\r
-                increment = ( (sbits64) zSig1 < 0 );\r
-            }\r
-            else {\r
-                if ( zSign ) {\r
-                    increment = ( roundingMode == float_round_down ) && zSig1;\r
-                }\r
-                else {\r
-                    increment = ( roundingMode == float_round_up ) && zSig1;\r
-                }\r
-            }\r
-            if ( increment ) {\r
-                ++zSig0;\r
-                zSig0 &=\r
-                    ~ ( ( (bits64) ( zSig1<<1 ) == 0 ) & roundNearestEven );\r
-                if ( (sbits64) zSig0 < 0 ) zExp = 1;\r
-            }\r
-            return packFloatx80( zSign, zExp, zSig0 );\r
-        }\r
-    }\r
-    if ( zSig1 ) float_exception_flags |= float_flag_inexact;\r
-    if ( increment ) {\r
-        ++zSig0;\r
-        if ( zSig0 == 0 ) {\r
-            ++zExp;\r
-            zSig0 = LIT64( 0x8000000000000000 );\r
-        }\r
-        else {\r
-            zSig0 &= ~ ( ( (bits64) ( zSig1<<1 ) == 0 ) & roundNearestEven );\r
-        }\r
-    }\r
-    else {\r
-        if ( zSig0 == 0 ) zExp = 0;\r
-    }\r
-    return packFloatx80( zSign, zExp, zSig0 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Takes an abstract floating-point value having sign `zSign', exponent\r
-| `zExp', and significand formed by the concatenation of `zSig0' and `zSig1',\r
-| and returns the proper extended double-precision floating-point value\r
-| corresponding to the abstract input.  This routine is just like\r
-| `roundAndPackFloatx80' except that the input significand does not have to be\r
-| normalized.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static floatx80\r
- normalizeRoundAndPackFloatx80(\r
-     int8 roundingPrecision, flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1\r
- )\r
-{\r
-    int8 shiftCount;\r
-\r
-    if ( zSig0 == 0 ) {\r
-        zSig0 = zSig1;\r
-        zSig1 = 0;\r
-        zExp -= 64;\r
-    }\r
-    shiftCount = countLeadingZeros64( zSig0 );\r
-    shortShift128Left( zSig0, zSig1, shiftCount, &zSig0, &zSig1 );\r
-    zExp -= shiftCount;\r
-    return\r
-        roundAndPackFloatx80( roundingPrecision, zSign, zExp, zSig0, zSig1 );\r
-\r
-}\r
-\r
-#endif\r
-\r
-#ifdef FLOAT128\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the least-significant 64 fraction bits of the quadruple-precision\r
-| floating-point value `a'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE bits64 extractFloat128Frac1( float128 a )\r
-{\r
-\r
-    return a.low;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the most-significant 48 fraction bits of the quadruple-precision\r
-| floating-point value `a'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE bits64 extractFloat128Frac0( float128 a )\r
-{\r
-\r
-    return a.high & LIT64( 0x0000FFFFFFFFFFFF );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the exponent bits of the quadruple-precision floating-point value\r
-| `a'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE int32 extractFloat128Exp( float128 a )\r
-{\r
-\r
-    return ( a.high>>48 ) & 0x7FFF;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the sign bit of the quadruple-precision floating-point value `a'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE flag extractFloat128Sign( float128 a )\r
-{\r
-\r
-    return a.high>>63;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Normalizes the subnormal quadruple-precision floating-point value\r
-| represented by the denormalized significand formed by the concatenation of\r
-| `aSig0' and `aSig1'.  The normalized exponent is stored at the location\r
-| pointed to by `zExpPtr'.  The most significant 49 bits of the normalized\r
-| significand are stored at the location pointed to by `zSig0Ptr', and the\r
-| least significant 64 bits of the normalized significand are stored at the\r
-| location pointed to by `zSig1Ptr'.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static void\r
- normalizeFloat128Subnormal(\r
-     bits64 aSig0,\r
-     bits64 aSig1,\r
-     int32 *zExpPtr,\r
-     bits64 *zSig0Ptr,\r
-     bits64 *zSig1Ptr\r
- )\r
-{\r
-    int8 shiftCount;\r
-\r
-    if ( aSig0 == 0 ) {\r
-        shiftCount = countLeadingZeros64( aSig1 ) - 15;\r
-        if ( shiftCount < 0 ) {\r
-            *zSig0Ptr = aSig1>>( - shiftCount );\r
-            *zSig1Ptr = aSig1<<( shiftCount & 63 );\r
-        }\r
-        else {\r
-            *zSig0Ptr = aSig1<<shiftCount;\r
-            *zSig1Ptr = 0;\r
-        }\r
-        *zExpPtr = - shiftCount - 63;\r
-    }\r
-    else {\r
-        shiftCount = countLeadingZeros64( aSig0 ) - 15;\r
-        shortShift128Left( aSig0, aSig1, shiftCount, zSig0Ptr, zSig1Ptr );\r
-        *zExpPtr = 1 - shiftCount;\r
-    }\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Packs the sign `zSign', the exponent `zExp', and the significand formed\r
-| by the concatenation of `zSig0' and `zSig1' into a quadruple-precision\r
-| floating-point value, returning the result.  After being shifted into the\r
-| proper positions, the three fields `zSign', `zExp', and `zSig0' are simply\r
-| added together to form the most significant 32 bits of the result.  This\r
-| means that any integer portion of `zSig0' will be added into the exponent.\r
-| Since a properly normalized significand will have an integer portion equal\r
-| to 1, the `zExp' input should be 1 less than the desired result exponent\r
-| whenever `zSig0' and `zSig1' concatenated form a complete, normalized\r
-| significand.\r
-*----------------------------------------------------------------------------*/\r
-\r
-INLINE float128\r
- packFloat128( flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1 )\r
-{\r
-    float128 z;\r
-\r
-    z.low = zSig1;\r
-    z.high = ( ( (bits64) zSign )<<63 ) + ( ( (bits64) zExp )<<48 ) + zSig0;\r
-    return z;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
-| and extended significand formed by the concatenation of `zSig0', `zSig1',\r
-| and `zSig2', and returns the proper quadruple-precision floating-point value\r
-| corresponding to the abstract input.  Ordinarily, the abstract value is\r
-| simply rounded and packed into the quadruple-precision format, with the\r
-| inexact exception raised if the abstract input cannot be represented\r
-| exactly.  However, if the abstract value is too large, the overflow and\r
-| inexact exceptions are raised and an infinity or maximal finite value is\r
-| returned.  If the abstract value is too small, the input value is rounded to\r
-| a subnormal number, and the underflow and inexact exceptions are raised if\r
-| the abstract input cannot be represented exactly as a subnormal quadruple-\r
-| precision floating-point number.\r
-|     The input significand must be normalized or smaller.  If the input\r
-| significand is not normalized, `zExp' must be 0; in that case, the result\r
-| returned is a subnormal number, and it must not require rounding.  In the\r
-| usual case that the input significand is normalized, `zExp' must be 1 less\r
-| than the ``true'' floating-point exponent.  The handling of underflow and\r
-| overflow follows the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static float128\r
- roundAndPackFloat128(\r
-     flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1, bits64 zSig2 )\r
-{\r
-    int8 roundingMode;\r
-    flag roundNearestEven, increment, isTiny;\r
-\r
-    roundingMode = float_rounding_mode;\r
-    roundNearestEven = ( roundingMode == float_round_nearest_even );\r
-    increment = ( (sbits64) zSig2 < 0 );\r
-    if ( ! roundNearestEven ) {\r
-        if ( roundingMode == float_round_to_zero ) {\r
-            increment = 0;\r
-        }\r
-        else {\r
-            if ( zSign ) {\r
-                increment = ( roundingMode == float_round_down ) && zSig2;\r
-            }\r
-            else {\r
-                increment = ( roundingMode == float_round_up ) && zSig2;\r
-            }\r
-        }\r
-    }\r
-    if ( 0x7FFD <= (bits32) zExp ) {\r
-        if (    ( 0x7FFD < zExp )\r
-             || (    ( zExp == 0x7FFD )\r
-                  && eq128(\r
-                         LIT64( 0x0001FFFFFFFFFFFF ),\r
-                         LIT64( 0xFFFFFFFFFFFFFFFF ),\r
-                         zSig0,\r
-                         zSig1\r
-                     )\r
-                  && increment\r
-                )\r
-           ) {\r
-            float_raise( float_flag_overflow | float_flag_inexact );\r
-            if (    ( roundingMode == float_round_to_zero )\r
-                 || ( zSign && ( roundingMode == float_round_up ) )\r
-                 || ( ! zSign && ( roundingMode == float_round_down ) )\r
-               ) {\r
-                return\r
-                    packFloat128(\r
-                        zSign,\r
-                        0x7FFE,\r
-                        LIT64( 0x0000FFFFFFFFFFFF ),\r
-                        LIT64( 0xFFFFFFFFFFFFFFFF )\r
-                    );\r
-            }\r
-            return packFloat128( zSign, 0x7FFF, 0, 0 );\r
-        }\r
-        if ( zExp < 0 ) {\r
-            isTiny =\r
-                   ( float_detect_tininess == float_tininess_before_rounding )\r
-                || ( zExp < -1 )\r
-                || ! increment\r
-                || lt128(\r
-                       zSig0,\r
-                       zSig1,\r
-                       LIT64( 0x0001FFFFFFFFFFFF ),\r
-                       LIT64( 0xFFFFFFFFFFFFFFFF )\r
-                   );\r
-            shift128ExtraRightJamming(\r
-                zSig0, zSig1, zSig2, - zExp, &zSig0, &zSig1, &zSig2 );\r
-            zExp = 0;\r
-            if ( isTiny && zSig2 ) float_raise( float_flag_underflow );\r
-            if ( roundNearestEven ) {\r
-                increment = ( (sbits64) zSig2 < 0 );\r
-            }\r
-            else {\r
-                if ( zSign ) {\r
-                    increment = ( roundingMode == float_round_down ) && zSig2;\r
-                }\r
-                else {\r
-                    increment = ( roundingMode == float_round_up ) && zSig2;\r
-                }\r
-            }\r
-        }\r
-    }\r
-    if ( zSig2 ) float_exception_flags |= float_flag_inexact;\r
-    if ( increment ) {\r
-        add128( zSig0, zSig1, 0, 1, &zSig0, &zSig1 );\r
-        zSig1 &= ~ ( ( zSig2 + zSig2 == 0 ) & roundNearestEven );\r
-    }\r
-    else {\r
-        if ( ( zSig0 | zSig1 ) == 0 ) zExp = 0;\r
-    }\r
-    return packFloat128( zSign, zExp, zSig0, zSig1 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Takes an abstract floating-point value having sign `zSign', exponent `zExp',\r
-| and significand formed by the concatenation of `zSig0' and `zSig1', and\r
-| returns the proper quadruple-precision floating-point value corresponding\r
-| to the abstract input.  This routine is just like `roundAndPackFloat128'\r
-| except that the input significand has fewer bits and does not have to be\r
-| normalized.  In all cases, `zExp' must be 1 less than the ``true'' floating-\r
-| point exponent.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static float128\r
- normalizeRoundAndPackFloat128(\r
-     flag zSign, int32 zExp, bits64 zSig0, bits64 zSig1 )\r
-{\r
-    int8 shiftCount;\r
-    bits64 zSig2;\r
-\r
-    if ( zSig0 == 0 ) {\r
-        zSig0 = zSig1;\r
-        zSig1 = 0;\r
-        zExp -= 64;\r
-    }\r
-    shiftCount = countLeadingZeros64( zSig0 ) - 15;\r
-    if ( 0 <= shiftCount ) {\r
-        zSig2 = 0;\r
-        shortShift128Left( zSig0, zSig1, shiftCount, &zSig0, &zSig1 );\r
-    }\r
-    else {\r
-        shift128ExtraRightJamming(\r
-            zSig0, zSig1, 0, - shiftCount, &zSig0, &zSig1, &zSig2 );\r
-    }\r
-    zExp -= shiftCount;\r
-    return roundAndPackFloat128( zSign, zExp, zSig0, zSig1, zSig2 );\r
-\r
-}\r
-\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the 32-bit two's complement integer `a'\r
-| to the single-precision floating-point format.  The conversion is performed\r
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float32 int32_to_float32( int32 a )\r
-{\r
-    flag zSign;\r
-\r
-    if ( a == 0 ) return 0;\r
-    if ( a == (sbits32) 0x80000000 ) return packFloat32( 1, 0x9E, 0 );\r
-    zSign = ( a < 0 );\r
-    return normalizeRoundAndPackFloat32( zSign, 0x9C, zSign ? - a : a );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the 32-bit two's complement integer `a'\r
-| to the double-precision floating-point format.  The conversion is performed\r
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float64 int32_to_float64( int32 a )\r
-{\r
-    flag zSign;\r
-    uint32 absA;\r
-    int8 shiftCount;\r
-    bits64 zSig;\r
-\r
-    if ( a == 0 ) return 0;\r
-    zSign = ( a < 0 );\r
-    absA = zSign ? - a : a;\r
-    shiftCount = countLeadingZeros32( absA ) + 21;\r
-    zSig = absA;\r
-    return packFloat64( zSign, 0x432 - shiftCount, zSig<<shiftCount );\r
-\r
-}\r
-\r
-#ifdef FLOATX80\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the 32-bit two's complement integer `a'\r
-| to the extended double-precision floating-point format.  The conversion\r
-| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-floatx80 int32_to_floatx80( int32 a )\r
-{\r
-    flag zSign;\r
-    uint32 absA;\r
-    int8 shiftCount;\r
-    bits64 zSig;\r
-\r
-    if ( a == 0 ) return packFloatx80( 0, 0, 0 );\r
-    zSign = ( a < 0 );\r
-    absA = zSign ? - a : a;\r
-    shiftCount = countLeadingZeros32( absA ) + 32;\r
-    zSig = absA;\r
-    return packFloatx80( zSign, 0x403E - shiftCount, zSig<<shiftCount );\r
-\r
-}\r
-\r
-#endif\r
-\r
-#ifdef FLOAT128\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the 32-bit two's complement integer `a' to\r
-| the quadruple-precision floating-point format.  The conversion is performed\r
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float128 int32_to_float128( int32 a )\r
-{\r
-    flag zSign;\r
-    uint32 absA;\r
-    int8 shiftCount;\r
-    bits64 zSig0;\r
-\r
-    if ( a == 0 ) return packFloat128( 0, 0, 0, 0 );\r
-    zSign = ( a < 0 );\r
-    absA = zSign ? - a : a;\r
-    shiftCount = countLeadingZeros32( absA ) + 17;\r
-    zSig0 = absA;\r
-    return packFloat128( zSign, 0x402E - shiftCount, zSig0<<shiftCount, 0 );\r
-\r
-}\r
-\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the 64-bit two's complement integer `a'\r
-| to the single-precision floating-point format.  The conversion is performed\r
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float32 int64_to_float32( int64 a )\r
-{\r
-    flag zSign;\r
-    uint64 absA;\r
-    int8 shiftCount;\r
-    bits32 zSig;\r
-\r
-    if ( a == 0 ) return 0;\r
-    zSign = ( a < 0 );\r
-    absA = zSign ? - a : a;\r
-    shiftCount = countLeadingZeros64( absA ) - 40;\r
-    if ( 0 <= shiftCount ) {\r
-        return packFloat32( zSign, 0x95 - shiftCount, absA<<shiftCount );\r
-    }\r
-    else {\r
-        shiftCount += 7;\r
-        if ( shiftCount < 0 ) {\r
-            shift64RightJamming( absA, - shiftCount, &absA );\r
-        }\r
-        else {\r
-            absA <<= shiftCount;\r
-        }\r
-        return roundAndPackFloat32( zSign, 0x9C - shiftCount, absA );\r
-    }\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the 64-bit two's complement integer `a'\r
-| to the double-precision floating-point format.  The conversion is performed\r
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float64 int64_to_float64( int64 a )\r
-{\r
-    flag zSign;\r
-\r
-    if ( a == 0 ) return 0;\r
-    if ( a == (sbits64) LIT64( 0x8000000000000000 ) ) {\r
-        return packFloat64( 1, 0x43E, 0 );\r
-    }\r
-    zSign = ( a < 0 );\r
-    return normalizeRoundAndPackFloat64( zSign, 0x43C, zSign ? - a : a );\r
-\r
-}\r
-\r
-#ifdef FLOATX80\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the 64-bit two's complement integer `a'\r
-| to the extended double-precision floating-point format.  The conversion\r
-| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-floatx80 int64_to_floatx80( int64 a )\r
-{\r
-    flag zSign;\r
-    uint64 absA;\r
-    int8 shiftCount;\r
-\r
-    if ( a == 0 ) return packFloatx80( 0, 0, 0 );\r
-    zSign = ( a < 0 );\r
-    absA = zSign ? - a : a;\r
-    shiftCount = countLeadingZeros64( absA );\r
-    return packFloatx80( zSign, 0x403E - shiftCount, absA<<shiftCount );\r
-\r
-}\r
-\r
-#endif\r
-\r
-#ifdef FLOAT128\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the 64-bit two's complement integer `a' to\r
-| the quadruple-precision floating-point format.  The conversion is performed\r
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float128 int64_to_float128( int64 a )\r
-{\r
-    flag zSign;\r
-    uint64 absA;\r
-    int8 shiftCount;\r
-    int32 zExp;\r
-    bits64 zSig0, zSig1;\r
-\r
-    if ( a == 0 ) return packFloat128( 0, 0, 0, 0 );\r
-    zSign = ( a < 0 );\r
-    absA = zSign ? - a : a;\r
-    shiftCount = countLeadingZeros64( absA ) + 49;\r
-    zExp = 0x406E - shiftCount;\r
-    if ( 64 <= shiftCount ) {\r
-        zSig1 = 0;\r
-        zSig0 = absA;\r
-        shiftCount -= 64;\r
-    }\r
-    else {\r
-        zSig1 = absA;\r
-        zSig0 = 0;\r
-    }\r
-    shortShift128Left( zSig0, zSig1, shiftCount, &zSig0, &zSig1 );\r
-    return packFloat128( zSign, zExp, zSig0, zSig1 );\r
-\r
-}\r
-\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the single-precision floating-point value\r
-| `a' to the 32-bit two's complement integer format.  The conversion is\r
-| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic---which means in particular that the conversion is rounded\r
-| according to the current rounding mode.  If `a' is a NaN, the largest\r
-| positive integer is returned.  Otherwise, if the conversion overflows, the\r
-| largest integer with the same sign as `a' is returned.\r
-*----------------------------------------------------------------------------*/\r
-\r
-int32 float32_to_int32( float32 a )\r
-{\r
-    flag aSign;\r
-    int16 aExp, shiftCount;\r
-    bits32 aSig;\r
-    bits64 aSig64;\r
-\r
-    aSig = extractFloat32Frac( a );\r
-    aExp = extractFloat32Exp( a );\r
-    aSign = extractFloat32Sign( a );\r
-    if ( ( aExp == 0xFF ) && aSig ) aSign = 0;\r
-    if ( aExp ) aSig |= 0x00800000;\r
-    shiftCount = 0xAF - aExp;\r
-    aSig64 = aSig;\r
-    aSig64 <<= 32;\r
-    if ( 0 < shiftCount ) shift64RightJamming( aSig64, shiftCount, &aSig64 );\r
-    return roundAndPackInt32( aSign, aSig64 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the single-precision floating-point value\r
-| `a' to the 32-bit two's complement integer format.  The conversion is\r
-| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic, except that the conversion is always rounded toward zero.\r
-| If `a' is a NaN, the largest positive integer is returned.  Otherwise, if\r
-| the conversion overflows, the largest integer with the same sign as `a' is\r
-| returned.\r
-*----------------------------------------------------------------------------*/\r
-\r
-int32 float32_to_int32_round_to_zero( float32 a )\r
-{\r
-    flag aSign;\r
-    int16 aExp, shiftCount;\r
-    bits32 aSig;\r
-    int32 z;\r
-\r
-    aSig = extractFloat32Frac( a );\r
-    aExp = extractFloat32Exp( a );\r
-    aSign = extractFloat32Sign( a );\r
-    shiftCount = aExp - 0x9E;\r
-    if ( 0 <= shiftCount ) {\r
-        if ( a != 0xCF000000 ) {\r
-            float_raise( float_flag_invalid );\r
-            if ( ! aSign || ( ( aExp == 0xFF ) && aSig ) ) return 0x7FFFFFFF;\r
-        }\r
-        return (sbits32) 0x80000000;\r
-    }\r
-    else if ( aExp <= 0x7E ) {\r
-        if ( aExp | aSig ) float_exception_flags |= float_flag_inexact;\r
-        return 0;\r
-    }\r
-    aSig = ( aSig | 0x00800000 )<<8;\r
-    z = aSig>>( - shiftCount );\r
-    if ( (bits32) ( aSig<<( shiftCount & 31 ) ) ) {\r
-        float_exception_flags |= float_flag_inexact;\r
-    }\r
-    if ( aSign ) z = - z;\r
-    return z;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the single-precision floating-point value\r
-| `a' to the 64-bit two's complement integer format.  The conversion is\r
-| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic---which means in particular that the conversion is rounded\r
-| according to the current rounding mode.  If `a' is a NaN, the largest\r
-| positive integer is returned.  Otherwise, if the conversion overflows, the\r
-| largest integer with the same sign as `a' is returned.\r
-*----------------------------------------------------------------------------*/\r
-\r
-int64 float32_to_int64( float32 a )\r
-{\r
-    flag aSign;\r
-    int16 aExp, shiftCount;\r
-    bits32 aSig;\r
-    bits64 aSig64, aSigExtra;\r
-\r
-    aSig = extractFloat32Frac( a );\r
-    aExp = extractFloat32Exp( a );\r
-    aSign = extractFloat32Sign( a );\r
-    shiftCount = 0xBE - aExp;\r
-    if ( shiftCount < 0 ) {\r
-        float_raise( float_flag_invalid );\r
-        if ( ! aSign || ( ( aExp == 0xFF ) && aSig ) ) {\r
-            return LIT64( 0x7FFFFFFFFFFFFFFF );\r
-        }\r
-        return (sbits64) LIT64( 0x8000000000000000 );\r
-    }\r
-    if ( aExp ) aSig |= 0x00800000;\r
-    aSig64 = aSig;\r
-    aSig64 <<= 40;\r
-    shift64ExtraRightJamming( aSig64, 0, shiftCount, &aSig64, &aSigExtra );\r
-    return roundAndPackInt64( aSign, aSig64, aSigExtra );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the single-precision floating-point value\r
-| `a' to the 64-bit two's complement integer format.  The conversion is\r
-| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic, except that the conversion is always rounded toward zero.  If\r
-| `a' is a NaN, the largest positive integer is returned.  Otherwise, if the\r
-| conversion overflows, the largest integer with the same sign as `a' is\r
-| returned.\r
-*----------------------------------------------------------------------------*/\r
-\r
-int64 float32_to_int64_round_to_zero( float32 a )\r
-{\r
-    flag aSign;\r
-    int16 aExp, shiftCount;\r
-    bits32 aSig;\r
-    bits64 aSig64;\r
-    int64 z;\r
-\r
-    aSig = extractFloat32Frac( a );\r
-    aExp = extractFloat32Exp( a );\r
-    aSign = extractFloat32Sign( a );\r
-    shiftCount = aExp - 0xBE;\r
-    if ( 0 <= shiftCount ) {\r
-        if ( a != 0xDF000000 ) {\r
-            float_raise( float_flag_invalid );\r
-            if ( ! aSign || ( ( aExp == 0xFF ) && aSig ) ) {\r
-                return LIT64( 0x7FFFFFFFFFFFFFFF );\r
-            }\r
-        }\r
-        return (sbits64) LIT64( 0x8000000000000000 );\r
-    }\r
-    else if ( aExp <= 0x7E ) {\r
-        if ( aExp | aSig ) float_exception_flags |= float_flag_inexact;\r
-        return 0;\r
-    }\r
-    aSig64 = aSig | 0x00800000;\r
-    aSig64 <<= 40;\r
-    z = aSig64>>( - shiftCount );\r
-    if ( (bits64) ( aSig64<<( shiftCount & 63 ) ) ) {\r
-        float_exception_flags |= float_flag_inexact;\r
-    }\r
-    if ( aSign ) z = - z;\r
-    return z;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the single-precision floating-point value\r
-| `a' to the double-precision floating-point format.  The conversion is\r
-| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float64 float32_to_float64( float32 a )\r
-{\r
-    flag aSign;\r
-    int16 aExp;\r
-    bits32 aSig;\r
-\r
-    aSig = extractFloat32Frac( a );\r
-    aExp = extractFloat32Exp( a );\r
-    aSign = extractFloat32Sign( a );\r
-    if ( aExp == 0xFF ) {\r
-        if ( aSig ) return commonNaNToFloat64( float32ToCommonNaN( a ) );\r
-        return packFloat64( aSign, 0x7FF, 0 );\r
-    }\r
-    if ( aExp == 0 ) {\r
-        if ( aSig == 0 ) return packFloat64( aSign, 0, 0 );\r
-        normalizeFloat32Subnormal( aSig, &aExp, &aSig );\r
-        --aExp;\r
-    }\r
-    return packFloat64( aSign, aExp + 0x380, ( (bits64) aSig )<<29 );\r
-\r
-}\r
-\r
-#ifdef FLOATX80\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the single-precision floating-point value\r
-| `a' to the extended double-precision floating-point format.  The conversion\r
-| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-floatx80 float32_to_floatx80( float32 a )\r
-{\r
-    flag aSign;\r
-    int16 aExp;\r
-    bits32 aSig;\r
-\r
-    aSig = extractFloat32Frac( a );\r
-    aExp = extractFloat32Exp( a );\r
-    aSign = extractFloat32Sign( a );\r
-    if ( aExp == 0xFF ) {\r
-        if ( aSig ) return commonNaNToFloatx80( float32ToCommonNaN( a ) );\r
-        return packFloatx80( aSign, 0x7FFF, LIT64( 0x8000000000000000 ) );\r
-    }\r
-    if ( aExp == 0 ) {\r
-        if ( aSig == 0 ) return packFloatx80( aSign, 0, 0 );\r
-        normalizeFloat32Subnormal( aSig, &aExp, &aSig );\r
-    }\r
-    aSig |= 0x00800000;\r
-    return packFloatx80( aSign, aExp + 0x3F80, ( (bits64) aSig )<<40 );\r
-\r
-}\r
-\r
-#endif\r
-\r
-#ifdef FLOAT128\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the single-precision floating-point value\r
-| `a' to the double-precision floating-point format.  The conversion is\r
-| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float128 float32_to_float128( float32 a )\r
-{\r
-    flag aSign;\r
-    int16 aExp;\r
-    bits32 aSig;\r
-\r
-    aSig = extractFloat32Frac( a );\r
-    aExp = extractFloat32Exp( a );\r
-    aSign = extractFloat32Sign( a );\r
-    if ( aExp == 0xFF ) {\r
-        if ( aSig ) return commonNaNToFloat128( float32ToCommonNaN( a ) );\r
-        return packFloat128( aSign, 0x7FFF, 0, 0 );\r
-    }\r
-    if ( aExp == 0 ) {\r
-        if ( aSig == 0 ) return packFloat128( aSign, 0, 0, 0 );\r
-        normalizeFloat32Subnormal( aSig, &aExp, &aSig );\r
-        --aExp;\r
-    }\r
-    return packFloat128( aSign, aExp + 0x3F80, ( (bits64) aSig )<<25, 0 );\r
-\r
-}\r
-\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------\r
-| Rounds the single-precision floating-point value `a' to an integer, and\r
-| returns the result as a single-precision floating-point value.  The\r
-| operation is performed according to the IEC/IEEE Standard for Binary\r
-| Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float32 float32_round_to_int( float32 a )\r
-{\r
-    flag aSign;\r
-    int16 aExp;\r
-    bits32 lastBitMask, roundBitsMask;\r
-    int8 roundingMode;\r
-    float32 z;\r
-\r
-    aExp = extractFloat32Exp( a );\r
-    if ( 0x96 <= aExp ) {\r
-        if ( ( aExp == 0xFF ) && extractFloat32Frac( a ) ) {\r
-            return propagateFloat32NaN( a, a );\r
-        }\r
-        return a;\r
-    }\r
-    if ( aExp <= 0x7E ) {\r
-        if ( (bits32) ( a<<1 ) == 0 ) return a;\r
-        float_exception_flags |= float_flag_inexact;\r
-        aSign = extractFloat32Sign( a );\r
-        switch ( float_rounding_mode ) {\r
-         case float_round_nearest_even:\r
-            if ( ( aExp == 0x7E ) && extractFloat32Frac( a ) ) {\r
-                return packFloat32( aSign, 0x7F, 0 );\r
-            }\r
-            break;\r
-         case float_round_down:\r
-            return aSign ? 0xBF800000 : 0;\r
-         case float_round_up:\r
-            return aSign ? 0x80000000 : 0x3F800000;\r
-        }\r
-        return packFloat32( aSign, 0, 0 );\r
-    }\r
-    lastBitMask = 1;\r
-    lastBitMask <<= 0x96 - aExp;\r
-    roundBitsMask = lastBitMask - 1;\r
-    z = a;\r
-    roundingMode = float_rounding_mode;\r
-    if ( roundingMode == float_round_nearest_even ) {\r
-        z += lastBitMask>>1;\r
-        if ( ( z & roundBitsMask ) == 0 ) z &= ~ lastBitMask;\r
-    }\r
-    else if ( roundingMode != float_round_to_zero ) {\r
-        if ( extractFloat32Sign( z ) ^ ( roundingMode == float_round_up ) ) {\r
-            z += roundBitsMask;\r
-        }\r
-    }\r
-    z &= ~ roundBitsMask;\r
-    if ( z != a ) float_exception_flags |= float_flag_inexact;\r
-    return z;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of adding the absolute values of the single-precision\r
-| floating-point values `a' and `b'.  If `zSign' is 1, the sum is negated\r
-| before being returned.  `zSign' is ignored if the result is a NaN.\r
-| The addition is performed according to the IEC/IEEE Standard for Binary\r
-| Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static float32 addFloat32Sigs( float32 a, float32 b, flag zSign )\r
-{\r
-    int16 aExp, bExp, zExp;\r
-    bits32 aSig, bSig, zSig;\r
-    int16 expDiff;\r
-\r
-    aSig = extractFloat32Frac( a );\r
-    aExp = extractFloat32Exp( a );\r
-    bSig = extractFloat32Frac( b );\r
-    bExp = extractFloat32Exp( b );\r
-    expDiff = aExp - bExp;\r
-    aSig <<= 6;\r
-    bSig <<= 6;\r
-    if ( 0 < expDiff ) {\r
-        if ( aExp == 0xFF ) {\r
-            if ( aSig ) return propagateFloat32NaN( a, b );\r
-            return a;\r
-        }\r
-        if ( bExp == 0 ) {\r
-            --expDiff;\r
-        }\r
-        else {\r
-            bSig |= 0x20000000;\r
-        }\r
-        shift32RightJamming( bSig, expDiff, &bSig );\r
-        zExp = aExp;\r
-    }\r
-    else if ( expDiff < 0 ) {\r
-        if ( bExp == 0xFF ) {\r
-            if ( bSig ) return propagateFloat32NaN( a, b );\r
-            return packFloat32( zSign, 0xFF, 0 );\r
-        }\r
-        if ( aExp == 0 ) {\r
-            ++expDiff;\r
-        }\r
-        else {\r
-            aSig |= 0x20000000;\r
-        }\r
-        shift32RightJamming( aSig, - expDiff, &aSig );\r
-        zExp = bExp;\r
-    }\r
-    else {\r
-        if ( aExp == 0xFF ) {\r
-            if ( aSig | bSig ) return propagateFloat32NaN( a, b );\r
-            return a;\r
-        }\r
-        if ( aExp == 0 ) return packFloat32( zSign, 0, ( aSig + bSig )>>6 );\r
-        zSig = 0x40000000 + aSig + bSig;\r
-        zExp = aExp;\r
-        goto roundAndPack;\r
-    }\r
-    aSig |= 0x20000000;\r
-    zSig = ( aSig + bSig )<<1;\r
-    --zExp;\r
-    if ( (sbits32) zSig < 0 ) {\r
-        zSig = aSig + bSig;\r
-        ++zExp;\r
-    }\r
- roundAndPack:\r
-    return roundAndPackFloat32( zSign, zExp, zSig );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of subtracting the absolute values of the single-\r
-| precision floating-point values `a' and `b'.  If `zSign' is 1, the\r
-| difference is negated before being returned.  `zSign' is ignored if the\r
-| result is a NaN.  The subtraction is performed according to the IEC/IEEE\r
-| Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static float32 subFloat32Sigs( float32 a, float32 b, flag zSign )\r
-{\r
-    int16 aExp, bExp, zExp;\r
-    bits32 aSig, bSig, zSig;\r
-    int16 expDiff;\r
-\r
-    aSig = extractFloat32Frac( a );\r
-    aExp = extractFloat32Exp( a );\r
-    bSig = extractFloat32Frac( b );\r
-    bExp = extractFloat32Exp( b );\r
-    expDiff = aExp - bExp;\r
-    aSig <<= 7;\r
-    bSig <<= 7;\r
-    if ( 0 < expDiff ) goto aExpBigger;\r
-    if ( expDiff < 0 ) goto bExpBigger;\r
-    if ( aExp == 0xFF ) {\r
-        if ( aSig | bSig ) return propagateFloat32NaN( a, b );\r
-        float_raise( float_flag_invalid );\r
-        return float32_default_nan;\r
-    }\r
-    if ( aExp == 0 ) {\r
-        aExp = 1;\r
-        bExp = 1;\r
-    }\r
-    if ( bSig < aSig ) goto aBigger;\r
-    if ( aSig < bSig ) goto bBigger;\r
-    return packFloat32( float_rounding_mode == float_round_down, 0, 0 );\r
- bExpBigger:\r
-    if ( bExp == 0xFF ) {\r
-        if ( bSig ) return propagateFloat32NaN( a, b );\r
-        return packFloat32( zSign ^ 1, 0xFF, 0 );\r
-    }\r
-    if ( aExp == 0 ) {\r
-        ++expDiff;\r
-    }\r
-    else {\r
-        aSig |= 0x40000000;\r
-    }\r
-    shift32RightJamming( aSig, - expDiff, &aSig );\r
-    bSig |= 0x40000000;\r
- bBigger:\r
-    zSig = bSig - aSig;\r
-    zExp = bExp;\r
-    zSign ^= 1;\r
-    goto normalizeRoundAndPack;\r
- aExpBigger:\r
-    if ( aExp == 0xFF ) {\r
-        if ( aSig ) return propagateFloat32NaN( a, b );\r
-        return a;\r
-    }\r
-    if ( bExp == 0 ) {\r
-        --expDiff;\r
-    }\r
-    else {\r
-        bSig |= 0x40000000;\r
-    }\r
-    shift32RightJamming( bSig, expDiff, &bSig );\r
-    aSig |= 0x40000000;\r
- aBigger:\r
-    zSig = aSig - bSig;\r
-    zExp = aExp;\r
- normalizeRoundAndPack:\r
-    --zExp;\r
-    return normalizeRoundAndPackFloat32( zSign, zExp, zSig );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of adding the single-precision floating-point values `a'\r
-| and `b'.  The operation is performed according to the IEC/IEEE Standard for\r
-| Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float32 float32_add( float32 a, float32 b )\r
-{\r
-    flag aSign, bSign;\r
-\r
-    aSign = extractFloat32Sign( a );\r
-    bSign = extractFloat32Sign( b );\r
-    if ( aSign == bSign ) {\r
-        return addFloat32Sigs( a, b, aSign );\r
-    }\r
-    else {\r
-        return subFloat32Sigs( a, b, aSign );\r
-    }\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of subtracting the single-precision floating-point values\r
-| `a' and `b'.  The operation is performed according to the IEC/IEEE Standard\r
-| for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float32 float32_sub( float32 a, float32 b )\r
-{\r
-    flag aSign, bSign;\r
-\r
-    aSign = extractFloat32Sign( a );\r
-    bSign = extractFloat32Sign( b );\r
-    if ( aSign == bSign ) {\r
-        return subFloat32Sigs( a, b, aSign );\r
-    }\r
-    else {\r
-        return addFloat32Sigs( a, b, aSign );\r
-    }\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of multiplying the single-precision floating-point values\r
-| `a' and `b'.  The operation is performed according to the IEC/IEEE Standard\r
-| for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float32 float32_mul( float32 a, float32 b )\r
-{\r
-    flag aSign, bSign, zSign;\r
-    int16 aExp, bExp, zExp;\r
-    bits32 aSig, bSig;\r
-    bits64 zSig64;\r
-    bits32 zSig;\r
-\r
-    aSig = extractFloat32Frac( a );\r
-    aExp = extractFloat32Exp( a );\r
-    aSign = extractFloat32Sign( a );\r
-    bSig = extractFloat32Frac( b );\r
-    bExp = extractFloat32Exp( b );\r
-    bSign = extractFloat32Sign( b );\r
-    zSign = aSign ^ bSign;\r
-    if ( aExp == 0xFF ) {\r
-        if ( aSig || ( ( bExp == 0xFF ) && bSig ) ) {\r
-            return propagateFloat32NaN( a, b );\r
-        }\r
-        if ( ( bExp | bSig ) == 0 ) {\r
-            float_raise( float_flag_invalid );\r
-            return float32_default_nan;\r
-        }\r
-        return packFloat32( zSign, 0xFF, 0 );\r
-    }\r
-    if ( bExp == 0xFF ) {\r
-        if ( bSig ) return propagateFloat32NaN( a, b );\r
-        if ( ( aExp | aSig ) == 0 ) {\r
-            float_raise( float_flag_invalid );\r
-            return float32_default_nan;\r
-        }\r
-        return packFloat32( zSign, 0xFF, 0 );\r
-    }\r
-    if ( aExp == 0 ) {\r
-        if ( aSig == 0 ) return packFloat32( zSign, 0, 0 );\r
-        normalizeFloat32Subnormal( aSig, &aExp, &aSig );\r
-    }\r
-    if ( bExp == 0 ) {\r
-        if ( bSig == 0 ) return packFloat32( zSign, 0, 0 );\r
-        normalizeFloat32Subnormal( bSig, &bExp, &bSig );\r
-    }\r
-    zExp = aExp + bExp - 0x7F;\r
-    aSig = ( aSig | 0x00800000 )<<7;\r
-    bSig = ( bSig | 0x00800000 )<<8;\r
-    shift64RightJamming( ( (bits64) aSig ) * bSig, 32, &zSig64 );\r
-    zSig = zSig64;\r
-    if ( 0 <= (sbits32) ( zSig<<1 ) ) {\r
-        zSig <<= 1;\r
-        --zExp;\r
-    }\r
-    return roundAndPackFloat32( zSign, zExp, zSig );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of dividing the single-precision floating-point value `a'\r
-| by the corresponding value `b'.  The operation is performed according to the\r
-| IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float32 float32_div( float32 a, float32 b )\r
-{\r
-    flag aSign, bSign, zSign;\r
-    int16 aExp, bExp, zExp;\r
-    bits32 aSig, bSig, zSig;\r
-\r
-    aSig = extractFloat32Frac( a );\r
-    aExp = extractFloat32Exp( a );\r
-    aSign = extractFloat32Sign( a );\r
-    bSig = extractFloat32Frac( b );\r
-    bExp = extractFloat32Exp( b );\r
-    bSign = extractFloat32Sign( b );\r
-    zSign = aSign ^ bSign;\r
-    if ( aExp == 0xFF ) {\r
-        if ( aSig ) return propagateFloat32NaN( a, b );\r
-        if ( bExp == 0xFF ) {\r
-            if ( bSig ) return propagateFloat32NaN( a, b );\r
-            float_raise( float_flag_invalid );\r
-            return float32_default_nan;\r
-        }\r
-        return packFloat32( zSign, 0xFF, 0 );\r
-    }\r
-    if ( bExp == 0xFF ) {\r
-        if ( bSig ) return propagateFloat32NaN( a, b );\r
-        return packFloat32( zSign, 0, 0 );\r
-    }\r
-    if ( bExp == 0 ) {\r
-        if ( bSig == 0 ) {\r
-            if ( ( aExp | aSig ) == 0 ) {\r
-                float_raise( float_flag_invalid );\r
-                return float32_default_nan;\r
-            }\r
-            float_raise( float_flag_divbyzero );\r
-            return packFloat32( zSign, 0xFF, 0 );\r
-        }\r
-        normalizeFloat32Subnormal( bSig, &bExp, &bSig );\r
-    }\r
-    if ( aExp == 0 ) {\r
-        if ( aSig == 0 ) return packFloat32( zSign, 0, 0 );\r
-        normalizeFloat32Subnormal( aSig, &aExp, &aSig );\r
-    }\r
-    zExp = aExp - bExp + 0x7D;\r
-    aSig = ( aSig | 0x00800000 )<<7;\r
-    bSig = ( bSig | 0x00800000 )<<8;\r
-    if ( bSig <= ( aSig + aSig ) ) {\r
-        aSig >>= 1;\r
-        ++zExp;\r
-    }\r
-    zSig = ( ( (bits64) aSig )<<32 ) / bSig;\r
-    if ( ( zSig & 0x3F ) == 0 ) {\r
-        zSig |= ( (bits64) bSig * zSig != ( (bits64) aSig )<<32 );\r
-    }\r
-    return roundAndPackFloat32( zSign, zExp, zSig );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the remainder of the single-precision floating-point value `a'\r
-| with respect to the corresponding value `b'.  The operation is performed\r
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float32 float32_rem( float32 a, float32 b )\r
-{\r
-    flag aSign, bSign, zSign;\r
-    int16 aExp, bExp, expDiff;\r
-    bits32 aSig, bSig;\r
-    bits32 q;\r
-    bits64 aSig64, bSig64, q64;\r
-    bits32 alternateASig;\r
-    sbits32 sigMean;\r
-\r
-    aSig = extractFloat32Frac( a );\r
-    aExp = extractFloat32Exp( a );\r
-    aSign = extractFloat32Sign( a );\r
-    bSig = extractFloat32Frac( b );\r
-    bExp = extractFloat32Exp( b );\r
-    bSign = extractFloat32Sign( b );\r
-    if ( aExp == 0xFF ) {\r
-        if ( aSig || ( ( bExp == 0xFF ) && bSig ) ) {\r
-            return propagateFloat32NaN( a, b );\r
-        }\r
-        float_raise( float_flag_invalid );\r
-        return float32_default_nan;\r
-    }\r
-    if ( bExp == 0xFF ) {\r
-        if ( bSig ) return propagateFloat32NaN( a, b );\r
-        return a;\r
-    }\r
-    if ( bExp == 0 ) {\r
-        if ( bSig == 0 ) {\r
-            float_raise( float_flag_invalid );\r
-            return float32_default_nan;\r
-        }\r
-        normalizeFloat32Subnormal( bSig, &bExp, &bSig );\r
-    }\r
-    if ( aExp == 0 ) {\r
-        if ( aSig == 0 ) return a;\r
-        normalizeFloat32Subnormal( aSig, &aExp, &aSig );\r
-    }\r
-    expDiff = aExp - bExp;\r
-    aSig |= 0x00800000;\r
-    bSig |= 0x00800000;\r
-    if ( expDiff < 32 ) {\r
-        aSig <<= 8;\r
-        bSig <<= 8;\r
-        if ( expDiff < 0 ) {\r
-            if ( expDiff < -1 ) return a;\r
-            aSig >>= 1;\r
-        }\r
-        q = ( bSig <= aSig );\r
-        if ( q ) aSig -= bSig;\r
-        if ( 0 < expDiff ) {\r
-            q = ( ( (bits64) aSig )<<32 ) / bSig;\r
-            q >>= 32 - expDiff;\r
-            bSig >>= 2;\r
-            aSig = ( ( aSig>>1 )<<( expDiff - 1 ) ) - bSig * q;\r
-        }\r
-        else {\r
-            aSig >>= 2;\r
-            bSig >>= 2;\r
-        }\r
-    }\r
-    else {\r
-        if ( bSig <= aSig ) aSig -= bSig;\r
-        aSig64 = ( (bits64) aSig )<<40;\r
-        bSig64 = ( (bits64) bSig )<<40;\r
-        expDiff -= 64;\r
-        while ( 0 < expDiff ) {\r
-            q64 = estimateDiv128To64( aSig64, 0, bSig64 );\r
-            q64 = ( 2 < q64 ) ? q64 - 2 : 0;\r
-            aSig64 = - ( ( bSig * q64 )<<38 );\r
-            expDiff -= 62;\r
-        }\r
-        expDiff += 64;\r
-        q64 = estimateDiv128To64( aSig64, 0, bSig64 );\r
-        q64 = ( 2 < q64 ) ? q64 - 2 : 0;\r
-        q = q64>>( 64 - expDiff );\r
-        bSig <<= 6;\r
-        aSig = ( ( aSig64>>33 )<<( expDiff - 1 ) ) - bSig * q;\r
-    }\r
-    do {\r
-        alternateASig = aSig;\r
-        ++q;\r
-        aSig -= bSig;\r
-    } while ( 0 <= (sbits32) aSig );\r
-    sigMean = aSig + alternateASig;\r
-    if ( ( sigMean < 0 ) || ( ( sigMean == 0 ) && ( q & 1 ) ) ) {\r
-        aSig = alternateASig;\r
-    }\r
-    zSign = ( (sbits32) aSig < 0 );\r
-    if ( zSign ) aSig = - aSig;\r
-    return normalizeRoundAndPackFloat32( aSign ^ zSign, bExp, aSig );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the square root of the single-precision floating-point value `a'.\r
-| The operation is performed according to the IEC/IEEE Standard for Binary\r
-| Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float32 float32_sqrt( float32 a )\r
-{\r
-    flag aSign;\r
-    int16 aExp, zExp;\r
-    bits32 aSig, zSig;\r
-    bits64 rem, term;\r
-\r
-    aSig = extractFloat32Frac( a );\r
-    aExp = extractFloat32Exp( a );\r
-    aSign = extractFloat32Sign( a );\r
-    if ( aExp == 0xFF ) {\r
-        if ( aSig ) return propagateFloat32NaN( a, 0 );\r
-        if ( ! aSign ) return a;\r
-        float_raise( float_flag_invalid );\r
-        return float32_default_nan;\r
-    }\r
-    if ( aSign ) {\r
-        if ( ( aExp | aSig ) == 0 ) return a;\r
-        float_raise( float_flag_invalid );\r
-        return float32_default_nan;\r
-    }\r
-    if ( aExp == 0 ) {\r
-        if ( aSig == 0 ) return 0;\r
-        normalizeFloat32Subnormal( aSig, &aExp, &aSig );\r
-    }\r
-    zExp = ( ( aExp - 0x7F )>>1 ) + 0x7E;\r
-    aSig = ( aSig | 0x00800000 )<<8;\r
-    zSig = estimateSqrt32( aExp, aSig ) + 2;\r
-    if ( ( zSig & 0x7F ) <= 5 ) {\r
-        if ( zSig < 2 ) {\r
-            zSig = 0x7FFFFFFF;\r
-            goto roundAndPack;\r
-        }\r
-        aSig >>= aExp & 1;\r
-        term = ( (bits64) zSig ) * zSig;\r
-        rem = ( ( (bits64) aSig )<<32 ) - term;\r
-        while ( (sbits64) rem < 0 ) {\r
-            --zSig;\r
-            rem += ( ( (bits64) zSig )<<1 ) | 1;\r
-        }\r
-        zSig |= ( rem != 0 );\r
-    }\r
-    shift32RightJamming( zSig, 1, &zSig );\r
- roundAndPack:\r
-    return roundAndPackFloat32( 0, zExp, zSig );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the single-precision floating-point value `a' is equal to\r
-| the corresponding value `b', and 0 otherwise.  The comparison is performed\r
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag float32_eq( float32 a, float32 b )\r
-{\r
-\r
-    if (    ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )\r
-         || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )\r
-       ) {\r
-        if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {\r
-            float_raise( float_flag_invalid );\r
-        }\r
-        return 0;\r
-    }\r
-    return ( a == b ) || ( (bits32) ( ( a | b )<<1 ) == 0 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the single-precision floating-point value `a' is less than\r
-| or equal to the corresponding value `b', and 0 otherwise.  The comparison\r
-| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag float32_le( float32 a, float32 b )\r
-{\r
-    flag aSign, bSign;\r
-\r
-    if (    ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )\r
-         || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )\r
-       ) {\r
-        float_raise( float_flag_invalid );\r
-        return 0;\r
-    }\r
-    aSign = extractFloat32Sign( a );\r
-    bSign = extractFloat32Sign( b );\r
-    if ( aSign != bSign ) return aSign || ( (bits32) ( ( a | b )<<1 ) == 0 );\r
-    return ( a == b ) || ( aSign ^ ( a < b ) );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the single-precision floating-point value `a' is less than\r
-| the corresponding value `b', and 0 otherwise.  The comparison is performed\r
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag float32_lt( float32 a, float32 b )\r
-{\r
-    flag aSign, bSign;\r
-\r
-    if (    ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )\r
-         || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )\r
-       ) {\r
-        float_raise( float_flag_invalid );\r
-        return 0;\r
-    }\r
-    aSign = extractFloat32Sign( a );\r
-    bSign = extractFloat32Sign( b );\r
-    if ( aSign != bSign ) return aSign && ( (bits32) ( ( a | b )<<1 ) != 0 );\r
-    return ( a != b ) && ( aSign ^ ( a < b ) );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the single-precision floating-point value `a' is equal to\r
-| the corresponding value `b', and 0 otherwise.  The invalid exception is\r
-| raised if either operand is a NaN.  Otherwise, the comparison is performed\r
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag float32_eq_signaling( float32 a, float32 b )\r
-{\r
-\r
-    if (    ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )\r
-         || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )\r
-       ) {\r
-        float_raise( float_flag_invalid );\r
-        return 0;\r
-    }\r
-    return ( a == b ) || ( (bits32) ( ( a | b )<<1 ) == 0 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the single-precision floating-point value `a' is less than or\r
-| equal to the corresponding value `b', and 0 otherwise.  Quiet NaNs do not\r
-| cause an exception.  Otherwise, the comparison is performed according to the\r
-| IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag float32_le_quiet( float32 a, float32 b )\r
-{\r
-    flag aSign, bSign;\r
-    int16 aExp, bExp;\r
-\r
-    if (    ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )\r
-         || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )\r
-       ) {\r
-        if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {\r
-            float_raise( float_flag_invalid );\r
-        }\r
-        return 0;\r
-    }\r
-    aSign = extractFloat32Sign( a );\r
-    bSign = extractFloat32Sign( b );\r
-    if ( aSign != bSign ) return aSign || ( (bits32) ( ( a | b )<<1 ) == 0 );\r
-    return ( a == b ) || ( aSign ^ ( a < b ) );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the single-precision floating-point value `a' is less than\r
-| the corresponding value `b', and 0 otherwise.  Quiet NaNs do not cause an\r
-| exception.  Otherwise, the comparison is performed according to the IEC/IEEE\r
-| Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag float32_lt_quiet( float32 a, float32 b )\r
-{\r
-    flag aSign, bSign;\r
-\r
-    if (    ( ( extractFloat32Exp( a ) == 0xFF ) && extractFloat32Frac( a ) )\r
-         || ( ( extractFloat32Exp( b ) == 0xFF ) && extractFloat32Frac( b ) )\r
-       ) {\r
-        if ( float32_is_signaling_nan( a ) || float32_is_signaling_nan( b ) ) {\r
-            float_raise( float_flag_invalid );\r
-        }\r
-        return 0;\r
-    }\r
-    aSign = extractFloat32Sign( a );\r
-    bSign = extractFloat32Sign( b );\r
-    if ( aSign != bSign ) return aSign && ( (bits32) ( ( a | b )<<1 ) != 0 );\r
-    return ( a != b ) && ( aSign ^ ( a < b ) );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the double-precision floating-point value\r
-| `a' to the 32-bit two's complement integer format.  The conversion is\r
-| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic---which means in particular that the conversion is rounded\r
-| according to the current rounding mode.  If `a' is a NaN, the largest\r
-| positive integer is returned.  Otherwise, if the conversion overflows, the\r
-| largest integer with the same sign as `a' is returned.\r
-*----------------------------------------------------------------------------*/\r
-\r
-int32 float64_to_int32( float64 a )\r
-{\r
-    flag aSign;\r
-    int16 aExp, shiftCount;\r
-    bits64 aSig;\r
-\r
-    aSig = extractFloat64Frac( a );\r
-    aExp = extractFloat64Exp( a );\r
-    aSign = extractFloat64Sign( a );\r
-    if ( ( aExp == 0x7FF ) && aSig ) aSign = 0;\r
-    if ( aExp ) aSig |= LIT64( 0x0010000000000000 );\r
-    shiftCount = 0x42C - aExp;\r
-    if ( 0 < shiftCount ) shift64RightJamming( aSig, shiftCount, &aSig );\r
-    return roundAndPackInt32( aSign, aSig );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the double-precision floating-point value\r
-| `a' to the 32-bit two's complement integer format.  The conversion is\r
-| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic, except that the conversion is always rounded toward zero.\r
-| If `a' is a NaN, the largest positive integer is returned.  Otherwise, if\r
-| the conversion overflows, the largest integer with the same sign as `a' is\r
-| returned.\r
-*----------------------------------------------------------------------------*/\r
-\r
-int32 float64_to_int32_round_to_zero( float64 a )\r
-{\r
-    flag aSign;\r
-    int16 aExp, shiftCount;\r
-    bits64 aSig, savedASig;\r
-    int32 z;\r
-\r
-    aSig = extractFloat64Frac( a );\r
-    aExp = extractFloat64Exp( a );\r
-    aSign = extractFloat64Sign( a );\r
-    if ( 0x41E < aExp ) {\r
-        if ( ( aExp == 0x7FF ) && aSig ) aSign = 0;\r
-        goto invalid;\r
-    }\r
-    else if ( aExp < 0x3FF ) {\r
-        if ( aExp || aSig ) float_exception_flags |= float_flag_inexact;\r
-        return 0;\r
-    }\r
-    aSig |= LIT64( 0x0010000000000000 );\r
-    shiftCount = 0x433 - aExp;\r
-    savedASig = aSig;\r
-    aSig >>= shiftCount;\r
-    z = aSig;\r
-    if ( aSign ) z = - z;\r
-    if ( ( z < 0 ) ^ aSign ) {\r
- invalid:\r
-        float_raise( float_flag_invalid );\r
-        return aSign ? (sbits32) 0x80000000 : 0x7FFFFFFF;\r
-    }\r
-    if ( ( aSig<<shiftCount ) != savedASig ) {\r
-        float_exception_flags |= float_flag_inexact;\r
-    }\r
-    return z;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the double-precision floating-point value\r
-| `a' to the 64-bit two's complement integer format.  The conversion is\r
-| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic---which means in particular that the conversion is rounded\r
-| according to the current rounding mode.  If `a' is a NaN, the largest\r
-| positive integer is returned.  Otherwise, if the conversion overflows, the\r
-| largest integer with the same sign as `a' is returned.\r
-*----------------------------------------------------------------------------*/\r
-\r
-int64 float64_to_int64( float64 a )\r
-{\r
-    flag aSign;\r
-    int16 aExp, shiftCount;\r
-    bits64 aSig, aSigExtra;\r
-\r
-    aSig = extractFloat64Frac( a );\r
-    aExp = extractFloat64Exp( a );\r
-    aSign = extractFloat64Sign( a );\r
-    if ( aExp ) aSig |= LIT64( 0x0010000000000000 );\r
-    shiftCount = 0x433 - aExp;\r
-    if ( shiftCount <= 0 ) {\r
-        if ( 0x43E < aExp ) {\r
-            float_raise( float_flag_invalid );\r
-            if (    ! aSign\r
-                 || (    ( aExp == 0x7FF )\r
-                      && ( aSig != LIT64( 0x0010000000000000 ) ) )\r
-               ) {\r
-                return LIT64( 0x7FFFFFFFFFFFFFFF );\r
-            }\r
-            return (sbits64) LIT64( 0x8000000000000000 );\r
-        }\r
-        aSigExtra = 0;\r
-        aSig <<= - shiftCount;\r
-    }\r
-    else {\r
-        shift64ExtraRightJamming( aSig, 0, shiftCount, &aSig, &aSigExtra );\r
-    }\r
-    return roundAndPackInt64( aSign, aSig, aSigExtra );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the double-precision floating-point value\r
-| `a' to the 64-bit two's complement integer format.  The conversion is\r
-| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic, except that the conversion is always rounded toward zero.\r
-| If `a' is a NaN, the largest positive integer is returned.  Otherwise, if\r
-| the conversion overflows, the largest integer with the same sign as `a' is\r
-| returned.\r
-*----------------------------------------------------------------------------*/\r
-\r
-int64 float64_to_int64_round_to_zero( float64 a )\r
-{\r
-    flag aSign;\r
-    int16 aExp, shiftCount;\r
-    bits64 aSig;\r
-    int64 z;\r
-\r
-    aSig = extractFloat64Frac( a );\r
-    aExp = extractFloat64Exp( a );\r
-    aSign = extractFloat64Sign( a );\r
-    if ( aExp ) aSig |= LIT64( 0x0010000000000000 );\r
-    shiftCount = aExp - 0x433;\r
-    if ( 0 <= shiftCount ) {\r
-        if ( 0x43E <= aExp ) {\r
-            if ( a != LIT64( 0xC3E0000000000000 ) ) {\r
-                float_raise( float_flag_invalid );\r
-                if (    ! aSign\r
-                     || (    ( aExp == 0x7FF )\r
-                          && ( aSig != LIT64( 0x0010000000000000 ) ) )\r
-                   ) {\r
-                    return LIT64( 0x7FFFFFFFFFFFFFFF );\r
-                }\r
-            }\r
-            return (sbits64) LIT64( 0x8000000000000000 );\r
-        }\r
-        z = aSig<<shiftCount;\r
-    }\r
-    else {\r
-        if ( aExp < 0x3FE ) {\r
-            if ( aExp | aSig ) float_exception_flags |= float_flag_inexact;\r
-            return 0;\r
-        }\r
-        z = aSig>>( - shiftCount );\r
-        if ( (bits64) ( aSig<<( shiftCount & 63 ) ) ) {\r
-            float_exception_flags |= float_flag_inexact;\r
-        }\r
-    }\r
-    if ( aSign ) z = - z;\r
-    return z;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the double-precision floating-point value\r
-| `a' to the single-precision floating-point format.  The conversion is\r
-| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float32 float64_to_float32( float64 a )\r
-{\r
-    flag aSign;\r
-    int16 aExp;\r
-    bits64 aSig;\r
-    bits32 zSig;\r
-\r
-    aSig = extractFloat64Frac( a );\r
-    aExp = extractFloat64Exp( a );\r
-    aSign = extractFloat64Sign( a );\r
-    if ( aExp == 0x7FF ) {\r
-        if ( aSig ) return commonNaNToFloat32( float64ToCommonNaN( a ) );\r
-        return packFloat32( aSign, 0xFF, 0 );\r
-    }\r
-    shift64RightJamming( aSig, 22, &aSig );\r
-    zSig = aSig;\r
-    if ( aExp || zSig ) {\r
-        zSig |= 0x40000000;\r
-        aExp -= 0x381;\r
-    }\r
-    return roundAndPackFloat32( aSign, aExp, zSig );\r
-\r
-}\r
-\r
-#ifdef FLOATX80\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the double-precision floating-point value\r
-| `a' to the extended double-precision floating-point format.  The conversion\r
-| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-floatx80 float64_to_floatx80( float64 a )\r
-{\r
-    flag aSign;\r
-    int16 aExp;\r
-    bits64 aSig;\r
-\r
-    aSig = extractFloat64Frac( a );\r
-    aExp = extractFloat64Exp( a );\r
-    aSign = extractFloat64Sign( a );\r
-    if ( aExp == 0x7FF ) {\r
-        if ( aSig ) return commonNaNToFloatx80( float64ToCommonNaN( a ) );\r
-        return packFloatx80( aSign, 0x7FFF, LIT64( 0x8000000000000000 ) );\r
-    }\r
-    if ( aExp == 0 ) {\r
-        if ( aSig == 0 ) return packFloatx80( aSign, 0, 0 );\r
-        normalizeFloat64Subnormal( aSig, &aExp, &aSig );\r
-    }\r
-    return\r
-        packFloatx80(\r
-            aSign, aExp + 0x3C00, ( aSig | LIT64( 0x0010000000000000 ) )<<11 );\r
-\r
-}\r
-\r
-#endif\r
-\r
-#ifdef FLOAT128\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the double-precision floating-point value\r
-| `a' to the quadruple-precision floating-point format.  The conversion is\r
-| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float128 float64_to_float128( float64 a )\r
-{\r
-    flag aSign;\r
-    int16 aExp;\r
-    bits64 aSig, zSig0, zSig1;\r
-\r
-    aSig = extractFloat64Frac( a );\r
-    aExp = extractFloat64Exp( a );\r
-    aSign = extractFloat64Sign( a );\r
-    if ( aExp == 0x7FF ) {\r
-        if ( aSig ) return commonNaNToFloat128( float64ToCommonNaN( a ) );\r
-        return packFloat128( aSign, 0x7FFF, 0, 0 );\r
-    }\r
-    if ( aExp == 0 ) {\r
-        if ( aSig == 0 ) return packFloat128( aSign, 0, 0, 0 );\r
-        normalizeFloat64Subnormal( aSig, &aExp, &aSig );\r
-        --aExp;\r
-    }\r
-    shift128Right( aSig, 0, 4, &zSig0, &zSig1 );\r
-    return packFloat128( aSign, aExp + 0x3C00, zSig0, zSig1 );\r
-\r
-}\r
-\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------\r
-| Rounds the double-precision floating-point value `a' to an integer, and\r
-| returns the result as a double-precision floating-point value.  The\r
-| operation is performed according to the IEC/IEEE Standard for Binary\r
-| Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float64 float64_round_to_int( float64 a )\r
-{\r
-    flag aSign;\r
-    int16 aExp;\r
-    bits64 lastBitMask, roundBitsMask;\r
-    int8 roundingMode;\r
-    float64 z;\r
-\r
-    aExp = extractFloat64Exp( a );\r
-    if ( 0x433 <= aExp ) {\r
-        if ( ( aExp == 0x7FF ) && extractFloat64Frac( a ) ) {\r
-            return propagateFloat64NaN( a, a );\r
-        }\r
-        return a;\r
-    }\r
-    if ( aExp < 0x3FF ) {\r
-        if ( (bits64) ( a<<1 ) == 0 ) return a;\r
-        float_exception_flags |= float_flag_inexact;\r
-        aSign = extractFloat64Sign( a );\r
-        switch ( float_rounding_mode ) {\r
-         case float_round_nearest_even:\r
-            if ( ( aExp == 0x3FE ) && extractFloat64Frac( a ) ) {\r
-                return packFloat64( aSign, 0x3FF, 0 );\r
-            }\r
-            break;\r
-         case float_round_down:\r
-            return aSign ? LIT64( 0xBFF0000000000000 ) : 0;\r
-         case float_round_up:\r
-            return\r
-            aSign ? LIT64( 0x8000000000000000 ) : LIT64( 0x3FF0000000000000 );\r
-        }\r
-        return packFloat64( aSign, 0, 0 );\r
-    }\r
-    lastBitMask = 1;\r
-    lastBitMask <<= 0x433 - aExp;\r
-    roundBitsMask = lastBitMask - 1;\r
-    z = a;\r
-    roundingMode = float_rounding_mode;\r
-    if ( roundingMode == float_round_nearest_even ) {\r
-        z += lastBitMask>>1;\r
-        if ( ( z & roundBitsMask ) == 0 ) z &= ~ lastBitMask;\r
-    }\r
-    else if ( roundingMode != float_round_to_zero ) {\r
-        if ( extractFloat64Sign( z ) ^ ( roundingMode == float_round_up ) ) {\r
-            z += roundBitsMask;\r
-        }\r
-    }\r
-    z &= ~ roundBitsMask;\r
-    if ( z != a ) float_exception_flags |= float_flag_inexact;\r
-    return z;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of adding the absolute values of the double-precision\r
-| floating-point values `a' and `b'.  If `zSign' is 1, the sum is negated\r
-| before being returned.  `zSign' is ignored if the result is a NaN.\r
-| The addition is performed according to the IEC/IEEE Standard for Binary\r
-| Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static float64 addFloat64Sigs( float64 a, float64 b, flag zSign )\r
-{\r
-    int16 aExp, bExp, zExp;\r
-    bits64 aSig, bSig, zSig;\r
-    int16 expDiff;\r
-\r
-    aSig = extractFloat64Frac( a );\r
-    aExp = extractFloat64Exp( a );\r
-    bSig = extractFloat64Frac( b );\r
-    bExp = extractFloat64Exp( b );\r
-    expDiff = aExp - bExp;\r
-    aSig <<= 9;\r
-    bSig <<= 9;\r
-    if ( 0 < expDiff ) {\r
-        if ( aExp == 0x7FF ) {\r
-            if ( aSig ) return propagateFloat64NaN( a, b );\r
-            return a;\r
-        }\r
-        if ( bExp == 0 ) {\r
-            --expDiff;\r
-        }\r
-        else {\r
-            bSig |= LIT64( 0x2000000000000000 );\r
-        }\r
-        shift64RightJamming( bSig, expDiff, &bSig );\r
-        zExp = aExp;\r
-    }\r
-    else if ( expDiff < 0 ) {\r
-        if ( bExp == 0x7FF ) {\r
-            if ( bSig ) return propagateFloat64NaN( a, b );\r
-            return packFloat64( zSign, 0x7FF, 0 );\r
-        }\r
-        if ( aExp == 0 ) {\r
-            ++expDiff;\r
-        }\r
-        else {\r
-            aSig |= LIT64( 0x2000000000000000 );\r
-        }\r
-        shift64RightJamming( aSig, - expDiff, &aSig );\r
-        zExp = bExp;\r
-    }\r
-    else {\r
-        if ( aExp == 0x7FF ) {\r
-            if ( aSig | bSig ) return propagateFloat64NaN( a, b );\r
-            return a;\r
-        }\r
-        if ( aExp == 0 ) return packFloat64( zSign, 0, ( aSig + bSig )>>9 );\r
-        zSig = LIT64( 0x4000000000000000 ) + aSig + bSig;\r
-        zExp = aExp;\r
-        goto roundAndPack;\r
-    }\r
-    aSig |= LIT64( 0x2000000000000000 );\r
-    zSig = ( aSig + bSig )<<1;\r
-    --zExp;\r
-    if ( (sbits64) zSig < 0 ) {\r
-        zSig = aSig + bSig;\r
-        ++zExp;\r
-    }\r
- roundAndPack:\r
-    return roundAndPackFloat64( zSign, zExp, zSig );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of subtracting the absolute values of the double-\r
-| precision floating-point values `a' and `b'.  If `zSign' is 1, the\r
-| difference is negated before being returned.  `zSign' is ignored if the\r
-| result is a NaN.  The subtraction is performed according to the IEC/IEEE\r
-| Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static float64 subFloat64Sigs( float64 a, float64 b, flag zSign )\r
-{\r
-    int16 aExp, bExp, zExp;\r
-    bits64 aSig, bSig, zSig;\r
-    int16 expDiff;\r
-\r
-    aSig = extractFloat64Frac( a );\r
-    aExp = extractFloat64Exp( a );\r
-    bSig = extractFloat64Frac( b );\r
-    bExp = extractFloat64Exp( b );\r
-    expDiff = aExp - bExp;\r
-    aSig <<= 10;\r
-    bSig <<= 10;\r
-    if ( 0 < expDiff ) goto aExpBigger;\r
-    if ( expDiff < 0 ) goto bExpBigger;\r
-    if ( aExp == 0x7FF ) {\r
-        if ( aSig | bSig ) return propagateFloat64NaN( a, b );\r
-        float_raise( float_flag_invalid );\r
-        return float64_default_nan;\r
-    }\r
-    if ( aExp == 0 ) {\r
-        aExp = 1;\r
-        bExp = 1;\r
-    }\r
-    if ( bSig < aSig ) goto aBigger;\r
-    if ( aSig < bSig ) goto bBigger;\r
-    return packFloat64( float_rounding_mode == float_round_down, 0, 0 );\r
- bExpBigger:\r
-    if ( bExp == 0x7FF ) {\r
-        if ( bSig ) return propagateFloat64NaN( a, b );\r
-        return packFloat64( zSign ^ 1, 0x7FF, 0 );\r
-    }\r
-    if ( aExp == 0 ) {\r
-        ++expDiff;\r
-    }\r
-    else {\r
-        aSig |= LIT64( 0x4000000000000000 );\r
-    }\r
-    shift64RightJamming( aSig, - expDiff, &aSig );\r
-    bSig |= LIT64( 0x4000000000000000 );\r
- bBigger:\r
-    zSig = bSig - aSig;\r
-    zExp = bExp;\r
-    zSign ^= 1;\r
-    goto normalizeRoundAndPack;\r
- aExpBigger:\r
-    if ( aExp == 0x7FF ) {\r
-        if ( aSig ) return propagateFloat64NaN( a, b );\r
-        return a;\r
-    }\r
-    if ( bExp == 0 ) {\r
-        --expDiff;\r
-    }\r
-    else {\r
-        bSig |= LIT64( 0x4000000000000000 );\r
-    }\r
-    shift64RightJamming( bSig, expDiff, &bSig );\r
-    aSig |= LIT64( 0x4000000000000000 );\r
- aBigger:\r
-    zSig = aSig - bSig;\r
-    zExp = aExp;\r
- normalizeRoundAndPack:\r
-    --zExp;\r
-    return normalizeRoundAndPackFloat64( zSign, zExp, zSig );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of adding the double-precision floating-point values `a'\r
-| and `b'.  The operation is performed according to the IEC/IEEE Standard for\r
-| Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float64 float64_add( float64 a, float64 b )\r
-{\r
-    flag aSign, bSign;\r
-\r
-    aSign = extractFloat64Sign( a );\r
-    bSign = extractFloat64Sign( b );\r
-    if ( aSign == bSign ) {\r
-        return addFloat64Sigs( a, b, aSign );\r
-    }\r
-    else {\r
-        return subFloat64Sigs( a, b, aSign );\r
-    }\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of subtracting the double-precision floating-point values\r
-| `a' and `b'.  The operation is performed according to the IEC/IEEE Standard\r
-| for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float64 float64_sub( float64 a, float64 b )\r
-{\r
-    flag aSign, bSign;\r
-\r
-    aSign = extractFloat64Sign( a );\r
-    bSign = extractFloat64Sign( b );\r
-    if ( aSign == bSign ) {\r
-        return subFloat64Sigs( a, b, aSign );\r
-    }\r
-    else {\r
-        return addFloat64Sigs( a, b, aSign );\r
-    }\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of multiplying the double-precision floating-point values\r
-| `a' and `b'.  The operation is performed according to the IEC/IEEE Standard\r
-| for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float64 float64_mul( float64 a, float64 b )\r
-{\r
-    flag aSign, bSign, zSign;\r
-    int16 aExp, bExp, zExp;\r
-    bits64 aSig, bSig, zSig0, zSig1;\r
-\r
-    aSig = extractFloat64Frac( a );\r
-    aExp = extractFloat64Exp( a );\r
-    aSign = extractFloat64Sign( a );\r
-    bSig = extractFloat64Frac( b );\r
-    bExp = extractFloat64Exp( b );\r
-    bSign = extractFloat64Sign( b );\r
-    zSign = aSign ^ bSign;\r
-    if ( aExp == 0x7FF ) {\r
-        if ( aSig || ( ( bExp == 0x7FF ) && bSig ) ) {\r
-            return propagateFloat64NaN( a, b );\r
-        }\r
-        if ( ( bExp | bSig ) == 0 ) {\r
-            float_raise( float_flag_invalid );\r
-            return float64_default_nan;\r
-        }\r
-        return packFloat64( zSign, 0x7FF, 0 );\r
-    }\r
-    if ( bExp == 0x7FF ) {\r
-        if ( bSig ) return propagateFloat64NaN( a, b );\r
-        if ( ( aExp | aSig ) == 0 ) {\r
-            float_raise( float_flag_invalid );\r
-            return float64_default_nan;\r
-        }\r
-        return packFloat64( zSign, 0x7FF, 0 );\r
-    }\r
-    if ( aExp == 0 ) {\r
-        if ( aSig == 0 ) return packFloat64( zSign, 0, 0 );\r
-        normalizeFloat64Subnormal( aSig, &aExp, &aSig );\r
-    }\r
-    if ( bExp == 0 ) {\r
-        if ( bSig == 0 ) return packFloat64( zSign, 0, 0 );\r
-        normalizeFloat64Subnormal( bSig, &bExp, &bSig );\r
-    }\r
-    zExp = aExp + bExp - 0x3FF;\r
-    aSig = ( aSig | LIT64( 0x0010000000000000 ) )<<10;\r
-    bSig = ( bSig | LIT64( 0x0010000000000000 ) )<<11;\r
-    mul64To128( aSig, bSig, &zSig0, &zSig1 );\r
-    zSig0 |= ( zSig1 != 0 );\r
-    if ( 0 <= (sbits64) ( zSig0<<1 ) ) {\r
-        zSig0 <<= 1;\r
-        --zExp;\r
-    }\r
-    return roundAndPackFloat64( zSign, zExp, zSig0 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of dividing the double-precision floating-point value `a'\r
-| by the corresponding value `b'.  The operation is performed according to\r
-| the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float64 float64_div( float64 a, float64 b )\r
-{\r
-    flag aSign, bSign, zSign;\r
-    int16 aExp, bExp, zExp;\r
-    bits64 aSig, bSig, zSig;\r
-    bits64 rem0, rem1;\r
-    bits64 term0, term1;\r
-\r
-    aSig = extractFloat64Frac( a );\r
-    aExp = extractFloat64Exp( a );\r
-    aSign = extractFloat64Sign( a );\r
-    bSig = extractFloat64Frac( b );\r
-    bExp = extractFloat64Exp( b );\r
-    bSign = extractFloat64Sign( b );\r
-    zSign = aSign ^ bSign;\r
-    if ( aExp == 0x7FF ) {\r
-        if ( aSig ) return propagateFloat64NaN( a, b );\r
-        if ( bExp == 0x7FF ) {\r
-            if ( bSig ) return propagateFloat64NaN( a, b );\r
-            float_raise( float_flag_invalid );\r
-            return float64_default_nan;\r
-        }\r
-        return packFloat64( zSign, 0x7FF, 0 );\r
-    }\r
-    if ( bExp == 0x7FF ) {\r
-        if ( bSig ) return propagateFloat64NaN( a, b );\r
-        return packFloat64( zSign, 0, 0 );\r
-    }\r
-    if ( bExp == 0 ) {\r
-        if ( bSig == 0 ) {\r
-            if ( ( aExp | aSig ) == 0 ) {\r
-                float_raise( float_flag_invalid );\r
-                return float64_default_nan;\r
-            }\r
-            float_raise( float_flag_divbyzero );\r
-            return packFloat64( zSign, 0x7FF, 0 );\r
-        }\r
-        normalizeFloat64Subnormal( bSig, &bExp, &bSig );\r
-    }\r
-    if ( aExp == 0 ) {\r
-        if ( aSig == 0 ) return packFloat64( zSign, 0, 0 );\r
-        normalizeFloat64Subnormal( aSig, &aExp, &aSig );\r
-    }\r
-    zExp = aExp - bExp + 0x3FD;\r
-    aSig = ( aSig | LIT64( 0x0010000000000000 ) )<<10;\r
-    bSig = ( bSig | LIT64( 0x0010000000000000 ) )<<11;\r
-    if ( bSig <= ( aSig + aSig ) ) {\r
-        aSig >>= 1;\r
-        ++zExp;\r
-    }\r
-    zSig = estimateDiv128To64( aSig, 0, bSig );\r
-    if ( ( zSig & 0x1FF ) <= 2 ) {\r
-        mul64To128( bSig, zSig, &term0, &term1 );\r
-        sub128( aSig, 0, term0, term1, &rem0, &rem1 );\r
-        while ( (sbits64) rem0 < 0 ) {\r
-            --zSig;\r
-            add128( rem0, rem1, 0, bSig, &rem0, &rem1 );\r
-        }\r
-        zSig |= ( rem1 != 0 );\r
-    }\r
-    return roundAndPackFloat64( zSign, zExp, zSig );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the remainder of the double-precision floating-point value `a'\r
-| with respect to the corresponding value `b'.  The operation is performed\r
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float64 float64_rem( float64 a, float64 b )\r
-{\r
-    flag aSign, bSign, zSign;\r
-    int16 aExp, bExp, expDiff;\r
-    bits64 aSig, bSig;\r
-    bits64 q, alternateASig;\r
-    sbits64 sigMean;\r
-\r
-    aSig = extractFloat64Frac( a );\r
-    aExp = extractFloat64Exp( a );\r
-    aSign = extractFloat64Sign( a );\r
-    bSig = extractFloat64Frac( b );\r
-    bExp = extractFloat64Exp( b );\r
-    bSign = extractFloat64Sign( b );\r
-    if ( aExp == 0x7FF ) {\r
-        if ( aSig || ( ( bExp == 0x7FF ) && bSig ) ) {\r
-            return propagateFloat64NaN( a, b );\r
-        }\r
-        float_raise( float_flag_invalid );\r
-        return float64_default_nan;\r
-    }\r
-    if ( bExp == 0x7FF ) {\r
-        if ( bSig ) return propagateFloat64NaN( a, b );\r
-        return a;\r
-    }\r
-    if ( bExp == 0 ) {\r
-        if ( bSig == 0 ) {\r
-            float_raise( float_flag_invalid );\r
-            return float64_default_nan;\r
-        }\r
-        normalizeFloat64Subnormal( bSig, &bExp, &bSig );\r
-    }\r
-    if ( aExp == 0 ) {\r
-        if ( aSig == 0 ) return a;\r
-        normalizeFloat64Subnormal( aSig, &aExp, &aSig );\r
-    }\r
-    expDiff = aExp - bExp;\r
-    aSig = ( aSig | LIT64( 0x0010000000000000 ) )<<11;\r
-    bSig = ( bSig | LIT64( 0x0010000000000000 ) )<<11;\r
-    if ( expDiff < 0 ) {\r
-        if ( expDiff < -1 ) return a;\r
-        aSig >>= 1;\r
-    }\r
-    q = ( bSig <= aSig );\r
-    if ( q ) aSig -= bSig;\r
-    expDiff -= 64;\r
-    while ( 0 < expDiff ) {\r
-        q = estimateDiv128To64( aSig, 0, bSig );\r
-        q = ( 2 < q ) ? q - 2 : 0;\r
-        aSig = - ( ( bSig>>2 ) * q );\r
-        expDiff -= 62;\r
-    }\r
-    expDiff += 64;\r
-    if ( 0 < expDiff ) {\r
-        q = estimateDiv128To64( aSig, 0, bSig );\r
-        q = ( 2 < q ) ? q - 2 : 0;\r
-        q >>= 64 - expDiff;\r
-        bSig >>= 2;\r
-        aSig = ( ( aSig>>1 )<<( expDiff - 1 ) ) - bSig * q;\r
-    }\r
-    else {\r
-        aSig >>= 2;\r
-        bSig >>= 2;\r
-    }\r
-    do {\r
-        alternateASig = aSig;\r
-        ++q;\r
-        aSig -= bSig;\r
-    } while ( 0 <= (sbits64) aSig );\r
-    sigMean = aSig + alternateASig;\r
-    if ( ( sigMean < 0 ) || ( ( sigMean == 0 ) && ( q & 1 ) ) ) {\r
-        aSig = alternateASig;\r
-    }\r
-    zSign = ( (sbits64) aSig < 0 );\r
-    if ( zSign ) aSig = - aSig;\r
-    return normalizeRoundAndPackFloat64( aSign ^ zSign, bExp, aSig );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the square root of the double-precision floating-point value `a'.\r
-| The operation is performed according to the IEC/IEEE Standard for Binary\r
-| Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float64 float64_sqrt( float64 a )\r
-{\r
-    flag aSign;\r
-    int16 aExp, zExp;\r
-    bits64 aSig, zSig, doubleZSig;\r
-    bits64 rem0, rem1, term0, term1;\r
-    float64 z;\r
-\r
-    aSig = extractFloat64Frac( a );\r
-    aExp = extractFloat64Exp( a );\r
-    aSign = extractFloat64Sign( a );\r
-    if ( aExp == 0x7FF ) {\r
-        if ( aSig ) return propagateFloat64NaN( a, a );\r
-        if ( ! aSign ) return a;\r
-        float_raise( float_flag_invalid );\r
-        return float64_default_nan;\r
-    }\r
-    if ( aSign ) {\r
-        if ( ( aExp | aSig ) == 0 ) return a;\r
-        float_raise( float_flag_invalid );\r
-        return float64_default_nan;\r
-    }\r
-    if ( aExp == 0 ) {\r
-        if ( aSig == 0 ) return 0;\r
-        normalizeFloat64Subnormal( aSig, &aExp, &aSig );\r
-    }\r
-    zExp = ( ( aExp - 0x3FF )>>1 ) + 0x3FE;\r
-    aSig |= LIT64( 0x0010000000000000 );\r
-    zSig = estimateSqrt32( aExp, aSig>>21 );\r
-    aSig <<= 9 - ( aExp & 1 );\r
-    zSig = estimateDiv128To64( aSig, 0, zSig<<32 ) + ( zSig<<30 );\r
-    if ( ( zSig & 0x1FF ) <= 5 ) {\r
-        doubleZSig = zSig<<1;\r
-        mul64To128( zSig, zSig, &term0, &term1 );\r
-        sub128( aSig, 0, term0, term1, &rem0, &rem1 );\r
-        while ( (sbits64) rem0 < 0 ) {\r
-            --zSig;\r
-            doubleZSig -= 2;\r
-            add128( rem0, rem1, zSig>>63, doubleZSig | 1, &rem0, &rem1 );\r
-        }\r
-        zSig |= ( ( rem0 | rem1 ) != 0 );\r
-    }\r
-    return roundAndPackFloat64( 0, zExp, zSig );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the double-precision floating-point value `a' is equal to the\r
-| corresponding value `b', and 0 otherwise.  The comparison is performed\r
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag float64_eq( float64 a, float64 b )\r
-{\r
-\r
-    if (    ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )\r
-         || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )\r
-       ) {\r
-        if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {\r
-            float_raise( float_flag_invalid );\r
-        }\r
-        return 0;\r
-    }\r
-    return ( a == b ) || ( (bits64) ( ( a | b )<<1 ) == 0 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the double-precision floating-point value `a' is less than or\r
-| equal to the corresponding value `b', and 0 otherwise.  The comparison is\r
-| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag float64_le( float64 a, float64 b )\r
-{\r
-    flag aSign, bSign;\r
-\r
-    if (    ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )\r
-         || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )\r
-       ) {\r
-        float_raise( float_flag_invalid );\r
-        return 0;\r
-    }\r
-    aSign = extractFloat64Sign( a );\r
-    bSign = extractFloat64Sign( b );\r
-    if ( aSign != bSign ) return aSign || ( (bits64) ( ( a | b )<<1 ) == 0 );\r
-    return ( a == b ) || ( aSign ^ ( a < b ) );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the double-precision floating-point value `a' is less than\r
-| the corresponding value `b', and 0 otherwise.  The comparison is performed\r
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag float64_lt( float64 a, float64 b )\r
-{\r
-    flag aSign, bSign;\r
-\r
-    if (    ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )\r
-         || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )\r
-       ) {\r
-        float_raise( float_flag_invalid );\r
-        return 0;\r
-    }\r
-    aSign = extractFloat64Sign( a );\r
-    bSign = extractFloat64Sign( b );\r
-    if ( aSign != bSign ) return aSign && ( (bits64) ( ( a | b )<<1 ) != 0 );\r
-    return ( a != b ) && ( aSign ^ ( a < b ) );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the double-precision floating-point value `a' is equal to the\r
-| corresponding value `b', and 0 otherwise.  The invalid exception is raised\r
-| if either operand is a NaN.  Otherwise, the comparison is performed\r
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag float64_eq_signaling( float64 a, float64 b )\r
-{\r
-\r
-    if (    ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )\r
-         || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )\r
-       ) {\r
-        float_raise( float_flag_invalid );\r
-        return 0;\r
-    }\r
-    return ( a == b ) || ( (bits64) ( ( a | b )<<1 ) == 0 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the double-precision floating-point value `a' is less than or\r
-| equal to the corresponding value `b', and 0 otherwise.  Quiet NaNs do not\r
-| cause an exception.  Otherwise, the comparison is performed according to the\r
-| IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag float64_le_quiet( float64 a, float64 b )\r
-{\r
-    flag aSign, bSign;\r
-    int16 aExp, bExp;\r
-\r
-    if (    ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )\r
-         || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )\r
-       ) {\r
-        if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {\r
-            float_raise( float_flag_invalid );\r
-        }\r
-        return 0;\r
-    }\r
-    aSign = extractFloat64Sign( a );\r
-    bSign = extractFloat64Sign( b );\r
-    if ( aSign != bSign ) return aSign || ( (bits64) ( ( a | b )<<1 ) == 0 );\r
-    return ( a == b ) || ( aSign ^ ( a < b ) );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the double-precision floating-point value `a' is less than\r
-| the corresponding value `b', and 0 otherwise.  Quiet NaNs do not cause an\r
-| exception.  Otherwise, the comparison is performed according to the IEC/IEEE\r
-| Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag float64_lt_quiet( float64 a, float64 b )\r
-{\r
-    flag aSign, bSign;\r
-\r
-    if (    ( ( extractFloat64Exp( a ) == 0x7FF ) && extractFloat64Frac( a ) )\r
-         || ( ( extractFloat64Exp( b ) == 0x7FF ) && extractFloat64Frac( b ) )\r
-       ) {\r
-        if ( float64_is_signaling_nan( a ) || float64_is_signaling_nan( b ) ) {\r
-            float_raise( float_flag_invalid );\r
-        }\r
-        return 0;\r
-    }\r
-    aSign = extractFloat64Sign( a );\r
-    bSign = extractFloat64Sign( b );\r
-    if ( aSign != bSign ) return aSign && ( (bits64) ( ( a | b )<<1 ) != 0 );\r
-    return ( a != b ) && ( aSign ^ ( a < b ) );\r
-\r
-}\r
-\r
-#ifdef FLOATX80\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the extended double-precision floating-\r
-| point value `a' to the 32-bit two's complement integer format.  The\r
-| conversion is performed according to the IEC/IEEE Standard for Binary\r
-| Floating-Point Arithmetic---which means in particular that the conversion\r
-| is rounded according to the current rounding mode.  If `a' is a NaN, the\r
-| largest positive integer is returned.  Otherwise, if the conversion\r
-| overflows, the largest integer with the same sign as `a' is returned.\r
-*----------------------------------------------------------------------------*/\r
-\r
-int32 floatx80_to_int32( floatx80 a )\r
-{\r
-    flag aSign;\r
-    int32 aExp, shiftCount;\r
-    bits64 aSig;\r
-\r
-    aSig = extractFloatx80Frac( a );\r
-    aExp = extractFloatx80Exp( a );\r
-    aSign = extractFloatx80Sign( a );\r
-    if ( ( aExp == 0x7FFF ) && (bits64) ( aSig<<1 ) ) aSign = 0;\r
-    shiftCount = 0x4037 - aExp;\r
-    if ( shiftCount <= 0 ) shiftCount = 1;\r
-    shift64RightJamming( aSig, shiftCount, &aSig );\r
-    return roundAndPackInt32( aSign, aSig );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the extended double-precision floating-\r
-| point value `a' to the 32-bit two's complement integer format.  The\r
-| conversion is performed according to the IEC/IEEE Standard for Binary\r
-| Floating-Point Arithmetic, except that the conversion is always rounded\r
-| toward zero.  If `a' is a NaN, the largest positive integer is returned.\r
-| Otherwise, if the conversion overflows, the largest integer with the same\r
-| sign as `a' is returned.\r
-*----------------------------------------------------------------------------*/\r
-\r
-int32 floatx80_to_int32_round_to_zero( floatx80 a )\r
-{\r
-    flag aSign;\r
-    int32 aExp, shiftCount;\r
-    bits64 aSig, savedASig;\r
-    int32 z;\r
-\r
-    aSig = extractFloatx80Frac( a );\r
-    aExp = extractFloatx80Exp( a );\r
-    aSign = extractFloatx80Sign( a );\r
-    if ( 0x401E < aExp ) {\r
-        if ( ( aExp == 0x7FFF ) && (bits64) ( aSig<<1 ) ) aSign = 0;\r
-        goto invalid;\r
-    }\r
-    else if ( aExp < 0x3FFF ) {\r
-        if ( aExp || aSig ) float_exception_flags |= float_flag_inexact;\r
-        return 0;\r
-    }\r
-    shiftCount = 0x403E - aExp;\r
-    savedASig = aSig;\r
-    aSig >>= shiftCount;\r
-    z = aSig;\r
-    if ( aSign ) z = - z;\r
-    if ( ( z < 0 ) ^ aSign ) {\r
- invalid:\r
-        float_raise( float_flag_invalid );\r
-        return aSign ? (sbits32) 0x80000000 : 0x7FFFFFFF;\r
-    }\r
-    if ( ( aSig<<shiftCount ) != savedASig ) {\r
-        float_exception_flags |= float_flag_inexact;\r
-    }\r
-    return z;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the extended double-precision floating-\r
-| point value `a' to the 64-bit two's complement integer format.  The\r
-| conversion is performed according to the IEC/IEEE Standard for Binary\r
-| Floating-Point Arithmetic---which means in particular that the conversion\r
-| is rounded according to the current rounding mode.  If `a' is a NaN,\r
-| the largest positive integer is returned.  Otherwise, if the conversion\r
-| overflows, the largest integer with the same sign as `a' is returned.\r
-*----------------------------------------------------------------------------*/\r
-\r
-int64 floatx80_to_int64( floatx80 a )\r
-{\r
-    flag aSign;\r
-    int32 aExp, shiftCount;\r
-    bits64 aSig, aSigExtra;\r
-\r
-    aSig = extractFloatx80Frac( a );\r
-    aExp = extractFloatx80Exp( a );\r
-    aSign = extractFloatx80Sign( a );\r
-    shiftCount = 0x403E - aExp;\r
-    if ( shiftCount <= 0 ) {\r
-        if ( shiftCount ) {\r
-            float_raise( float_flag_invalid );\r
-            if (    ! aSign\r
-                 || (    ( aExp == 0x7FFF )\r
-                      && ( aSig != LIT64( 0x8000000000000000 ) ) )\r
-               ) {\r
-                return LIT64( 0x7FFFFFFFFFFFFFFF );\r
-            }\r
-            return (sbits64) LIT64( 0x8000000000000000 );\r
-        }\r
-        aSigExtra = 0;\r
-    }\r
-    else {\r
-        shift64ExtraRightJamming( aSig, 0, shiftCount, &aSig, &aSigExtra );\r
-    }\r
-    return roundAndPackInt64( aSign, aSig, aSigExtra );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the extended double-precision floating-\r
-| point value `a' to the 64-bit two's complement integer format.  The\r
-| conversion is performed according to the IEC/IEEE Standard for Binary\r
-| Floating-Point Arithmetic, except that the conversion is always rounded\r
-| toward zero.  If `a' is a NaN, the largest positive integer is returned.\r
-| Otherwise, if the conversion overflows, the largest integer with the same\r
-| sign as `a' is returned.\r
-*----------------------------------------------------------------------------*/\r
-\r
-int64 floatx80_to_int64_round_to_zero( floatx80 a )\r
-{\r
-    flag aSign;\r
-    int32 aExp, shiftCount;\r
-    bits64 aSig;\r
-    int64 z;\r
-\r
-    aSig = extractFloatx80Frac( a );\r
-    aExp = extractFloatx80Exp( a );\r
-    aSign = extractFloatx80Sign( a );\r
-    shiftCount = aExp - 0x403E;\r
-    if ( 0 <= shiftCount ) {\r
-        aSig &= LIT64( 0x7FFFFFFFFFFFFFFF );\r
-        if ( ( a.high != 0xC03E ) || aSig ) {\r
-            float_raise( float_flag_invalid );\r
-            if ( ! aSign || ( ( aExp == 0x7FFF ) && aSig ) ) {\r
-                return LIT64( 0x7FFFFFFFFFFFFFFF );\r
-            }\r
-        }\r
-        return (sbits64) LIT64( 0x8000000000000000 );\r
-    }\r
-    else if ( aExp < 0x3FFF ) {\r
-        if ( aExp | aSig ) float_exception_flags |= float_flag_inexact;\r
-        return 0;\r
-    }\r
-    z = aSig>>( - shiftCount );\r
-    if ( (bits64) ( aSig<<( shiftCount & 63 ) ) ) {\r
-        float_exception_flags |= float_flag_inexact;\r
-    }\r
-    if ( aSign ) z = - z;\r
-    return z;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the extended double-precision floating-\r
-| point value `a' to the single-precision floating-point format.  The\r
-| conversion is performed according to the IEC/IEEE Standard for Binary\r
-| Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float32 floatx80_to_float32( floatx80 a )\r
-{\r
-    flag aSign;\r
-    int32 aExp;\r
-    bits64 aSig;\r
-\r
-    aSig = extractFloatx80Frac( a );\r
-    aExp = extractFloatx80Exp( a );\r
-    aSign = extractFloatx80Sign( a );\r
-    if ( aExp == 0x7FFF ) {\r
-        if ( (bits64) ( aSig<<1 ) ) {\r
-            return commonNaNToFloat32( floatx80ToCommonNaN( a ) );\r
-        }\r
-        return packFloat32( aSign, 0xFF, 0 );\r
-    }\r
-    shift64RightJamming( aSig, 33, &aSig );\r
-    if ( aExp || aSig ) aExp -= 0x3F81;\r
-    return roundAndPackFloat32( aSign, aExp, aSig );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the extended double-precision floating-\r
-| point value `a' to the double-precision floating-point format.  The\r
-| conversion is performed according to the IEC/IEEE Standard for Binary\r
-| Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float64 floatx80_to_float64( floatx80 a )\r
-{\r
-    flag aSign;\r
-    int32 aExp;\r
-    bits64 aSig, zSig;\r
-\r
-    aSig = extractFloatx80Frac( a );\r
-    aExp = extractFloatx80Exp( a );\r
-    aSign = extractFloatx80Sign( a );\r
-    if ( aExp == 0x7FFF ) {\r
-        if ( (bits64) ( aSig<<1 ) ) {\r
-            return commonNaNToFloat64( floatx80ToCommonNaN( a ) );\r
-        }\r
-        return packFloat64( aSign, 0x7FF, 0 );\r
-    }\r
-    shift64RightJamming( aSig, 1, &zSig );\r
-    if ( aExp || aSig ) aExp -= 0x3C01;\r
-    return roundAndPackFloat64( aSign, aExp, zSig );\r
-\r
-}\r
-\r
-#ifdef FLOAT128\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the extended double-precision floating-\r
-| point value `a' to the quadruple-precision floating-point format.  The\r
-| conversion is performed according to the IEC/IEEE Standard for Binary\r
-| Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float128 floatx80_to_float128( floatx80 a )\r
-{\r
-    flag aSign;\r
-    int16 aExp;\r
-    bits64 aSig, zSig0, zSig1;\r
-\r
-    aSig = extractFloatx80Frac( a );\r
-    aExp = extractFloatx80Exp( a );\r
-    aSign = extractFloatx80Sign( a );\r
-    if ( ( aExp == 0x7FFF ) && (bits64) ( aSig<<1 ) ) {\r
-        return commonNaNToFloat128( floatx80ToCommonNaN( a ) );\r
-    }\r
-    shift128Right( aSig<<1, 0, 16, &zSig0, &zSig1 );\r
-    return packFloat128( aSign, aExp, zSig0, zSig1 );\r
-\r
-}\r
-\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------\r
-| Rounds the extended double-precision floating-point value `a' to an integer,\r
-| and returns the result as an extended quadruple-precision floating-point\r
-| value.  The operation is performed according to the IEC/IEEE Standard for\r
-| Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-floatx80 floatx80_round_to_int( floatx80 a )\r
-{\r
-    flag aSign;\r
-    int32 aExp;\r
-    bits64 lastBitMask, roundBitsMask;\r
-    int8 roundingMode;\r
-    floatx80 z;\r
-\r
-    aExp = extractFloatx80Exp( a );\r
-    if ( 0x403E <= aExp ) {\r
-        if ( ( aExp == 0x7FFF ) && (bits64) ( extractFloatx80Frac( a )<<1 ) ) {\r
-            return propagateFloatx80NaN( a, a );\r
-        }\r
-        return a;\r
-    }\r
-    if ( aExp < 0x3FFF ) {\r
-        if (    ( aExp == 0 )\r
-             && ( (bits64) ( extractFloatx80Frac( a )<<1 ) == 0 ) ) {\r
-            return a;\r
-        }\r
-        float_exception_flags |= float_flag_inexact;\r
-        aSign = extractFloatx80Sign( a );\r
-        switch ( float_rounding_mode ) {\r
-         case float_round_nearest_even:\r
-            if ( ( aExp == 0x3FFE ) && (bits64) ( extractFloatx80Frac( a )<<1 )\r
-               ) {\r
-                return\r
-                    packFloatx80( aSign, 0x3FFF, LIT64( 0x8000000000000000 ) );\r
-            }\r
-            break;\r
-         case float_round_down:\r
-            return\r
-                  aSign ?\r
-                      packFloatx80( 1, 0x3FFF, LIT64( 0x8000000000000000 ) )\r
-                : packFloatx80( 0, 0, 0 );\r
-         case float_round_up:\r
-            return\r
-                  aSign ? packFloatx80( 1, 0, 0 )\r
-                : packFloatx80( 0, 0x3FFF, LIT64( 0x8000000000000000 ) );\r
-        }\r
-        return packFloatx80( aSign, 0, 0 );\r
-    }\r
-    lastBitMask = 1;\r
-    lastBitMask <<= 0x403E - aExp;\r
-    roundBitsMask = lastBitMask - 1;\r
-    z = a;\r
-    roundingMode = float_rounding_mode;\r
-    if ( roundingMode == float_round_nearest_even ) {\r
-        z.low += lastBitMask>>1;\r
-        if ( ( z.low & roundBitsMask ) == 0 ) z.low &= ~ lastBitMask;\r
-    }\r
-    else if ( roundingMode != float_round_to_zero ) {\r
-        if ( extractFloatx80Sign( z ) ^ ( roundingMode == float_round_up ) ) {\r
-            z.low += roundBitsMask;\r
-        }\r
-    }\r
-    z.low &= ~ roundBitsMask;\r
-    if ( z.low == 0 ) {\r
-        ++z.high;\r
-        z.low = LIT64( 0x8000000000000000 );\r
-    }\r
-    if ( z.low != a.low ) float_exception_flags |= float_flag_inexact;\r
-    return z;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of adding the absolute values of the extended double-\r
-| precision floating-point values `a' and `b'.  If `zSign' is 1, the sum is\r
-| negated before being returned.  `zSign' is ignored if the result is a NaN.\r
-| The addition is performed according to the IEC/IEEE Standard for Binary\r
-| Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static floatx80 addFloatx80Sigs( floatx80 a, floatx80 b, flag zSign )\r
-{\r
-    int32 aExp, bExp, zExp;\r
-    bits64 aSig, bSig, zSig0, zSig1;\r
-    int32 expDiff;\r
-\r
-    aSig = extractFloatx80Frac( a );\r
-    aExp = extractFloatx80Exp( a );\r
-    bSig = extractFloatx80Frac( b );\r
-    bExp = extractFloatx80Exp( b );\r
-    expDiff = aExp - bExp;\r
-    if ( 0 < expDiff ) {\r
-        if ( aExp == 0x7FFF ) {\r
-            if ( (bits64) ( aSig<<1 ) ) return propagateFloatx80NaN( a, b );\r
-            return a;\r
-        }\r
-        if ( bExp == 0 ) --expDiff;\r
-        shift64ExtraRightJamming( bSig, 0, expDiff, &bSig, &zSig1 );\r
-        zExp = aExp;\r
-    }\r
-    else if ( expDiff < 0 ) {\r
-        if ( bExp == 0x7FFF ) {\r
-            if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );\r
-            return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );\r
-        }\r
-        if ( aExp == 0 ) ++expDiff;\r
-        shift64ExtraRightJamming( aSig, 0, - expDiff, &aSig, &zSig1 );\r
-        zExp = bExp;\r
-    }\r
-    else {\r
-        if ( aExp == 0x7FFF ) {\r
-            if ( (bits64) ( ( aSig | bSig )<<1 ) ) {\r
-                return propagateFloatx80NaN( a, b );\r
-            }\r
-            return a;\r
-        }\r
-        zSig1 = 0;\r
-        zSig0 = aSig + bSig;\r
-        if ( aExp == 0 ) {\r
-            normalizeFloatx80Subnormal( zSig0, &zExp, &zSig0 );\r
-            goto roundAndPack;\r
-        }\r
-        zExp = aExp;\r
-        goto shiftRight1;\r
-    }\r
-    zSig0 = aSig + bSig;\r
-    if ( (sbits64) zSig0 < 0 ) goto roundAndPack;\r
- shiftRight1:\r
-    shift64ExtraRightJamming( zSig0, zSig1, 1, &zSig0, &zSig1 );\r
-    zSig0 |= LIT64( 0x8000000000000000 );\r
-    ++zExp;\r
- roundAndPack:\r
-    return\r
-        roundAndPackFloatx80(\r
-            floatx80_rounding_precision, zSign, zExp, zSig0, zSig1 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of subtracting the absolute values of the extended\r
-| double-precision floating-point values `a' and `b'.  If `zSign' is 1, the\r
-| difference is negated before being returned.  `zSign' is ignored if the\r
-| result is a NaN.  The subtraction is performed according to the IEC/IEEE\r
-| Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static floatx80 subFloatx80Sigs( floatx80 a, floatx80 b, flag zSign )\r
-{\r
-    int32 aExp, bExp, zExp;\r
-    bits64 aSig, bSig, zSig0, zSig1;\r
-    int32 expDiff;\r
-    floatx80 z;\r
-\r
-    aSig = extractFloatx80Frac( a );\r
-    aExp = extractFloatx80Exp( a );\r
-    bSig = extractFloatx80Frac( b );\r
-    bExp = extractFloatx80Exp( b );\r
-    expDiff = aExp - bExp;\r
-    if ( 0 < expDiff ) goto aExpBigger;\r
-    if ( expDiff < 0 ) goto bExpBigger;\r
-    if ( aExp == 0x7FFF ) {\r
-        if ( (bits64) ( ( aSig | bSig )<<1 ) ) {\r
-            return propagateFloatx80NaN( a, b );\r
-        }\r
-        float_raise( float_flag_invalid );\r
-        z.low = floatx80_default_nan_low;\r
-        z.high = floatx80_default_nan_high;\r
-        return z;\r
-    }\r
-    if ( aExp == 0 ) {\r
-        aExp = 1;\r
-        bExp = 1;\r
-    }\r
-    zSig1 = 0;\r
-    if ( bSig < aSig ) goto aBigger;\r
-    if ( aSig < bSig ) goto bBigger;\r
-    return packFloatx80( float_rounding_mode == float_round_down, 0, 0 );\r
- bExpBigger:\r
-    if ( bExp == 0x7FFF ) {\r
-        if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );\r
-        return packFloatx80( zSign ^ 1, 0x7FFF, LIT64( 0x8000000000000000 ) );\r
-    }\r
-    if ( aExp == 0 ) ++expDiff;\r
-    shift128RightJamming( aSig, 0, - expDiff, &aSig, &zSig1 );\r
- bBigger:\r
-    sub128( bSig, 0, aSig, zSig1, &zSig0, &zSig1 );\r
-    zExp = bExp;\r
-    zSign ^= 1;\r
-    goto normalizeRoundAndPack;\r
- aExpBigger:\r
-    if ( aExp == 0x7FFF ) {\r
-        if ( (bits64) ( aSig<<1 ) ) return propagateFloatx80NaN( a, b );\r
-        return a;\r
-    }\r
-    if ( bExp == 0 ) --expDiff;\r
-    shift128RightJamming( bSig, 0, expDiff, &bSig, &zSig1 );\r
- aBigger:\r
-    sub128( aSig, 0, bSig, zSig1, &zSig0, &zSig1 );\r
-    zExp = aExp;\r
- normalizeRoundAndPack:\r
-    return\r
-        normalizeRoundAndPackFloatx80(\r
-            floatx80_rounding_precision, zSign, zExp, zSig0, zSig1 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of adding the extended double-precision floating-point\r
-| values `a' and `b'.  The operation is performed according to the IEC/IEEE\r
-| Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-floatx80 floatx80_add( floatx80 a, floatx80 b )\r
-{\r
-    flag aSign, bSign;\r
-\r
-    aSign = extractFloatx80Sign( a );\r
-    bSign = extractFloatx80Sign( b );\r
-    if ( aSign == bSign ) {\r
-        return addFloatx80Sigs( a, b, aSign );\r
-    }\r
-    else {\r
-        return subFloatx80Sigs( a, b, aSign );\r
-    }\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of subtracting the extended double-precision floating-\r
-| point values `a' and `b'.  The operation is performed according to the\r
-| IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-floatx80 floatx80_sub( floatx80 a, floatx80 b )\r
-{\r
-    flag aSign, bSign;\r
-\r
-    aSign = extractFloatx80Sign( a );\r
-    bSign = extractFloatx80Sign( b );\r
-    if ( aSign == bSign ) {\r
-        return subFloatx80Sigs( a, b, aSign );\r
-    }\r
-    else {\r
-        return addFloatx80Sigs( a, b, aSign );\r
-    }\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of multiplying the extended double-precision floating-\r
-| point values `a' and `b'.  The operation is performed according to the\r
-| IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-floatx80 floatx80_mul( floatx80 a, floatx80 b )\r
-{\r
-    flag aSign, bSign, zSign;\r
-    int32 aExp, bExp, zExp;\r
-    bits64 aSig, bSig, zSig0, zSig1;\r
-    floatx80 z;\r
-\r
-    aSig = extractFloatx80Frac( a );\r
-    aExp = extractFloatx80Exp( a );\r
-    aSign = extractFloatx80Sign( a );\r
-    bSig = extractFloatx80Frac( b );\r
-    bExp = extractFloatx80Exp( b );\r
-    bSign = extractFloatx80Sign( b );\r
-    zSign = aSign ^ bSign;\r
-    if ( aExp == 0x7FFF ) {\r
-        if (    (bits64) ( aSig<<1 )\r
-             || ( ( bExp == 0x7FFF ) && (bits64) ( bSig<<1 ) ) ) {\r
-            return propagateFloatx80NaN( a, b );\r
-        }\r
-        if ( ( bExp | bSig ) == 0 ) goto invalid;\r
-        return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );\r
-    }\r
-    if ( bExp == 0x7FFF ) {\r
-        if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );\r
-        if ( ( aExp | aSig ) == 0 ) {\r
- invalid:\r
-            float_raise( float_flag_invalid );\r
-            z.low = floatx80_default_nan_low;\r
-            z.high = floatx80_default_nan_high;\r
-            return z;\r
-        }\r
-        return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );\r
-    }\r
-    if ( aExp == 0 ) {\r
-        if ( aSig == 0 ) return packFloatx80( zSign, 0, 0 );\r
-        normalizeFloatx80Subnormal( aSig, &aExp, &aSig );\r
-    }\r
-    if ( bExp == 0 ) {\r
-        if ( bSig == 0 ) return packFloatx80( zSign, 0, 0 );\r
-        normalizeFloatx80Subnormal( bSig, &bExp, &bSig );\r
-    }\r
-    zExp = aExp + bExp - 0x3FFE;\r
-    mul64To128( aSig, bSig, &zSig0, &zSig1 );\r
-    if ( 0 < (sbits64) zSig0 ) {\r
-        shortShift128Left( zSig0, zSig1, 1, &zSig0, &zSig1 );\r
-        --zExp;\r
-    }\r
-    return\r
-        roundAndPackFloatx80(\r
-            floatx80_rounding_precision, zSign, zExp, zSig0, zSig1 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of dividing the extended double-precision floating-point\r
-| value `a' by the corresponding value `b'.  The operation is performed\r
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-floatx80 floatx80_div( floatx80 a, floatx80 b )\r
-{\r
-    flag aSign, bSign, zSign;\r
-    int32 aExp, bExp, zExp;\r
-    bits64 aSig, bSig, zSig0, zSig1;\r
-    bits64 rem0, rem1, rem2, term0, term1, term2;\r
-    floatx80 z;\r
-\r
-    aSig = extractFloatx80Frac( a );\r
-    aExp = extractFloatx80Exp( a );\r
-    aSign = extractFloatx80Sign( a );\r
-    bSig = extractFloatx80Frac( b );\r
-    bExp = extractFloatx80Exp( b );\r
-    bSign = extractFloatx80Sign( b );\r
-    zSign = aSign ^ bSign;\r
-    if ( aExp == 0x7FFF ) {\r
-        if ( (bits64) ( aSig<<1 ) ) return propagateFloatx80NaN( a, b );\r
-        if ( bExp == 0x7FFF ) {\r
-            if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );\r
-            goto invalid;\r
-        }\r
-        return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );\r
-    }\r
-    if ( bExp == 0x7FFF ) {\r
-        if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );\r
-        return packFloatx80( zSign, 0, 0 );\r
-    }\r
-    if ( bExp == 0 ) {\r
-        if ( bSig == 0 ) {\r
-            if ( ( aExp | aSig ) == 0 ) {\r
- invalid:\r
-                float_raise( float_flag_invalid );\r
-                z.low = floatx80_default_nan_low;\r
-                z.high = floatx80_default_nan_high;\r
-                return z;\r
-            }\r
-            float_raise( float_flag_divbyzero );\r
-            return packFloatx80( zSign, 0x7FFF, LIT64( 0x8000000000000000 ) );\r
-        }\r
-        normalizeFloatx80Subnormal( bSig, &bExp, &bSig );\r
-    }\r
-    if ( aExp == 0 ) {\r
-        if ( aSig == 0 ) return packFloatx80( zSign, 0, 0 );\r
-        normalizeFloatx80Subnormal( aSig, &aExp, &aSig );\r
-    }\r
-    zExp = aExp - bExp + 0x3FFE;\r
-    rem1 = 0;\r
-    if ( bSig <= aSig ) {\r
-        shift128Right( aSig, 0, 1, &aSig, &rem1 );\r
-        ++zExp;\r
-    }\r
-    zSig0 = estimateDiv128To64( aSig, rem1, bSig );\r
-    mul64To128( bSig, zSig0, &term0, &term1 );\r
-    sub128( aSig, rem1, term0, term1, &rem0, &rem1 );\r
-    while ( (sbits64) rem0 < 0 ) {\r
-        --zSig0;\r
-        add128( rem0, rem1, 0, bSig, &rem0, &rem1 );\r
-    }\r
-    zSig1 = estimateDiv128To64( rem1, 0, bSig );\r
-    if ( (bits64) ( zSig1<<1 ) <= 8 ) {\r
-        mul64To128( bSig, zSig1, &term1, &term2 );\r
-        sub128( rem1, 0, term1, term2, &rem1, &rem2 );\r
-        while ( (sbits64) rem1 < 0 ) {\r
-            --zSig1;\r
-            add128( rem1, rem2, 0, bSig, &rem1, &rem2 );\r
-        }\r
-        zSig1 |= ( ( rem1 | rem2 ) != 0 );\r
-    }\r
-    return\r
-        roundAndPackFloatx80(\r
-            floatx80_rounding_precision, zSign, zExp, zSig0, zSig1 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the remainder of the extended double-precision floating-point value\r
-| `a' with respect to the corresponding value `b'.  The operation is performed\r
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-floatx80 floatx80_rem( floatx80 a, floatx80 b )\r
-{\r
-    flag aSign, bSign, zSign;\r
-    int32 aExp, bExp, expDiff;\r
-    bits64 aSig0, aSig1, bSig;\r
-    bits64 q, term0, term1, alternateASig0, alternateASig1;\r
-    floatx80 z;\r
-\r
-    aSig0 = extractFloatx80Frac( a );\r
-    aExp = extractFloatx80Exp( a );\r
-    aSign = extractFloatx80Sign( a );\r
-    bSig = extractFloatx80Frac( b );\r
-    bExp = extractFloatx80Exp( b );\r
-    bSign = extractFloatx80Sign( b );\r
-    if ( aExp == 0x7FFF ) {\r
-        if (    (bits64) ( aSig0<<1 )\r
-             || ( ( bExp == 0x7FFF ) && (bits64) ( bSig<<1 ) ) ) {\r
-            return propagateFloatx80NaN( a, b );\r
-        }\r
-        goto invalid;\r
-    }\r
-    if ( bExp == 0x7FFF ) {\r
-        if ( (bits64) ( bSig<<1 ) ) return propagateFloatx80NaN( a, b );\r
-        return a;\r
-    }\r
-    if ( bExp == 0 ) {\r
-        if ( bSig == 0 ) {\r
- invalid:\r
-            float_raise( float_flag_invalid );\r
-            z.low = floatx80_default_nan_low;\r
-            z.high = floatx80_default_nan_high;\r
-            return z;\r
-        }\r
-        normalizeFloatx80Subnormal( bSig, &bExp, &bSig );\r
-    }\r
-    if ( aExp == 0 ) {\r
-        if ( (bits64) ( aSig0<<1 ) == 0 ) return a;\r
-        normalizeFloatx80Subnormal( aSig0, &aExp, &aSig0 );\r
-    }\r
-    bSig |= LIT64( 0x8000000000000000 );\r
-    zSign = aSign;\r
-    expDiff = aExp - bExp;\r
-    aSig1 = 0;\r
-    if ( expDiff < 0 ) {\r
-        if ( expDiff < -1 ) return a;\r
-        shift128Right( aSig0, 0, 1, &aSig0, &aSig1 );\r
-        expDiff = 0;\r
-    }\r
-    q = ( bSig <= aSig0 );\r
-    if ( q ) aSig0 -= bSig;\r
-    expDiff -= 64;\r
-    while ( 0 < expDiff ) {\r
-        q = estimateDiv128To64( aSig0, aSig1, bSig );\r
-        q = ( 2 < q ) ? q - 2 : 0;\r
-        mul64To128( bSig, q, &term0, &term1 );\r
-        sub128( aSig0, aSig1, term0, term1, &aSig0, &aSig1 );\r
-        shortShift128Left( aSig0, aSig1, 62, &aSig0, &aSig1 );\r
-        expDiff -= 62;\r
-    }\r
-    expDiff += 64;\r
-    if ( 0 < expDiff ) {\r
-        q = estimateDiv128To64( aSig0, aSig1, bSig );\r
-        q = ( 2 < q ) ? q - 2 : 0;\r
-        q >>= 64 - expDiff;\r
-        mul64To128( bSig, q<<( 64 - expDiff ), &term0, &term1 );\r
-        sub128( aSig0, aSig1, term0, term1, &aSig0, &aSig1 );\r
-        shortShift128Left( 0, bSig, 64 - expDiff, &term0, &term1 );\r
-        while ( le128( term0, term1, aSig0, aSig1 ) ) {\r
-            ++q;\r
-            sub128( aSig0, aSig1, term0, term1, &aSig0, &aSig1 );\r
-        }\r
-    }\r
-    else {\r
-        term1 = 0;\r
-        term0 = bSig;\r
-    }\r
-    sub128( term0, term1, aSig0, aSig1, &alternateASig0, &alternateASig1 );\r
-    if (    lt128( alternateASig0, alternateASig1, aSig0, aSig1 )\r
-         || (    eq128( alternateASig0, alternateASig1, aSig0, aSig1 )\r
-              && ( q & 1 ) )\r
-       ) {\r
-        aSig0 = alternateASig0;\r
-        aSig1 = alternateASig1;\r
-        zSign = ! zSign;\r
-    }\r
-    return\r
-        normalizeRoundAndPackFloatx80(\r
-            80, zSign, bExp + expDiff, aSig0, aSig1 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the square root of the extended double-precision floating-point\r
-| value `a'.  The operation is performed according to the IEC/IEEE Standard\r
-| for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-floatx80 floatx80_sqrt( floatx80 a )\r
-{\r
-    flag aSign;\r
-    int32 aExp, zExp;\r
-    bits64 aSig0, aSig1, zSig0, zSig1, doubleZSig0;\r
-    bits64 rem0, rem1, rem2, rem3, term0, term1, term2, term3;\r
-    floatx80 z;\r
-\r
-    aSig0 = extractFloatx80Frac( a );\r
-    aExp = extractFloatx80Exp( a );\r
-    aSign = extractFloatx80Sign( a );\r
-    if ( aExp == 0x7FFF ) {\r
-        if ( (bits64) ( aSig0<<1 ) ) return propagateFloatx80NaN( a, a );\r
-        if ( ! aSign ) return a;\r
-        goto invalid;\r
-    }\r
-    if ( aSign ) {\r
-        if ( ( aExp | aSig0 ) == 0 ) return a;\r
- invalid:\r
-        float_raise( float_flag_invalid );\r
-        z.low = floatx80_default_nan_low;\r
-        z.high = floatx80_default_nan_high;\r
-        return z;\r
-    }\r
-    if ( aExp == 0 ) {\r
-        if ( aSig0 == 0 ) return packFloatx80( 0, 0, 0 );\r
-        normalizeFloatx80Subnormal( aSig0, &aExp, &aSig0 );\r
-    }\r
-    zExp = ( ( aExp - 0x3FFF )>>1 ) + 0x3FFF;\r
-    zSig0 = estimateSqrt32( aExp, aSig0>>32 );\r
-    shift128Right( aSig0, 0, 2 + ( aExp & 1 ), &aSig0, &aSig1 );\r
-    zSig0 = estimateDiv128To64( aSig0, aSig1, zSig0<<32 ) + ( zSig0<<30 );\r
-    doubleZSig0 = zSig0<<1;\r
-    mul64To128( zSig0, zSig0, &term0, &term1 );\r
-    sub128( aSig0, aSig1, term0, term1, &rem0, &rem1 );\r
-    while ( (sbits64) rem0 < 0 ) {\r
-        --zSig0;\r
-        doubleZSig0 -= 2;\r
-        add128( rem0, rem1, zSig0>>63, doubleZSig0 | 1, &rem0, &rem1 );\r
-    }\r
-    zSig1 = estimateDiv128To64( rem1, 0, doubleZSig0 );\r
-    if ( ( zSig1 & LIT64( 0x3FFFFFFFFFFFFFFF ) ) <= 5 ) {\r
-        if ( zSig1 == 0 ) zSig1 = 1;\r
-        mul64To128( doubleZSig0, zSig1, &term1, &term2 );\r
-        sub128( rem1, 0, term1, term2, &rem1, &rem2 );\r
-        mul64To128( zSig1, zSig1, &term2, &term3 );\r
-        sub192( rem1, rem2, 0, 0, term2, term3, &rem1, &rem2, &rem3 );\r
-        while ( (sbits64) rem1 < 0 ) {\r
-            --zSig1;\r
-            shortShift128Left( 0, zSig1, 1, &term2, &term3 );\r
-            term3 |= 1;\r
-            term2 |= doubleZSig0;\r
-            add192( rem1, rem2, rem3, 0, term2, term3, &rem1, &rem2, &rem3 );\r
-        }\r
-        zSig1 |= ( ( rem1 | rem2 | rem3 ) != 0 );\r
-    }\r
-    shortShift128Left( 0, zSig1, 1, &zSig0, &zSig1 );\r
-    zSig0 |= doubleZSig0;\r
-    return\r
-        roundAndPackFloatx80(\r
-            floatx80_rounding_precision, 0, zExp, zSig0, zSig1 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the extended double-precision floating-point value `a' is\r
-| equal to the corresponding value `b', and 0 otherwise.  The comparison is\r
-| performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag floatx80_eq( floatx80 a, floatx80 b )\r
-{\r
-\r
-    if (    (    ( extractFloatx80Exp( a ) == 0x7FFF )\r
-              && (bits64) ( extractFloatx80Frac( a )<<1 ) )\r
-         || (    ( extractFloatx80Exp( b ) == 0x7FFF )\r
-              && (bits64) ( extractFloatx80Frac( b )<<1 ) )\r
-       ) {\r
-        if (    floatx80_is_signaling_nan( a )\r
-             || floatx80_is_signaling_nan( b ) ) {\r
-            float_raise( float_flag_invalid );\r
-        }\r
-        return 0;\r
-    }\r
-    return\r
-           ( a.low == b.low )\r
-        && (    ( a.high == b.high )\r
-             || (    ( a.low == 0 )\r
-                  && ( (bits16) ( ( a.high | b.high )<<1 ) == 0 ) )\r
-           );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the extended double-precision floating-point value `a' is\r
-| less than or equal to the corresponding value `b', and 0 otherwise.  The\r
-| comparison is performed according to the IEC/IEEE Standard for Binary\r
-| Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag floatx80_le( floatx80 a, floatx80 b )\r
-{\r
-    flag aSign, bSign;\r
-\r
-    if (    (    ( extractFloatx80Exp( a ) == 0x7FFF )\r
-              && (bits64) ( extractFloatx80Frac( a )<<1 ) )\r
-         || (    ( extractFloatx80Exp( b ) == 0x7FFF )\r
-              && (bits64) ( extractFloatx80Frac( b )<<1 ) )\r
-       ) {\r
-        float_raise( float_flag_invalid );\r
-        return 0;\r
-    }\r
-    aSign = extractFloatx80Sign( a );\r
-    bSign = extractFloatx80Sign( b );\r
-    if ( aSign != bSign ) {\r
-        return\r
-               aSign\r
-            || (    ( ( (bits16) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )\r
-                 == 0 );\r
-    }\r
-    return\r
-          aSign ? le128( b.high, b.low, a.high, a.low )\r
-        : le128( a.high, a.low, b.high, b.low );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the extended double-precision floating-point value `a' is\r
-| less than the corresponding value `b', and 0 otherwise.  The comparison\r
-| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag floatx80_lt( floatx80 a, floatx80 b )\r
-{\r
-    flag aSign, bSign;\r
-\r
-    if (    (    ( extractFloatx80Exp( a ) == 0x7FFF )\r
-              && (bits64) ( extractFloatx80Frac( a )<<1 ) )\r
-         || (    ( extractFloatx80Exp( b ) == 0x7FFF )\r
-              && (bits64) ( extractFloatx80Frac( b )<<1 ) )\r
-       ) {\r
-        float_raise( float_flag_invalid );\r
-        return 0;\r
-    }\r
-    aSign = extractFloatx80Sign( a );\r
-    bSign = extractFloatx80Sign( b );\r
-    if ( aSign != bSign ) {\r
-        return\r
-               aSign\r
-            && (    ( ( (bits16) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )\r
-                 != 0 );\r
-    }\r
-    return\r
-          aSign ? lt128( b.high, b.low, a.high, a.low )\r
-        : lt128( a.high, a.low, b.high, b.low );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the extended double-precision floating-point value `a' is equal\r
-| to the corresponding value `b', and 0 otherwise.  The invalid exception is\r
-| raised if either operand is a NaN.  Otherwise, the comparison is performed\r
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag floatx80_eq_signaling( floatx80 a, floatx80 b )\r
-{\r
-\r
-    if (    (    ( extractFloatx80Exp( a ) == 0x7FFF )\r
-              && (bits64) ( extractFloatx80Frac( a )<<1 ) )\r
-         || (    ( extractFloatx80Exp( b ) == 0x7FFF )\r
-              && (bits64) ( extractFloatx80Frac( b )<<1 ) )\r
-       ) {\r
-        float_raise( float_flag_invalid );\r
-        return 0;\r
-    }\r
-    return\r
-           ( a.low == b.low )\r
-        && (    ( a.high == b.high )\r
-             || (    ( a.low == 0 )\r
-                  && ( (bits16) ( ( a.high | b.high )<<1 ) == 0 ) )\r
-           );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the extended double-precision floating-point value `a' is less\r
-| than or equal to the corresponding value `b', and 0 otherwise.  Quiet NaNs\r
-| do not cause an exception.  Otherwise, the comparison is performed according\r
-| to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag floatx80_le_quiet( floatx80 a, floatx80 b )\r
-{\r
-    flag aSign, bSign;\r
-\r
-    if (    (    ( extractFloatx80Exp( a ) == 0x7FFF )\r
-              && (bits64) ( extractFloatx80Frac( a )<<1 ) )\r
-         || (    ( extractFloatx80Exp( b ) == 0x7FFF )\r
-              && (bits64) ( extractFloatx80Frac( b )<<1 ) )\r
-       ) {\r
-        if (    floatx80_is_signaling_nan( a )\r
-             || floatx80_is_signaling_nan( b ) ) {\r
-            float_raise( float_flag_invalid );\r
-        }\r
-        return 0;\r
-    }\r
-    aSign = extractFloatx80Sign( a );\r
-    bSign = extractFloatx80Sign( b );\r
-    if ( aSign != bSign ) {\r
-        return\r
-               aSign\r
-            || (    ( ( (bits16) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )\r
-                 == 0 );\r
-    }\r
-    return\r
-          aSign ? le128( b.high, b.low, a.high, a.low )\r
-        : le128( a.high, a.low, b.high, b.low );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the extended double-precision floating-point value `a' is less\r
-| than the corresponding value `b', and 0 otherwise.  Quiet NaNs do not cause\r
-| an exception.  Otherwise, the comparison is performed according to the\r
-| IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag floatx80_lt_quiet( floatx80 a, floatx80 b )\r
-{\r
-    flag aSign, bSign;\r
-\r
-    if (    (    ( extractFloatx80Exp( a ) == 0x7FFF )\r
-              && (bits64) ( extractFloatx80Frac( a )<<1 ) )\r
-         || (    ( extractFloatx80Exp( b ) == 0x7FFF )\r
-              && (bits64) ( extractFloatx80Frac( b )<<1 ) )\r
-       ) {\r
-        if (    floatx80_is_signaling_nan( a )\r
-             || floatx80_is_signaling_nan( b ) ) {\r
-            float_raise( float_flag_invalid );\r
-        }\r
-        return 0;\r
-    }\r
-    aSign = extractFloatx80Sign( a );\r
-    bSign = extractFloatx80Sign( b );\r
-    if ( aSign != bSign ) {\r
-        return\r
-               aSign\r
-            && (    ( ( (bits16) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )\r
-                 != 0 );\r
-    }\r
-    return\r
-          aSign ? lt128( b.high, b.low, a.high, a.low )\r
-        : lt128( a.high, a.low, b.high, b.low );\r
-\r
-}\r
-\r
-#endif\r
-\r
-#ifdef FLOAT128\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the quadruple-precision floating-point\r
-| value `a' to the 32-bit two's complement integer format.  The conversion\r
-| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic---which means in particular that the conversion is rounded\r
-| according to the current rounding mode.  If `a' is a NaN, the largest\r
-| positive integer is returned.  Otherwise, if the conversion overflows, the\r
-| largest integer with the same sign as `a' is returned.\r
-*----------------------------------------------------------------------------*/\r
-\r
-int32 float128_to_int32( float128 a )\r
-{\r
-    flag aSign;\r
-    int32 aExp, shiftCount;\r
-    bits64 aSig0, aSig1;\r
-\r
-    aSig1 = extractFloat128Frac1( a );\r
-    aSig0 = extractFloat128Frac0( a );\r
-    aExp = extractFloat128Exp( a );\r
-    aSign = extractFloat128Sign( a );\r
-    if ( ( aExp == 0x7FFF ) && ( aSig0 | aSig1 ) ) aSign = 0;\r
-    if ( aExp ) aSig0 |= LIT64( 0x0001000000000000 );\r
-    aSig0 |= ( aSig1 != 0 );\r
-    shiftCount = 0x4028 - aExp;\r
-    if ( 0 < shiftCount ) shift64RightJamming( aSig0, shiftCount, &aSig0 );\r
-    return roundAndPackInt32( aSign, aSig0 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the quadruple-precision floating-point\r
-| value `a' to the 32-bit two's complement integer format.  The conversion\r
-| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic, except that the conversion is always rounded toward zero.  If\r
-| `a' is a NaN, the largest positive integer is returned.  Otherwise, if the\r
-| conversion overflows, the largest integer with the same sign as `a' is\r
-| returned.\r
-*----------------------------------------------------------------------------*/\r
-\r
-int32 float128_to_int32_round_to_zero( float128 a )\r
-{\r
-    flag aSign;\r
-    int32 aExp, shiftCount;\r
-    bits64 aSig0, aSig1, savedASig;\r
-    int32 z;\r
-\r
-    aSig1 = extractFloat128Frac1( a );\r
-    aSig0 = extractFloat128Frac0( a );\r
-    aExp = extractFloat128Exp( a );\r
-    aSign = extractFloat128Sign( a );\r
-    aSig0 |= ( aSig1 != 0 );\r
-    if ( 0x401E < aExp ) {\r
-        if ( ( aExp == 0x7FFF ) && aSig0 ) aSign = 0;\r
-        goto invalid;\r
-    }\r
-    else if ( aExp < 0x3FFF ) {\r
-        if ( aExp || aSig0 ) float_exception_flags |= float_flag_inexact;\r
-        return 0;\r
-    }\r
-    aSig0 |= LIT64( 0x0001000000000000 );\r
-    shiftCount = 0x402F - aExp;\r
-    savedASig = aSig0;\r
-    aSig0 >>= shiftCount;\r
-    z = aSig0;\r
-    if ( aSign ) z = - z;\r
-    if ( ( z < 0 ) ^ aSign ) {\r
- invalid:\r
-        float_raise( float_flag_invalid );\r
-        return aSign ? (sbits32) 0x80000000 : 0x7FFFFFFF;\r
-    }\r
-    if ( ( aSig0<<shiftCount ) != savedASig ) {\r
-        float_exception_flags |= float_flag_inexact;\r
-    }\r
-    return z;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the quadruple-precision floating-point\r
-| value `a' to the 64-bit two's complement integer format.  The conversion\r
-| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic---which means in particular that the conversion is rounded\r
-| according to the current rounding mode.  If `a' is a NaN, the largest\r
-| positive integer is returned.  Otherwise, if the conversion overflows, the\r
-| largest integer with the same sign as `a' is returned.\r
-*----------------------------------------------------------------------------*/\r
-\r
-int64 float128_to_int64( float128 a )\r
-{\r
-    flag aSign;\r
-    int32 aExp, shiftCount;\r
-    bits64 aSig0, aSig1;\r
-\r
-    aSig1 = extractFloat128Frac1( a );\r
-    aSig0 = extractFloat128Frac0( a );\r
-    aExp = extractFloat128Exp( a );\r
-    aSign = extractFloat128Sign( a );\r
-    if ( aExp ) aSig0 |= LIT64( 0x0001000000000000 );\r
-    shiftCount = 0x402F - aExp;\r
-    if ( shiftCount <= 0 ) {\r
-        if ( 0x403E < aExp ) {\r
-            float_raise( float_flag_invalid );\r
-            if (    ! aSign\r
-                 || (    ( aExp == 0x7FFF )\r
-                      && ( aSig1 || ( aSig0 != LIT64( 0x0001000000000000 ) ) )\r
-                    )\r
-               ) {\r
-                return LIT64( 0x7FFFFFFFFFFFFFFF );\r
-            }\r
-            return (sbits64) LIT64( 0x8000000000000000 );\r
-        }\r
-        shortShift128Left( aSig0, aSig1, - shiftCount, &aSig0, &aSig1 );\r
-    }\r
-    else {\r
-        shift64ExtraRightJamming( aSig0, aSig1, shiftCount, &aSig0, &aSig1 );\r
-    }\r
-    return roundAndPackInt64( aSign, aSig0, aSig1 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the quadruple-precision floating-point\r
-| value `a' to the 64-bit two's complement integer format.  The conversion\r
-| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic, except that the conversion is always rounded toward zero.\r
-| If `a' is a NaN, the largest positive integer is returned.  Otherwise, if\r
-| the conversion overflows, the largest integer with the same sign as `a' is\r
-| returned.\r
-*----------------------------------------------------------------------------*/\r
-\r
-int64 float128_to_int64_round_to_zero( float128 a )\r
-{\r
-    flag aSign;\r
-    int32 aExp, shiftCount;\r
-    bits64 aSig0, aSig1;\r
-    int64 z;\r
-\r
-    aSig1 = extractFloat128Frac1( a );\r
-    aSig0 = extractFloat128Frac0( a );\r
-    aExp = extractFloat128Exp( a );\r
-    aSign = extractFloat128Sign( a );\r
-    if ( aExp ) aSig0 |= LIT64( 0x0001000000000000 );\r
-    shiftCount = aExp - 0x402F;\r
-    if ( 0 < shiftCount ) {\r
-        if ( 0x403E <= aExp ) {\r
-            aSig0 &= LIT64( 0x0000FFFFFFFFFFFF );\r
-            if (    ( a.high == LIT64( 0xC03E000000000000 ) )\r
-                 && ( aSig1 < LIT64( 0x0002000000000000 ) ) ) {\r
-                if ( aSig1 ) float_exception_flags |= float_flag_inexact;\r
-            }\r
-            else {\r
-                float_raise( float_flag_invalid );\r
-                if ( ! aSign || ( ( aExp == 0x7FFF ) && ( aSig0 | aSig1 ) ) ) {\r
-                    return LIT64( 0x7FFFFFFFFFFFFFFF );\r
-                }\r
-            }\r
-            return (sbits64) LIT64( 0x8000000000000000 );\r
-        }\r
-        z = ( aSig0<<shiftCount ) | ( aSig1>>( ( - shiftCount ) & 63 ) );\r
-        if ( (bits64) ( aSig1<<shiftCount ) ) {\r
-            float_exception_flags |= float_flag_inexact;\r
-        }\r
-    }\r
-    else {\r
-        if ( aExp < 0x3FFF ) {\r
-            if ( aExp | aSig0 | aSig1 ) {\r
-                float_exception_flags |= float_flag_inexact;\r
-            }\r
-            return 0;\r
-        }\r
-        z = aSig0>>( - shiftCount );\r
-        if (    aSig1\r
-             || ( shiftCount && (bits64) ( aSig0<<( shiftCount & 63 ) ) ) ) {\r
-            float_exception_flags |= float_flag_inexact;\r
-        }\r
-    }\r
-    if ( aSign ) z = - z;\r
-    return z;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the quadruple-precision floating-point\r
-| value `a' to the single-precision floating-point format.  The conversion\r
-| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float32 float128_to_float32( float128 a )\r
-{\r
-    flag aSign;\r
-    int32 aExp;\r
-    bits64 aSig0, aSig1;\r
-    bits32 zSig;\r
-\r
-    aSig1 = extractFloat128Frac1( a );\r
-    aSig0 = extractFloat128Frac0( a );\r
-    aExp = extractFloat128Exp( a );\r
-    aSign = extractFloat128Sign( a );\r
-    if ( aExp == 0x7FFF ) {\r
-        if ( aSig0 | aSig1 ) {\r
-            return commonNaNToFloat32( float128ToCommonNaN( a ) );\r
-        }\r
-        return packFloat32( aSign, 0xFF, 0 );\r
-    }\r
-    aSig0 |= ( aSig1 != 0 );\r
-    shift64RightJamming( aSig0, 18, &aSig0 );\r
-    zSig = aSig0;\r
-    if ( aExp || zSig ) {\r
-        zSig |= 0x40000000;\r
-        aExp -= 0x3F81;\r
-    }\r
-    return roundAndPackFloat32( aSign, aExp, zSig );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the quadruple-precision floating-point\r
-| value `a' to the double-precision floating-point format.  The conversion\r
-| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float64 float128_to_float64( float128 a )\r
-{\r
-    flag aSign;\r
-    int32 aExp;\r
-    bits64 aSig0, aSig1;\r
-\r
-    aSig1 = extractFloat128Frac1( a );\r
-    aSig0 = extractFloat128Frac0( a );\r
-    aExp = extractFloat128Exp( a );\r
-    aSign = extractFloat128Sign( a );\r
-    if ( aExp == 0x7FFF ) {\r
-        if ( aSig0 | aSig1 ) {\r
-            return commonNaNToFloat64( float128ToCommonNaN( a ) );\r
-        }\r
-        return packFloat64( aSign, 0x7FF, 0 );\r
-    }\r
-    shortShift128Left( aSig0, aSig1, 14, &aSig0, &aSig1 );\r
-    aSig0 |= ( aSig1 != 0 );\r
-    if ( aExp || aSig0 ) {\r
-        aSig0 |= LIT64( 0x4000000000000000 );\r
-        aExp -= 0x3C01;\r
-    }\r
-    return roundAndPackFloat64( aSign, aExp, aSig0 );\r
-\r
-}\r
-\r
-#ifdef FLOATX80\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of converting the quadruple-precision floating-point\r
-| value `a' to the extended double-precision floating-point format.  The\r
-| conversion is performed according to the IEC/IEEE Standard for Binary\r
-| Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-floatx80 float128_to_floatx80( float128 a )\r
-{\r
-    flag aSign;\r
-    int32 aExp;\r
-    bits64 aSig0, aSig1;\r
-\r
-    aSig1 = extractFloat128Frac1( a );\r
-    aSig0 = extractFloat128Frac0( a );\r
-    aExp = extractFloat128Exp( a );\r
-    aSign = extractFloat128Sign( a );\r
-    if ( aExp == 0x7FFF ) {\r
-        if ( aSig0 | aSig1 ) {\r
-            return commonNaNToFloatx80( float128ToCommonNaN( a ) );\r
-        }\r
-        return packFloatx80( aSign, 0x7FFF, LIT64( 0x8000000000000000 ) );\r
-    }\r
-    if ( aExp == 0 ) {\r
-        if ( ( aSig0 | aSig1 ) == 0 ) return packFloatx80( aSign, 0, 0 );\r
-        normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );\r
-    }\r
-    else {\r
-        aSig0 |= LIT64( 0x0001000000000000 );\r
-    }\r
-    shortShift128Left( aSig0, aSig1, 15, &aSig0, &aSig1 );\r
-    return roundAndPackFloatx80( 80, aSign, aExp, aSig0, aSig1 );\r
-\r
-}\r
-\r
-#endif\r
-\r
-/*----------------------------------------------------------------------------\r
-| Rounds the quadruple-precision floating-point value `a' to an integer, and\r
-| returns the result as a quadruple-precision floating-point value.  The\r
-| operation is performed according to the IEC/IEEE Standard for Binary\r
-| Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float128 float128_round_to_int( float128 a )\r
-{\r
-    flag aSign;\r
-    int32 aExp;\r
-    bits64 lastBitMask, roundBitsMask;\r
-    int8 roundingMode;\r
-    float128 z;\r
-\r
-    aExp = extractFloat128Exp( a );\r
-    if ( 0x402F <= aExp ) {\r
-        if ( 0x406F <= aExp ) {\r
-            if (    ( aExp == 0x7FFF )\r
-                 && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) )\r
-               ) {\r
-                return propagateFloat128NaN( a, a );\r
-            }\r
-            return a;\r
-        }\r
-        lastBitMask = 1;\r
-        lastBitMask = ( lastBitMask<<( 0x406E - aExp ) )<<1;\r
-        roundBitsMask = lastBitMask - 1;\r
-        z = a;\r
-        roundingMode = float_rounding_mode;\r
-        if ( roundingMode == float_round_nearest_even ) {\r
-            if ( lastBitMask ) {\r
-                add128( z.high, z.low, 0, lastBitMask>>1, &z.high, &z.low );\r
-                if ( ( z.low & roundBitsMask ) == 0 ) z.low &= ~ lastBitMask;\r
-            }\r
-            else {\r
-                if ( (sbits64) z.low < 0 ) {\r
-                    ++z.high;\r
-                    if ( (bits64) ( z.low<<1 ) == 0 ) z.high &= ~1;\r
-                }\r
-            }\r
-        }\r
-        else if ( roundingMode != float_round_to_zero ) {\r
-            if (   extractFloat128Sign( z )\r
-                 ^ ( roundingMode == float_round_up ) ) {\r
-                add128( z.high, z.low, 0, roundBitsMask, &z.high, &z.low );\r
-            }\r
-        }\r
-        z.low &= ~ roundBitsMask;\r
-    }\r
-    else {\r
-        if ( aExp < 0x3FFF ) {\r
-            if ( ( ( (bits64) ( a.high<<1 ) ) | a.low ) == 0 ) return a;\r
-            float_exception_flags |= float_flag_inexact;\r
-            aSign = extractFloat128Sign( a );\r
-            switch ( float_rounding_mode ) {\r
-             case float_round_nearest_even:\r
-                if (    ( aExp == 0x3FFE )\r
-                     && (   extractFloat128Frac0( a )\r
-                          | extractFloat128Frac1( a ) )\r
-                   ) {\r
-                    return packFloat128( aSign, 0x3FFF, 0, 0 );\r
-                }\r
-                break;\r
-             case float_round_down:\r
-                return\r
-                      aSign ? packFloat128( 1, 0x3FFF, 0, 0 )\r
-                    : packFloat128( 0, 0, 0, 0 );\r
-             case float_round_up:\r
-                return\r
-                      aSign ? packFloat128( 1, 0, 0, 0 )\r
-                    : packFloat128( 0, 0x3FFF, 0, 0 );\r
-            }\r
-            return packFloat128( aSign, 0, 0, 0 );\r
-        }\r
-        lastBitMask = 1;\r
-        lastBitMask <<= 0x402F - aExp;\r
-        roundBitsMask = lastBitMask - 1;\r
-        z.low = 0;\r
-        z.high = a.high;\r
-        roundingMode = float_rounding_mode;\r
-        if ( roundingMode == float_round_nearest_even ) {\r
-            z.high += lastBitMask>>1;\r
-            if ( ( ( z.high & roundBitsMask ) | a.low ) == 0 ) {\r
-                z.high &= ~ lastBitMask;\r
-            }\r
-        }\r
-        else if ( roundingMode != float_round_to_zero ) {\r
-            if (   extractFloat128Sign( z )\r
-                 ^ ( roundingMode == float_round_up ) ) {\r
-                z.high |= ( a.low != 0 );\r
-                z.high += roundBitsMask;\r
-            }\r
-        }\r
-        z.high &= ~ roundBitsMask;\r
-    }\r
-    if ( ( z.low != a.low ) || ( z.high != a.high ) ) {\r
-        float_exception_flags |= float_flag_inexact;\r
-    }\r
-    return z;\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of adding the absolute values of the quadruple-precision\r
-| floating-point values `a' and `b'.  If `zSign' is 1, the sum is negated\r
-| before being returned.  `zSign' is ignored if the result is a NaN.\r
-| The addition is performed according to the IEC/IEEE Standard for Binary\r
-| Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static float128 addFloat128Sigs( float128 a, float128 b, flag zSign )\r
-{\r
-    int32 aExp, bExp, zExp;\r
-    bits64 aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2;\r
-    int32 expDiff;\r
-\r
-    aSig1 = extractFloat128Frac1( a );\r
-    aSig0 = extractFloat128Frac0( a );\r
-    aExp = extractFloat128Exp( a );\r
-    bSig1 = extractFloat128Frac1( b );\r
-    bSig0 = extractFloat128Frac0( b );\r
-    bExp = extractFloat128Exp( b );\r
-    expDiff = aExp - bExp;\r
-    if ( 0 < expDiff ) {\r
-        if ( aExp == 0x7FFF ) {\r
-            if ( aSig0 | aSig1 ) return propagateFloat128NaN( a, b );\r
-            return a;\r
-        }\r
-        if ( bExp == 0 ) {\r
-            --expDiff;\r
-        }\r
-        else {\r
-            bSig0 |= LIT64( 0x0001000000000000 );\r
-        }\r
-        shift128ExtraRightJamming(\r
-            bSig0, bSig1, 0, expDiff, &bSig0, &bSig1, &zSig2 );\r
-        zExp = aExp;\r
-    }\r
-    else if ( expDiff < 0 ) {\r
-        if ( bExp == 0x7FFF ) {\r
-            if ( bSig0 | bSig1 ) return propagateFloat128NaN( a, b );\r
-            return packFloat128( zSign, 0x7FFF, 0, 0 );\r
-        }\r
-        if ( aExp == 0 ) {\r
-            ++expDiff;\r
-        }\r
-        else {\r
-            aSig0 |= LIT64( 0x0001000000000000 );\r
-        }\r
-        shift128ExtraRightJamming(\r
-            aSig0, aSig1, 0, - expDiff, &aSig0, &aSig1, &zSig2 );\r
-        zExp = bExp;\r
-    }\r
-    else {\r
-        if ( aExp == 0x7FFF ) {\r
-            if ( aSig0 | aSig1 | bSig0 | bSig1 ) {\r
-                return propagateFloat128NaN( a, b );\r
-            }\r
-            return a;\r
-        }\r
-        add128( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1 );\r
-        if ( aExp == 0 ) return packFloat128( zSign, 0, zSig0, zSig1 );\r
-        zSig2 = 0;\r
-        zSig0 |= LIT64( 0x0002000000000000 );\r
-        zExp = aExp;\r
-        goto shiftRight1;\r
-    }\r
-    aSig0 |= LIT64( 0x0001000000000000 );\r
-    add128( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1 );\r
-    --zExp;\r
-    if ( zSig0 < LIT64( 0x0002000000000000 ) ) goto roundAndPack;\r
-    ++zExp;\r
- shiftRight1:\r
-    shift128ExtraRightJamming(\r
-        zSig0, zSig1, zSig2, 1, &zSig0, &zSig1, &zSig2 );\r
- roundAndPack:\r
-    return roundAndPackFloat128( zSign, zExp, zSig0, zSig1, zSig2 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of subtracting the absolute values of the quadruple-\r
-| precision floating-point values `a' and `b'.  If `zSign' is 1, the\r
-| difference is negated before being returned.  `zSign' is ignored if the\r
-| result is a NaN.  The subtraction is performed according to the IEC/IEEE\r
-| Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-static float128 subFloat128Sigs( float128 a, float128 b, flag zSign )\r
-{\r
-    int32 aExp, bExp, zExp;\r
-    bits64 aSig0, aSig1, bSig0, bSig1, zSig0, zSig1;\r
-    int32 expDiff;\r
-    float128 z;\r
-\r
-    aSig1 = extractFloat128Frac1( a );\r
-    aSig0 = extractFloat128Frac0( a );\r
-    aExp = extractFloat128Exp( a );\r
-    bSig1 = extractFloat128Frac1( b );\r
-    bSig0 = extractFloat128Frac0( b );\r
-    bExp = extractFloat128Exp( b );\r
-    expDiff = aExp - bExp;\r
-    shortShift128Left( aSig0, aSig1, 14, &aSig0, &aSig1 );\r
-    shortShift128Left( bSig0, bSig1, 14, &bSig0, &bSig1 );\r
-    if ( 0 < expDiff ) goto aExpBigger;\r
-    if ( expDiff < 0 ) goto bExpBigger;\r
-    if ( aExp == 0x7FFF ) {\r
-        if ( aSig0 | aSig1 | bSig0 | bSig1 ) {\r
-            return propagateFloat128NaN( a, b );\r
-        }\r
-        float_raise( float_flag_invalid );\r
-        z.low = float128_default_nan_low;\r
-        z.high = float128_default_nan_high;\r
-        return z;\r
-    }\r
-    if ( aExp == 0 ) {\r
-        aExp = 1;\r
-        bExp = 1;\r
-    }\r
-    if ( bSig0 < aSig0 ) goto aBigger;\r
-    if ( aSig0 < bSig0 ) goto bBigger;\r
-    if ( bSig1 < aSig1 ) goto aBigger;\r
-    if ( aSig1 < bSig1 ) goto bBigger;\r
-    return packFloat128( float_rounding_mode == float_round_down, 0, 0, 0 );\r
- bExpBigger:\r
-    if ( bExp == 0x7FFF ) {\r
-        if ( bSig0 | bSig1 ) return propagateFloat128NaN( a, b );\r
-        return packFloat128( zSign ^ 1, 0x7FFF, 0, 0 );\r
-    }\r
-    if ( aExp == 0 ) {\r
-        ++expDiff;\r
-    }\r
-    else {\r
-        aSig0 |= LIT64( 0x4000000000000000 );\r
-    }\r
-    shift128RightJamming( aSig0, aSig1, - expDiff, &aSig0, &aSig1 );\r
-    bSig0 |= LIT64( 0x4000000000000000 );\r
- bBigger:\r
-    sub128( bSig0, bSig1, aSig0, aSig1, &zSig0, &zSig1 );\r
-    zExp = bExp;\r
-    zSign ^= 1;\r
-    goto normalizeRoundAndPack;\r
- aExpBigger:\r
-    if ( aExp == 0x7FFF ) {\r
-        if ( aSig0 | aSig1 ) return propagateFloat128NaN( a, b );\r
-        return a;\r
-    }\r
-    if ( bExp == 0 ) {\r
-        --expDiff;\r
-    }\r
-    else {\r
-        bSig0 |= LIT64( 0x4000000000000000 );\r
-    }\r
-    shift128RightJamming( bSig0, bSig1, expDiff, &bSig0, &bSig1 );\r
-    aSig0 |= LIT64( 0x4000000000000000 );\r
- aBigger:\r
-    sub128( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1 );\r
-    zExp = aExp;\r
- normalizeRoundAndPack:\r
-    --zExp;\r
-    return normalizeRoundAndPackFloat128( zSign, zExp - 14, zSig0, zSig1 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of adding the quadruple-precision floating-point values\r
-| `a' and `b'.  The operation is performed according to the IEC/IEEE Standard\r
-| for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float128 float128_add( float128 a, float128 b )\r
-{\r
-    flag aSign, bSign;\r
-\r
-    aSign = extractFloat128Sign( a );\r
-    bSign = extractFloat128Sign( b );\r
-    if ( aSign == bSign ) {\r
-        return addFloat128Sigs( a, b, aSign );\r
-    }\r
-    else {\r
-        return subFloat128Sigs( a, b, aSign );\r
-    }\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of subtracting the quadruple-precision floating-point\r
-| values `a' and `b'.  The operation is performed according to the IEC/IEEE\r
-| Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float128 float128_sub( float128 a, float128 b )\r
-{\r
-    flag aSign, bSign;\r
-\r
-    aSign = extractFloat128Sign( a );\r
-    bSign = extractFloat128Sign( b );\r
-    if ( aSign == bSign ) {\r
-        return subFloat128Sigs( a, b, aSign );\r
-    }\r
-    else {\r
-        return addFloat128Sigs( a, b, aSign );\r
-    }\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of multiplying the quadruple-precision floating-point\r
-| values `a' and `b'.  The operation is performed according to the IEC/IEEE\r
-| Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float128 float128_mul( float128 a, float128 b )\r
-{\r
-    flag aSign, bSign, zSign;\r
-    int32 aExp, bExp, zExp;\r
-    bits64 aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2, zSig3;\r
-    float128 z;\r
-\r
-    aSig1 = extractFloat128Frac1( a );\r
-    aSig0 = extractFloat128Frac0( a );\r
-    aExp = extractFloat128Exp( a );\r
-    aSign = extractFloat128Sign( a );\r
-    bSig1 = extractFloat128Frac1( b );\r
-    bSig0 = extractFloat128Frac0( b );\r
-    bExp = extractFloat128Exp( b );\r
-    bSign = extractFloat128Sign( b );\r
-    zSign = aSign ^ bSign;\r
-    if ( aExp == 0x7FFF ) {\r
-        if (    ( aSig0 | aSig1 )\r
-             || ( ( bExp == 0x7FFF ) && ( bSig0 | bSig1 ) ) ) {\r
-            return propagateFloat128NaN( a, b );\r
-        }\r
-        if ( ( bExp | bSig0 | bSig1 ) == 0 ) goto invalid;\r
-        return packFloat128( zSign, 0x7FFF, 0, 0 );\r
-    }\r
-    if ( bExp == 0x7FFF ) {\r
-        if ( bSig0 | bSig1 ) return propagateFloat128NaN( a, b );\r
-        if ( ( aExp | aSig0 | aSig1 ) == 0 ) {\r
- invalid:\r
-            float_raise( float_flag_invalid );\r
-            z.low = float128_default_nan_low;\r
-            z.high = float128_default_nan_high;\r
-            return z;\r
-        }\r
-        return packFloat128( zSign, 0x7FFF, 0, 0 );\r
-    }\r
-    if ( aExp == 0 ) {\r
-        if ( ( aSig0 | aSig1 ) == 0 ) return packFloat128( zSign, 0, 0, 0 );\r
-        normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );\r
-    }\r
-    if ( bExp == 0 ) {\r
-        if ( ( bSig0 | bSig1 ) == 0 ) return packFloat128( zSign, 0, 0, 0 );\r
-        normalizeFloat128Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 );\r
-    }\r
-    zExp = aExp + bExp - 0x4000;\r
-    aSig0 |= LIT64( 0x0001000000000000 );\r
-    shortShift128Left( bSig0, bSig1, 16, &bSig0, &bSig1 );\r
-    mul128To256( aSig0, aSig1, bSig0, bSig1, &zSig0, &zSig1, &zSig2, &zSig3 );\r
-    add128( zSig0, zSig1, aSig0, aSig1, &zSig0, &zSig1 );\r
-    zSig2 |= ( zSig3 != 0 );\r
-    if ( LIT64( 0x0002000000000000 ) <= zSig0 ) {\r
-        shift128ExtraRightJamming(\r
-            zSig0, zSig1, zSig2, 1, &zSig0, &zSig1, &zSig2 );\r
-        ++zExp;\r
-    }\r
-    return roundAndPackFloat128( zSign, zExp, zSig0, zSig1, zSig2 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the result of dividing the quadruple-precision floating-point value\r
-| `a' by the corresponding value `b'.  The operation is performed according to\r
-| the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float128 float128_div( float128 a, float128 b )\r
-{\r
-    flag aSign, bSign, zSign;\r
-    int32 aExp, bExp, zExp;\r
-    bits64 aSig0, aSig1, bSig0, bSig1, zSig0, zSig1, zSig2;\r
-    bits64 rem0, rem1, rem2, rem3, term0, term1, term2, term3;\r
-    float128 z;\r
-\r
-    aSig1 = extractFloat128Frac1( a );\r
-    aSig0 = extractFloat128Frac0( a );\r
-    aExp = extractFloat128Exp( a );\r
-    aSign = extractFloat128Sign( a );\r
-    bSig1 = extractFloat128Frac1( b );\r
-    bSig0 = extractFloat128Frac0( b );\r
-    bExp = extractFloat128Exp( b );\r
-    bSign = extractFloat128Sign( b );\r
-    zSign = aSign ^ bSign;\r
-    if ( aExp == 0x7FFF ) {\r
-        if ( aSig0 | aSig1 ) return propagateFloat128NaN( a, b );\r
-        if ( bExp == 0x7FFF ) {\r
-            if ( bSig0 | bSig1 ) return propagateFloat128NaN( a, b );\r
-            goto invalid;\r
-        }\r
-        return packFloat128( zSign, 0x7FFF, 0, 0 );\r
-    }\r
-    if ( bExp == 0x7FFF ) {\r
-        if ( bSig0 | bSig1 ) return propagateFloat128NaN( a, b );\r
-        return packFloat128( zSign, 0, 0, 0 );\r
-    }\r
-    if ( bExp == 0 ) {\r
-        if ( ( bSig0 | bSig1 ) == 0 ) {\r
-            if ( ( aExp | aSig0 | aSig1 ) == 0 ) {\r
- invalid:\r
-                float_raise( float_flag_invalid );\r
-                z.low = float128_default_nan_low;\r
-                z.high = float128_default_nan_high;\r
-                return z;\r
-            }\r
-            float_raise( float_flag_divbyzero );\r
-            return packFloat128( zSign, 0x7FFF, 0, 0 );\r
-        }\r
-        normalizeFloat128Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 );\r
-    }\r
-    if ( aExp == 0 ) {\r
-        if ( ( aSig0 | aSig1 ) == 0 ) return packFloat128( zSign, 0, 0, 0 );\r
-        normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );\r
-    }\r
-    zExp = aExp - bExp + 0x3FFD;\r
-    shortShift128Left(\r
-        aSig0 | LIT64( 0x0001000000000000 ), aSig1, 15, &aSig0, &aSig1 );\r
-    shortShift128Left(\r
-        bSig0 | LIT64( 0x0001000000000000 ), bSig1, 15, &bSig0, &bSig1 );\r
-    if ( le128( bSig0, bSig1, aSig0, aSig1 ) ) {\r
-        shift128Right( aSig0, aSig1, 1, &aSig0, &aSig1 );\r
-        ++zExp;\r
-    }\r
-    zSig0 = estimateDiv128To64( aSig0, aSig1, bSig0 );\r
-    mul128By64To192( bSig0, bSig1, zSig0, &term0, &term1, &term2 );\r
-    sub192( aSig0, aSig1, 0, term0, term1, term2, &rem0, &rem1, &rem2 );\r
-    while ( (sbits64) rem0 < 0 ) {\r
-        --zSig0;\r
-        add192( rem0, rem1, rem2, 0, bSig0, bSig1, &rem0, &rem1, &rem2 );\r
-    }\r
-    zSig1 = estimateDiv128To64( rem1, rem2, bSig0 );\r
-    if ( ( zSig1 & 0x3FFF ) <= 4 ) {\r
-        mul128By64To192( bSig0, bSig1, zSig1, &term1, &term2, &term3 );\r
-        sub192( rem1, rem2, 0, term1, term2, term3, &rem1, &rem2, &rem3 );\r
-        while ( (sbits64) rem1 < 0 ) {\r
-            --zSig1;\r
-            add192( rem1, rem2, rem3, 0, bSig0, bSig1, &rem1, &rem2, &rem3 );\r
-        }\r
-        zSig1 |= ( ( rem1 | rem2 | rem3 ) != 0 );\r
-    }\r
-    shift128ExtraRightJamming( zSig0, zSig1, 0, 15, &zSig0, &zSig1, &zSig2 );\r
-    return roundAndPackFloat128( zSign, zExp, zSig0, zSig1, zSig2 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the remainder of the quadruple-precision floating-point value `a'\r
-| with respect to the corresponding value `b'.  The operation is performed\r
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float128 float128_rem( float128 a, float128 b )\r
-{\r
-    flag aSign, bSign, zSign;\r
-    int32 aExp, bExp, expDiff;\r
-    bits64 aSig0, aSig1, bSig0, bSig1, q, term0, term1, term2;\r
-    bits64 allZero, alternateASig0, alternateASig1, sigMean1;\r
-    sbits64 sigMean0;\r
-    float128 z;\r
-\r
-    aSig1 = extractFloat128Frac1( a );\r
-    aSig0 = extractFloat128Frac0( a );\r
-    aExp = extractFloat128Exp( a );\r
-    aSign = extractFloat128Sign( a );\r
-    bSig1 = extractFloat128Frac1( b );\r
-    bSig0 = extractFloat128Frac0( b );\r
-    bExp = extractFloat128Exp( b );\r
-    bSign = extractFloat128Sign( b );\r
-    if ( aExp == 0x7FFF ) {\r
-        if (    ( aSig0 | aSig1 )\r
-             || ( ( bExp == 0x7FFF ) && ( bSig0 | bSig1 ) ) ) {\r
-            return propagateFloat128NaN( a, b );\r
-        }\r
-        goto invalid;\r
-    }\r
-    if ( bExp == 0x7FFF ) {\r
-        if ( bSig0 | bSig1 ) return propagateFloat128NaN( a, b );\r
-        return a;\r
-    }\r
-    if ( bExp == 0 ) {\r
-        if ( ( bSig0 | bSig1 ) == 0 ) {\r
- invalid:\r
-            float_raise( float_flag_invalid );\r
-            z.low = float128_default_nan_low;\r
-            z.high = float128_default_nan_high;\r
-            return z;\r
-        }\r
-        normalizeFloat128Subnormal( bSig0, bSig1, &bExp, &bSig0, &bSig1 );\r
-    }\r
-    if ( aExp == 0 ) {\r
-        if ( ( aSig0 | aSig1 ) == 0 ) return a;\r
-        normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );\r
-    }\r
-    expDiff = aExp - bExp;\r
-    if ( expDiff < -1 ) return a;\r
-    shortShift128Left(\r
-        aSig0 | LIT64( 0x0001000000000000 ),\r
-        aSig1,\r
-        15 - ( expDiff < 0 ),\r
-        &aSig0,\r
-        &aSig1\r
-    );\r
-    shortShift128Left(\r
-        bSig0 | LIT64( 0x0001000000000000 ), bSig1, 15, &bSig0, &bSig1 );\r
-    q = le128( bSig0, bSig1, aSig0, aSig1 );\r
-    if ( q ) sub128( aSig0, aSig1, bSig0, bSig1, &aSig0, &aSig1 );\r
-    expDiff -= 64;\r
-    while ( 0 < expDiff ) {\r
-        q = estimateDiv128To64( aSig0, aSig1, bSig0 );\r
-        q = ( 4 < q ) ? q - 4 : 0;\r
-        mul128By64To192( bSig0, bSig1, q, &term0, &term1, &term2 );\r
-        shortShift192Left( term0, term1, term2, 61, &term1, &term2, &allZero );\r
-        shortShift128Left( aSig0, aSig1, 61, &aSig0, &allZero );\r
-        sub128( aSig0, 0, term1, term2, &aSig0, &aSig1 );\r
-        expDiff -= 61;\r
-    }\r
-    if ( -64 < expDiff ) {\r
-        q = estimateDiv128To64( aSig0, aSig1, bSig0 );\r
-        q = ( 4 < q ) ? q - 4 : 0;\r
-        q >>= - expDiff;\r
-        shift128Right( bSig0, bSig1, 12, &bSig0, &bSig1 );\r
-        expDiff += 52;\r
-        if ( expDiff < 0 ) {\r
-            shift128Right( aSig0, aSig1, - expDiff, &aSig0, &aSig1 );\r
-        }\r
-        else {\r
-            shortShift128Left( aSig0, aSig1, expDiff, &aSig0, &aSig1 );\r
-        }\r
-        mul128By64To192( bSig0, bSig1, q, &term0, &term1, &term2 );\r
-        sub128( aSig0, aSig1, term1, term2, &aSig0, &aSig1 );\r
-    }\r
-    else {\r
-        shift128Right( aSig0, aSig1, 12, &aSig0, &aSig1 );\r
-        shift128Right( bSig0, bSig1, 12, &bSig0, &bSig1 );\r
-    }\r
-    do {\r
-        alternateASig0 = aSig0;\r
-        alternateASig1 = aSig1;\r
-        ++q;\r
-        sub128( aSig0, aSig1, bSig0, bSig1, &aSig0, &aSig1 );\r
-    } while ( 0 <= (sbits64) aSig0 );\r
-    add128(\r
-        aSig0, aSig1, alternateASig0, alternateASig1, (bits64*)&sigMean0, &sigMean1 );\r
-    if (    ( sigMean0 < 0 )\r
-         || ( ( ( sigMean0 | sigMean1 ) == 0 ) && ( q & 1 ) ) ) {\r
-        aSig0 = alternateASig0;\r
-        aSig1 = alternateASig1;\r
-    }\r
-    zSign = ( (sbits64) aSig0 < 0 );\r
-    if ( zSign ) sub128( 0, 0, aSig0, aSig1, &aSig0, &aSig1 );\r
-    return\r
-        normalizeRoundAndPackFloat128( aSign ^ zSign, bExp - 4, aSig0, aSig1 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns the square root of the quadruple-precision floating-point value `a'.\r
-| The operation is performed according to the IEC/IEEE Standard for Binary\r
-| Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-float128 float128_sqrt( float128 a )\r
-{\r
-    flag aSign;\r
-    int32 aExp, zExp;\r
-    bits64 aSig0, aSig1, zSig0, zSig1, zSig2, doubleZSig0;\r
-    bits64 rem0, rem1, rem2, rem3, term0, term1, term2, term3;\r
-    float128 z;\r
-\r
-    aSig1 = extractFloat128Frac1( a );\r
-    aSig0 = extractFloat128Frac0( a );\r
-    aExp = extractFloat128Exp( a );\r
-    aSign = extractFloat128Sign( a );\r
-    if ( aExp == 0x7FFF ) {\r
-        if ( aSig0 | aSig1 ) return propagateFloat128NaN( a, a );\r
-        if ( ! aSign ) return a;\r
-        goto invalid;\r
-    }\r
-    if ( aSign ) {\r
-        if ( ( aExp | aSig0 | aSig1 ) == 0 ) return a;\r
- invalid:\r
-        float_raise( float_flag_invalid );\r
-        z.low = float128_default_nan_low;\r
-        z.high = float128_default_nan_high;\r
-        return z;\r
-    }\r
-    if ( aExp == 0 ) {\r
-        if ( ( aSig0 | aSig1 ) == 0 ) return packFloat128( 0, 0, 0, 0 );\r
-        normalizeFloat128Subnormal( aSig0, aSig1, &aExp, &aSig0, &aSig1 );\r
-    }\r
-    zExp = ( ( aExp - 0x3FFF )>>1 ) + 0x3FFE;\r
-    aSig0 |= LIT64( 0x0001000000000000 );\r
-    zSig0 = estimateSqrt32( aExp, aSig0>>17 );\r
-    shortShift128Left( aSig0, aSig1, 13 - ( aExp & 1 ), &aSig0, &aSig1 );\r
-    zSig0 = estimateDiv128To64( aSig0, aSig1, zSig0<<32 ) + ( zSig0<<30 );\r
-    doubleZSig0 = zSig0<<1;\r
-    mul64To128( zSig0, zSig0, &term0, &term1 );\r
-    sub128( aSig0, aSig1, term0, term1, &rem0, &rem1 );\r
-    while ( (sbits64) rem0 < 0 ) {\r
-        --zSig0;\r
-        doubleZSig0 -= 2;\r
-        add128( rem0, rem1, zSig0>>63, doubleZSig0 | 1, &rem0, &rem1 );\r
-    }\r
-    zSig1 = estimateDiv128To64( rem1, 0, doubleZSig0 );\r
-    if ( ( zSig1 & 0x1FFF ) <= 5 ) {\r
-        if ( zSig1 == 0 ) zSig1 = 1;\r
-        mul64To128( doubleZSig0, zSig1, &term1, &term2 );\r
-        sub128( rem1, 0, term1, term2, &rem1, &rem2 );\r
-        mul64To128( zSig1, zSig1, &term2, &term3 );\r
-        sub192( rem1, rem2, 0, 0, term2, term3, &rem1, &rem2, &rem3 );\r
-        while ( (sbits64) rem1 < 0 ) {\r
-            --zSig1;\r
-            shortShift128Left( 0, zSig1, 1, &term2, &term3 );\r
-            term3 |= 1;\r
-            term2 |= doubleZSig0;\r
-            add192( rem1, rem2, rem3, 0, term2, term3, &rem1, &rem2, &rem3 );\r
-        }\r
-        zSig1 |= ( ( rem1 | rem2 | rem3 ) != 0 );\r
-    }\r
-    shift128ExtraRightJamming( zSig0, zSig1, 0, 14, &zSig0, &zSig1, &zSig2 );\r
-    return roundAndPackFloat128( 0, zExp, zSig0, zSig1, zSig2 );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the quadruple-precision floating-point value `a' is equal to\r
-| the corresponding value `b', and 0 otherwise.  The comparison is performed\r
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag float128_eq( float128 a, float128 b )\r
-{\r
-\r
-    if (    (    ( extractFloat128Exp( a ) == 0x7FFF )\r
-              && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) )\r
-         || (    ( extractFloat128Exp( b ) == 0x7FFF )\r
-              && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )\r
-       ) {\r
-        if (    float128_is_signaling_nan( a )\r
-             || float128_is_signaling_nan( b ) ) {\r
-            float_raise( float_flag_invalid );\r
-        }\r
-        return 0;\r
-    }\r
-    return\r
-           ( a.low == b.low )\r
-        && (    ( a.high == b.high )\r
-             || (    ( a.low == 0 )\r
-                  && ( (bits64) ( ( a.high | b.high )<<1 ) == 0 ) )\r
-           );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the quadruple-precision floating-point value `a' is less than\r
-| or equal to the corresponding value `b', and 0 otherwise.  The comparison\r
-| is performed according to the IEC/IEEE Standard for Binary Floating-Point\r
-| Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag float128_le( float128 a, float128 b )\r
-{\r
-    flag aSign, bSign;\r
-\r
-    if (    (    ( extractFloat128Exp( a ) == 0x7FFF )\r
-              && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) )\r
-         || (    ( extractFloat128Exp( b ) == 0x7FFF )\r
-              && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )\r
-       ) {\r
-        float_raise( float_flag_invalid );\r
-        return 0;\r
-    }\r
-    aSign = extractFloat128Sign( a );\r
-    bSign = extractFloat128Sign( b );\r
-    if ( aSign != bSign ) {\r
-        return\r
-               aSign\r
-            || (    ( ( (bits64) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )\r
-                 == 0 );\r
-    }\r
-    return\r
-          aSign ? le128( b.high, b.low, a.high, a.low )\r
-        : le128( a.high, a.low, b.high, b.low );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the quadruple-precision floating-point value `a' is less than\r
-| the corresponding value `b', and 0 otherwise.  The comparison is performed\r
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag float128_lt( float128 a, float128 b )\r
-{\r
-    flag aSign, bSign;\r
-\r
-    if (    (    ( extractFloat128Exp( a ) == 0x7FFF )\r
-              && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) )\r
-         || (    ( extractFloat128Exp( b ) == 0x7FFF )\r
-              && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )\r
-       ) {\r
-        float_raise( float_flag_invalid );\r
-        return 0;\r
-    }\r
-    aSign = extractFloat128Sign( a );\r
-    bSign = extractFloat128Sign( b );\r
-    if ( aSign != bSign ) {\r
-        return\r
-               aSign\r
-            && (    ( ( (bits64) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )\r
-                 != 0 );\r
-    }\r
-    return\r
-          aSign ? lt128( b.high, b.low, a.high, a.low )\r
-        : lt128( a.high, a.low, b.high, b.low );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the quadruple-precision floating-point value `a' is equal to\r
-| the corresponding value `b', and 0 otherwise.  The invalid exception is\r
-| raised if either operand is a NaN.  Otherwise, the comparison is performed\r
-| according to the IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag float128_eq_signaling( float128 a, float128 b )\r
-{\r
-\r
-    if (    (    ( extractFloat128Exp( a ) == 0x7FFF )\r
-              && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) )\r
-         || (    ( extractFloat128Exp( b ) == 0x7FFF )\r
-              && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )\r
-       ) {\r
-        float_raise( float_flag_invalid );\r
-        return 0;\r
-    }\r
-    return\r
-           ( a.low == b.low )\r
-        && (    ( a.high == b.high )\r
-             || (    ( a.low == 0 )\r
-                  && ( (bits64) ( ( a.high | b.high )<<1 ) == 0 ) )\r
-           );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the quadruple-precision floating-point value `a' is less than\r
-| or equal to the corresponding value `b', and 0 otherwise.  Quiet NaNs do not\r
-| cause an exception.  Otherwise, the comparison is performed according to the\r
-| IEC/IEEE Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag float128_le_quiet( float128 a, float128 b )\r
-{\r
-    flag aSign, bSign;\r
-\r
-    if (    (    ( extractFloat128Exp( a ) == 0x7FFF )\r
-              && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) )\r
-         || (    ( extractFloat128Exp( b ) == 0x7FFF )\r
-              && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )\r
-       ) {\r
-        if (    float128_is_signaling_nan( a )\r
-             || float128_is_signaling_nan( b ) ) {\r
-            float_raise( float_flag_invalid );\r
-        }\r
-        return 0;\r
-    }\r
-    aSign = extractFloat128Sign( a );\r
-    bSign = extractFloat128Sign( b );\r
-    if ( aSign != bSign ) {\r
-        return\r
-               aSign\r
-            || (    ( ( (bits64) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )\r
-                 == 0 );\r
-    }\r
-    return\r
-          aSign ? le128( b.high, b.low, a.high, a.low )\r
-        : le128( a.high, a.low, b.high, b.low );\r
-\r
-}\r
-\r
-/*----------------------------------------------------------------------------\r
-| Returns 1 if the quadruple-precision floating-point value `a' is less than\r
-| the corresponding value `b', and 0 otherwise.  Quiet NaNs do not cause an\r
-| exception.  Otherwise, the comparison is performed according to the IEC/IEEE\r
-| Standard for Binary Floating-Point Arithmetic.\r
-*----------------------------------------------------------------------------*/\r
-\r
-flag float128_lt_quiet( float128 a, float128 b )\r
-{\r
-    flag aSign, bSign;\r
-\r
-    if (    (    ( extractFloat128Exp( a ) == 0x7FFF )\r
-              && ( extractFloat128Frac0( a ) | extractFloat128Frac1( a ) ) )\r
-         || (    ( extractFloat128Exp( b ) == 0x7FFF )\r
-              && ( extractFloat128Frac0( b ) | extractFloat128Frac1( b ) ) )\r
-       ) {\r
-        if (    float128_is_signaling_nan( a )\r
-             || float128_is_signaling_nan( b ) ) {\r
-            float_raise( float_flag_invalid );\r
-        }\r
-        return 0;\r
-    }\r
-    aSign = extractFloat128Sign( a );\r
-    bSign = extractFloat128Sign( b );\r
-    if ( aSign != bSign ) {\r
-        return\r
-               aSign\r
-            && (    ( ( (bits64) ( ( a.high | b.high )<<1 ) ) | a.low | b.low )\r
-                 != 0 );\r
-    }\r
-    return\r
-          aSign ? lt128( b.high, b.low, a.high, a.low )\r
-        : lt128( a.high, a.low, b.high, b.low );\r
-\r
-}\r
-\r
-#endif\r
-\r

diff --git a/softfloat/softfloat.cc b/softfloat/softfloat.cc
deleted file mode 100644 (file)
index c44e828..0000000
--- a/softfloat/softfloat.cc
+++ /dev/null
@@ -1 +0,0 @@
-#include "softfloat.c"

diff --git a/softfloat/softfloat.h b/softfloat/softfloat.h
old mode 100644 (file)
new mode 100755 (executable)
index fc3f9dc..a7ea248
--- a/softfloat/softfloat.h
+++ b/softfloat/softfloat.h
@@ -1,14 +1,225 @@
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef _SOFTFLOAT_H
-#define _SOFTFLOAT_H
-
-#include "softfloat-header"
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
+\r
+#ifndef softfloat_h\r
+#define softfloat_h\r
+\r
+/*** UPDATE COMMENTS. ***/\r
+\r
+/*============================================================================\r
+\r
+This C header file is part of the SoftFloat IEEE Floating-point Arithmetic\r
+Package, Release 2b.\r
+\r
+Written by John R. Hauser.  This work was made possible in part by the\r
+International Computer Science Institute, located at Suite 600, 1947 Center\r
+Street, Berkeley, California 94704.  Funding was partially provided by the\r
+National Science Foundation under grant MIP-9311980.  The original version\r
+of this code was written as part of a project to build a fixed-point vector\r
+processor in collaboration with the University of California at Berkeley,\r
+overseen by Profs. Nelson Morgan and John Wawrzynek.  More information\r
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
+arithmetic/SoftFloat.html'.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has\r
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
+RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
+\r
+Derivative works are acceptable, even for commercial purposes, so long as\r
+(1) the source code for the derivative work includes prominent notice that\r
+the work is derivative, and (2) the source code includes prominent notice with\r
+these four paragraphs for those parts of this code that are retained.\r
+\r
+=============================================================================*/\r
+\r
+#include "softfloat_types.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software floating-point underflow tininess-detection mode.\r
+*----------------------------------------------------------------------------*/\r
+extern int_fast8_t softfloat_detectTininess;\r
+enum {\r
+    softfloat_tininess_beforeRounding = 0,\r
+    softfloat_tininess_afterRounding  = 1\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software floating-point rounding mode.\r
+*----------------------------------------------------------------------------*/\r
+extern int_fast8_t softfloat_roundingMode;\r
+enum {\r
+    softfloat_round_nearest_even   = 0,\r
+    softfloat_round_minMag         = 1,\r
+    softfloat_round_min            = 2,\r
+    softfloat_round_max            = 3,\r
+    softfloat_round_nearest_maxMag = 4\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+| Software floating-point exception flags.\r
+*----------------------------------------------------------------------------*/\r
+extern int_fast8_t softfloat_exceptionFlags;\r
+enum {\r
+    softfloat_flag_inexact   =  1,\r
+    softfloat_flag_underflow =  2,\r
+    softfloat_flag_overflow  =  4,\r
+    softfloat_flag_infinity  =  8,\r
+    softfloat_flag_invalid   = 16\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+| Routine to raise any or all of the software floating-point exception flags.\r
+*----------------------------------------------------------------------------*/\r
+void softfloat_raiseFlags( int_fast8_t );\r
+\r
+/*----------------------------------------------------------------------------\r
+| Integer-to-floating-point conversion routines.\r
+*----------------------------------------------------------------------------*/\r
+float32_t ui32_to_f32( uint_fast32_t );\r
+float64_t ui32_to_f64( uint_fast32_t );\r
+floatx80_t ui32_to_fx80( uint_fast32_t );\r
+float128_t ui32_to_f128( uint_fast32_t );\r
+float32_t ui64_to_f32( uint_fast64_t );\r
+float64_t ui64_to_f64( uint_fast64_t );\r
+floatx80_t ui64_to_fx80( uint_fast64_t );\r
+float128_t ui64_to_f128( uint_fast64_t );\r
+float32_t i32_to_f32( int_fast32_t );\r
+float64_t i32_to_f64( int_fast32_t );\r
+floatx80_t i32_to_fx80( int_fast32_t );\r
+float128_t i32_to_f128( int_fast32_t );\r
+float32_t i64_to_f32( int_fast64_t );\r
+float64_t i64_to_f64( int_fast64_t );\r
+floatx80_t i64_to_fx80( int_fast64_t );\r
+float128_t i64_to_f128( int_fast64_t );\r
+\r
+/*----------------------------------------------------------------------------\r
+| 32-bit (single-precision) floating-point operations.\r
+*----------------------------------------------------------------------------*/\r
+uint_fast32_t f32_to_ui32( float32_t, int_fast8_t, bool );\r
+uint_fast64_t f32_to_ui64( float32_t, int_fast8_t, bool );\r
+int_fast32_t f32_to_i32( float32_t, int_fast8_t, bool );\r
+int_fast64_t f32_to_i64( float32_t, int_fast8_t, bool );\r
+uint_fast32_t f32_to_ui32_r_minMag( float32_t, bool );\r
+uint_fast64_t f32_to_ui64_r_minMag( float32_t, bool );\r
+int_fast32_t f32_to_i32_r_minMag( float32_t, bool );\r
+int_fast64_t f32_to_i64_r_minMag( float32_t, bool );\r
+float64_t f32_to_f64( float32_t );\r
+floatx80_t f32_to_fx80( float32_t );\r
+float128_t f32_to_f128( float32_t );\r
+float32_t f32_roundToInt( float32_t, int_fast8_t, bool );\r
+float32_t f32_add( float32_t, float32_t );\r
+float32_t f32_sub( float32_t, float32_t );\r
+float32_t f32_mul( float32_t, float32_t );\r
+float32_t f32_mulAdd( float32_t, float32_t, float32_t );\r
+float32_t f32_div( float32_t, float32_t );\r
+float32_t f32_rem( float32_t, float32_t );\r
+float32_t f32_sqrt( float32_t );\r
+bool f32_eq( float32_t, float32_t );\r
+bool f32_le( float32_t, float32_t );\r
+bool f32_lt( float32_t, float32_t );\r
+bool f32_eq_signaling( float32_t, float32_t );\r
+bool f32_le_quiet( float32_t, float32_t );\r
+bool f32_lt_quiet( float32_t, float32_t );\r
+bool f32_isSignalingNaN( float32_t );\r
+\r
+/*----------------------------------------------------------------------------\r
+| 64-bit (double-precision) floating-point operations.\r
+*----------------------------------------------------------------------------*/\r
+uint_fast32_t f64_to_ui32( float64_t, int_fast8_t, bool );\r
+uint_fast64_t f64_to_ui64( float64_t, int_fast8_t, bool );\r
+int_fast32_t f64_to_i32( float64_t, int_fast8_t, bool );\r
+int_fast64_t f64_to_i64( float64_t, int_fast8_t, bool );\r
+uint_fast32_t f64_to_ui32_r_minMag( float64_t, bool );\r
+uint_fast64_t f64_to_ui64_r_minMag( float64_t, bool );\r
+int_fast32_t f64_to_i32_r_minMag( float64_t, bool );\r
+int_fast64_t f64_to_i64_r_minMag( float64_t, bool );\r
+float32_t f64_to_f32( float64_t );\r
+floatx80_t f64_to_fx80( float64_t );\r
+float128_t f64_to_f128( float64_t );\r
+float64_t f64_roundToInt( float64_t, int_fast8_t, bool );\r
+float64_t f64_add( float64_t, float64_t );\r
+float64_t f64_sub( float64_t, float64_t );\r
+float64_t f64_mul( float64_t, float64_t );\r
+float64_t f64_mulAdd( float64_t, float64_t, float64_t );\r
+float64_t f64_div( float64_t, float64_t );\r
+float64_t f64_rem( float64_t, float64_t );\r
+float64_t f64_sqrt( float64_t );\r
+bool f64_eq( float64_t, float64_t );\r
+bool f64_le( float64_t, float64_t );\r
+bool f64_lt( float64_t, float64_t );\r
+bool f64_eq_signaling( float64_t, float64_t );\r
+bool f64_le_quiet( float64_t, float64_t );\r
+bool f64_lt_quiet( float64_t, float64_t );\r
+bool f64_isSignalingNaN( float64_t );\r
+\r
+/*----------------------------------------------------------------------------\r
+| Extended double-precision rounding precision.  Valid values are 32, 64, and\r
+| 80.\r
+*----------------------------------------------------------------------------*/\r
+extern int_fast8_t floatx80_roundingPrecision;\r
+\r
+/*----------------------------------------------------------------------------\r
+| Extended double-precision floating-point operations.\r
+*----------------------------------------------------------------------------*/\r
+uint_fast32_t fx80_to_ui32( floatx80_t, int_fast8_t, bool );\r
+uint_fast64_t fx80_to_ui64( floatx80_t, int_fast8_t, bool );\r
+int_fast32_t fx80_to_i32( floatx80_t, int_fast8_t, bool );\r
+int_fast64_t fx80_to_i64( floatx80_t, int_fast8_t, bool );\r
+uint_fast32_t fx80_to_ui32_r_minMag( floatx80_t, bool );\r
+uint_fast64_t fx80_to_ui64_r_minMag( floatx80_t, bool );\r
+int_fast32_t fx80_to_i32_r_minMag( floatx80_t, bool );\r
+int_fast64_t fx80_to_i64_r_minMag( floatx80_t, bool );\r
+float32_t fx80_to_f32( floatx80_t );\r
+float64_t fx80_to_f64( floatx80_t );\r
+float128_t fx80_to_f128( floatx80_t );\r
+floatx80_t fx80_roundToInt( floatx80_t, int_fast8_t, bool );\r
+floatx80_t fx80_add( floatx80_t, floatx80_t );\r
+floatx80_t fx80_sub( floatx80_t, floatx80_t );\r
+floatx80_t fx80_mul( floatx80_t, floatx80_t );\r
+floatx80_t fx80_mulAdd( floatx80_t, floatx80_t, floatx80_t );\r
+floatx80_t fx80_div( floatx80_t, floatx80_t );\r
+floatx80_t fx80_rem( floatx80_t, floatx80_t );\r
+floatx80_t fx80_sqrt( floatx80_t );\r
+bool fx80_eq( floatx80_t, floatx80_t );\r
+bool fx80_le( floatx80_t, floatx80_t );\r
+bool fx80_lt( floatx80_t, floatx80_t );\r
+bool fx80_eq_signaling( floatx80_t, floatx80_t );\r
+bool fx80_le_quiet( floatx80_t, floatx80_t );\r
+bool fx80_lt_quiet( floatx80_t, floatx80_t );\r
+bool fx80_isSignalingNaN( floatx80_t );\r
+\r
+/*----------------------------------------------------------------------------\r
+| 128-bit (quadruple-precision) floating-point operations.\r
+*----------------------------------------------------------------------------*/\r
+uint_fast32_t f128_to_ui32( float128_t, int_fast8_t, bool );\r
+uint_fast64_t f128_to_ui64( float128_t, int_fast8_t, bool );\r
+int_fast32_t f128_to_i32( float128_t, int_fast8_t, bool );\r
+int_fast64_t f128_to_i64( float128_t, int_fast8_t, bool );\r
+uint_fast32_t f128_to_ui32_r_minMag( float128_t, bool );\r
+uint_fast64_t f128_to_ui64_r_minMag( float128_t, bool );\r
+int_fast32_t f128_to_i32_r_minMag( float128_t, bool );\r
+int_fast64_t f128_to_i64_r_minMag( float128_t, bool );\r
+float32_t f128_to_f32( float128_t );\r
+float64_t f128_to_f64( float128_t );\r
+floatx80_t f128_to_fx80( float128_t );\r
+float128_t f128_roundToInt( float128_t, int_fast8_t, bool );\r
+float128_t f128_add( float128_t, float128_t );\r
+float128_t f128_sub( float128_t, float128_t );\r
+float128_t f128_mul( float128_t, float128_t );\r
+float128_t f128_mulAdd( float128_t, float128_t, float128_t );\r
+float128_t f128_div( float128_t, float128_t );\r
+float128_t f128_rem( float128_t, float128_t );\r
+float128_t f128_sqrt( float128_t );\r
+bool f128_eq( float128_t, float128_t );\r
+bool f128_le( float128_t, float128_t );\r
+bool f128_lt( float128_t, float128_t );\r
+bool f128_eq_signaling( float128_t, float128_t );\r
+bool f128_le_quiet( float128_t, float128_t );\r
+bool f128_lt_quiet( float128_t, float128_t );\r
+bool f128_isSignalingNaN( float128_t );\r
+\r
+#endif\r
+\r

diff --git a/softfloat/softfloat.mk.in b/softfloat/softfloat.mk.in
index 4f86e1258bf5e2b1af8d01d8d46461717dc0ecde..964bc478fbe185435a8624954872ea58191ad2e1 100644 (file)
--- a/softfloat/softfloat.mk.in
+++ b/softfloat/softfloat.mk.in
@@ -1,13 +1,112 @@
-softfloat_subproject_deps =
+softfloat_subproject_deps = \
+       sotfloat_riscv \
 
 softfloat_hdrs = \
-    softfloat.h \
-    softfloat-macros \
-    milieu.h \
-    softfloat-specialize \
+       internals.h \
+       primitives.h \
+       softfloat.h \
 
 softfloat_srcs = \
-       softfloat.cc \
+       f32_add.cc                      \
+       f32_div.cc                      \
+       f32_eq.cc                       \
+       f32_eq_signaling.cc             \
+       f32_isSignalingNaN.cc           \
+       f32_le.cc                       \
+       f32_le_quiet.cc                 \
+       f32_lt.cc                       \
+       f32_lt_quiet.cc                 \
+       f32_mulAdd.cc                   \
+       f32_mul.cc                      \
+       f32_rem.cc                      \
+       f32_roundToInt.cc               \
+       f32_sqrt.cc                     \
+       f32_sub.cc                      \
+       f32_to_f64.cc                   \
+       f32_to_i32.cc                   \
+       f32_to_i32_r_minMag.cc          \
+       f32_to_i64.cc                   \
+       f32_to_i64_r_minMag.cc          \
+       f32_to_ui32.cc                  \
+       f32_to_ui32_r_minMag.cc         \
+       f32_to_ui64.cc                  \
+       f32_to_ui64_r_minMag.cc         \
+       f64_add.cc                      \
+       f64_div.cc                      \
+       f64_eq.cc                       \
+       f64_eq_signaling.cc             \
+       f64_isSignalingNaN.cc           \
+       f64_le.cc                       \
+       f64_le_quiet.cc                 \
+       f64_lt.cc                       \
+       f64_lt_quiet.cc                 \
+       f64_mulAdd.cc                   \
+       f64_mul.cc                      \
+       f64_rem.cc                      \
+       f64_roundToInt.cc               \
+       f64_sqrt.cc                     \
+       f64_sub.cc                      \
+       f64_to_f32.cc                   \
+       f64_to_i32.cc                   \
+       f64_to_i32_r_minMag.cc          \
+       f64_to_i64.cc                   \
+       f64_to_i64_r_minMag.cc          \
+       f64_to_ui32.cc                  \
+       f64_to_ui32_r_minMag.cc         \
+       f64_to_ui64.cc                  \
+       f64_to_ui64_r_minMag.cc         \
+       i32_to_f32.cc                   \
+       i32_to_f64.cc                   \
+       i64_to_f32.cc                   \
+       i64_to_f64.cc                   \
+       s_add128.cc                     \
+       s_add192.cc                     \
+       s_addMagsF32.cc                 \
+       s_addMagsF64.cc                 \
+       s_countLeadingZeros32.cc        \
+       s_countLeadingZeros64.cc        \
+       s_countLeadingZeros8.cc         \
+       s_eq128.cc                      \
+       s_estimateDiv128To64.cc         \
+       s_estimateSqrt32.cc             \
+       s_le128.cc                      \
+       s_lt128.cc                      \
+       s_mul128By64To192.cc            \
+       s_mul128To256.cc                \
+       s_mul64To128.cc                 \
+       s_mulAddF32.cc                  \
+       s_mulAddF64.cc                  \
+       s_normRoundPackToF32.cc         \
+       s_normRoundPackToF64.cc         \
+       s_normSubnormalF32Sig.cc        \
+       s_normSubnormalF64Sig.cc        \
+       softfloat_state.cc              \
+       s_roundPackToF32.cc             \
+       s_roundPackToF64.cc             \
+       s_roundPackToI32.cc             \
+       s_roundPackToI64.cc             \
+       s_roundPackToUI32.cc            \
+       s_roundPackToUI64.cc            \
+       s_shift128ExtraRightJam.cc      \
+       s_shift128RightJam.cc           \
+       s_shift32RightJam.cc            \
+       s_shift64ExtraRightJam.cc       \
+       s_shift64RightJam.cc            \
+       s_shortShift128ExtraRightJam.cc \
+       s_shortShift128Left.cc          \
+       s_shortShift128Right.cc         \
+       s_shortShift192Left.cc          \
+       s_shortShift32Right1Jam.cc      \
+       s_shortShift64ExtraRightJam.cc  \
+       s_shortShift64RightJam.cc       \
+       s_sub128.cc                     \
+       s_sub192.cc                     \
+       s_subMagsF32.cc                 \
+       s_subMagsF64.cc                 \
+       ui32_to_f32.cc                  \
+       ui32_to_f64.cc                  \
+       ui64_to_f32.cc                  \
+       ui64_to_f64.cc                  \
 
 softfloat_test_srcs =
 

diff --git a/softfloat/softfloat_state.cc b/softfloat/softfloat_state.cc
new file mode 100755 (executable)
index 0000000..8859089
--- /dev/null
+++ b/softfloat/softfloat_state.cc
@@ -0,0 +1,19 @@
+\r
+/*** COMMENTS. ***/\r
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "internals.h"\r
+#include "specialize.h"\r
+#include "softfloat.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+| Floating-point rounding mode, extended double-precision rounding precision,\r
+| and exception flags.\r
+*----------------------------------------------------------------------------*/\r
+int_fast8_t softfloat_roundingMode = softfloat_round_nearest_even;\r
+int_fast8_t softfloat_detectTininess = init_detectTininess;\r
+int_fast8_t softfloat_exceptionFlags = 0;\r
+\r
+int_fast8_t floatx80_roundingPrecision = 80;\r
+\r

diff --git a/softfloat/ui32_to_f32.cc b/softfloat/ui32_to_f32.cc
new file mode 100755 (executable)
index 0000000..ba0fc1a
--- /dev/null
+++ b/softfloat/ui32_to_f32.cc
@@ -0,0 +1,25 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+float32_t ui32_to_f32( uint_fast32_t a )\r
+{\r
+    union ui32_f32 uZ;\r
+\r
+    if ( ! a ) {\r
+        uZ.ui = 0;\r
+        return uZ.f;\r
+    }\r
+    if ( a & 0x80000000 ) {\r
+        return\r
+            softfloat_roundPackToF32(\r
+                0, 0x9D, softfloat_shortShift32Right1Jam( a ) );\r
+    } else {\r
+        return softfloat_normRoundPackToF32( 0, 0x9C, a );\r
+    }\r
+\r
+}\r
+\r

diff --git a/softfloat/ui32_to_f64.cc b/softfloat/ui32_to_f64.cc
new file mode 100755 (executable)
index 0000000..d0bd177
--- /dev/null
+++ b/softfloat/ui32_to_f64.cc
@@ -0,0 +1,26 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+float64_t ui32_to_f64( uint_fast32_t a )\r
+{\r
+    uint_fast64_t uiZ;\r
+    int shiftCount;\r
+    union ui64_f64 uZ;\r
+\r
+    if ( ! a ) {\r
+        uiZ = 0;\r
+    } else {\r
+        shiftCount = softfloat_countLeadingZeros32( a ) + 21;\r
+        uiZ =\r
+            packToF64UI(\r
+                0, 0x432 - shiftCount, (uint_fast64_t) a<<shiftCount );\r
+    }\r
+    uZ.ui = uiZ;\r
+    return uZ.f;\r
+\r
+}\r
+\r

diff --git a/softfloat/ui64_to_f32.cc b/softfloat/ui64_to_f32.cc
new file mode 100755 (executable)
index 0000000..82afbdc
--- /dev/null
+++ b/softfloat/ui64_to_f32.cc
@@ -0,0 +1,31 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+float32_t ui64_to_f32( uint_fast64_t a )\r
+{\r
+    int shiftCount;\r
+    union ui32_f32 u;\r
+    uint_fast32_t sig;\r
+\r
+    shiftCount = softfloat_countLeadingZeros64( a ) - 40;\r
+    if ( 0 <= shiftCount ) {\r
+        u.ui =\r
+            a ? packToF32UI(\r
+                    0, 0x95 - shiftCount, (uint_fast32_t) a<<shiftCount )\r
+                : 0;\r
+        return u.f;\r
+    } else {\r
+        shiftCount += 7;\r
+        sig =\r
+            ( shiftCount < 0 )\r
+                ? softfloat_shortShift64RightJam( a, - shiftCount )\r
+                : (uint_fast32_t) a<<shiftCount;\r
+        return softfloat_roundPackToF32( 0, 0x9C - shiftCount, sig );\r
+    }\r
+\r
+}\r
+\r

diff --git a/softfloat/ui64_to_f64.cc b/softfloat/ui64_to_f64.cc
new file mode 100755 (executable)
index 0000000..52c158b
--- /dev/null
+++ b/softfloat/ui64_to_f64.cc
@@ -0,0 +1,25 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "primitives.h"\r
+#include "internals.h"\r
+#include "softfloat.h"\r
+\r
+float64_t ui64_to_f64( uint_fast64_t a )\r
+{\r
+    union ui64_f64 uZ;\r
+\r
+    if ( ! a ) {\r
+        uZ.ui = 0;\r
+        return uZ.f;\r
+    }\r
+    if ( a & UINT64_C( 0x8000000000000000 ) ) {\r
+        return\r
+            softfloat_roundPackToF64(\r
+                0, 0x43D, softfloat_shortShift64RightJam( a, 1 ) );\r
+    } else {\r
+        return softfloat_normRoundPackToF64( 0, 0x43C, a );\r
+    }\r
+\r
+}\r
+\r

diff --git a/softfloat_riscv/platform.h b/softfloat_riscv/platform.h
new file mode 100755 (executable)
index 0000000..6c54313
--- /dev/null
+++ b/softfloat_riscv/platform.h
@@ -0,0 +1,42 @@
+
+/*============================================================================
+
+*** FIX.
+
+This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
+Arithmetic Package, Release 2b.
+
+Written by John R. Hauser.  This work was made possible in part by the
+International Computer Science Institute, located at Suite 600, 1947 Center
+Street, Berkeley, California 94704.  Funding was partially provided by the
+National Science Foundation under grant MIP-9311980.  The original version
+of this code was written as part of a project to build a fixed-point vector
+processor in collaboration with the University of California at Berkeley,
+overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/
+arithmetic/SoftFloat.html'.
+
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
+RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
+
+Derivative works are acceptable, even for commercial purposes, so long as
+(1) the source code for the derivative work includes prominent notice that
+the work is derivative, and (2) the source code includes prominent notice with
+these four paragraphs for those parts of this code that are retained.
+
+=============================================================================*/
+
+/*----------------------------------------------------------------------------
+*----------------------------------------------------------------------------*/
+#define LITTLEENDIAN
+
+#ifndef UINT64_C
+# define UINT64_C(x) (x ## ULL)
+# define INT64_C(x) (x ## LL)
+#endif

diff --git a/softfloat_riscv/s_commonNaNToF32UI.cc b/softfloat_riscv/s_commonNaNToF32UI.cc
new file mode 100755 (executable)
index 0000000..61f2735
--- /dev/null
+++ b/softfloat_riscv/s_commonNaNToF32UI.cc
@@ -0,0 +1,17 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "specialize.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the canonical NaN `a' to the single-\r
+| precision floating-point format.\r
+*----------------------------------------------------------------------------*/\r
+\r
+uint_fast32_t softfloat_commonNaNToF32UI( struct commonNaN a )\r
+{\r
+\r
+    return (uint_fast32_t) a.sign<<31 | 0x7FFFFFFF;\r
+\r
+}\r
+\r

diff --git a/softfloat_riscv/s_commonNaNToF64UI.cc b/softfloat_riscv/s_commonNaNToF64UI.cc
new file mode 100755 (executable)
index 0000000..da36c04
--- /dev/null
+++ b/softfloat_riscv/s_commonNaNToF64UI.cc
@@ -0,0 +1,18 @@
+
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+
+/*----------------------------------------------------------------------------
+| Returns the result of converting the canonical NaN `a' to the double-
+| precision floating-point format.
+*----------------------------------------------------------------------------*/
+
+uint_fast64_t softfloat_commonNaNToF64UI( struct commonNaN a )
+{
+
+    return
+        (uint_fast64_t) a.sign<<63 | UINT64_C( 0x7FFFFFFFFFFFFFFF );
+
+}
+

diff --git a/softfloat_riscv/s_f32UIToCommonNaN.cc b/softfloat_riscv/s_f32UIToCommonNaN.cc
new file mode 100755 (executable)
index 0000000..9ee0db9
--- /dev/null
+++ b/softfloat_riscv/s_f32UIToCommonNaN.cc
@@ -0,0 +1,25 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "specialize.h"\r
+#include "softfloat.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the single-precision floating-point NaN\r
+| `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid\r
+| exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+struct commonNaN softfloat_f32UIToCommonNaN( uint_fast32_t uiA )\r
+{\r
+    struct commonNaN z;\r
+\r
+    if ( softfloat_isSigNaNF32UI( uiA ) ) {\r
+        softfloat_raiseFlags( softfloat_flag_invalid );\r
+    }\r
+    z.sign = uiA>>31;\r
+    z.v64 = (uint_fast64_t) 0x7FFFF <<41;\r
+    z.v0 = 0;\r
+    return z;\r
+\r
+}\r
+\r

diff --git a/softfloat_riscv/s_f64UIToCommonNaN.cc b/softfloat_riscv/s_f64UIToCommonNaN.cc
new file mode 100755 (executable)
index 0000000..84d8ca0
--- /dev/null
+++ b/softfloat_riscv/s_f64UIToCommonNaN.cc
@@ -0,0 +1,25 @@
+\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "specialize.h"\r
+#include "softfloat.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns the result of converting the double-precision floating-point NaN\r
+| `a' to the canonical NaN format.  If `a' is a signaling NaN, the invalid\r
+| exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+struct commonNaN softfloat_f64UIToCommonNaN( uint_fast64_t uiA )\r
+{\r
+    struct commonNaN z;\r
+\r
+    if ( softfloat_isSigNaNF64UI( uiA ) ) {\r
+        softfloat_raiseFlags( softfloat_flag_invalid );\r
+    }\r
+    z.sign = uiA>>63;\r
+    z.v64 = (uint_fast64_t) 0xFFFFFFFFFFFFF <<12;\r
+    z.v0 = 0;\r
+    return z;\r
+\r
+}\r
+\r

diff --git a/softfloat_riscv/s_isSigNaNF32UI.cc b/softfloat_riscv/s_isSigNaNF32UI.cc
new file mode 100755 (executable)
index 0000000..0a9c33f
--- /dev/null
+++ b/softfloat_riscv/s_isSigNaNF32UI.cc
@@ -0,0 +1,13 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+
+bool softfloat_isSigNaNF32UI( uint_fast32_t ui )
+{
+
+    return ( ( ui>>22 & 0x1FF ) == 0x1FE ) && ( ui & 0x003FFFFF );
+
+}
+

diff --git a/softfloat_riscv/s_isSigNaNF64UI.cc b/softfloat_riscv/s_isSigNaNF64UI.cc
new file mode 100755 (executable)
index 0000000..d255213
--- /dev/null
+++ b/softfloat_riscv/s_isSigNaNF64UI.cc
@@ -0,0 +1,15 @@
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "specialize.h"
+
+bool softfloat_isSigNaNF64UI( uint_fast64_t ui )
+{
+
+    return
+        ( ( ui>>51 & 0xFFF ) == 0xFFE )
+            && ( ui & UINT64_C( 0x0007FFFFFFFFFFFF ) );
+
+}
+

diff --git a/softfloat_riscv/s_propagateNaNF32UI.cc b/softfloat_riscv/s_propagateNaNF32UI.cc
new file mode 100755 (executable)
index 0000000..07774e8
--- /dev/null
+++ b/softfloat_riscv/s_propagateNaNF32UI.cc
@@ -0,0 +1,55 @@
+\r
+/*** UPDATE COMMENTS. ***/\r
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+#include "platform.h"\r
+#include "internals.h"\r
+#include "specialize.h"\r
+#include "softfloat.h"\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes two single-precision floating-point values `a' and `b', one of which\r
+| is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a\r
+| signaling NaN, the invalid exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+\r
+uint_fast32_t\r
+ softfloat_propagateNaNF32UI( uint_fast32_t uiA, uint_fast32_t uiB )\r
+{\r
+    bool isNaNA, isSigNaNA, isNaNB, isSigNaNB;\r
+    uint_fast32_t uiMagA, uiMagB;\r
+\r
+    /*------------------------------------------------------------------------\r
+    *------------------------------------------------------------------------*/\r
+    isNaNA = isNaNF32UI( uiA );\r
+    isSigNaNA = softfloat_isSigNaNF32UI( uiA );\r
+    isNaNB = isNaNF32UI( uiB );\r
+    isSigNaNB = softfloat_isSigNaNF32UI( uiB );\r
+    /*------------------------------------------------------------------------\r
+    | Make NaNs non-signaling.\r
+    *------------------------------------------------------------------------*/\r
+    uiA |= 0x00400000;\r
+    uiB |= 0x00400000;\r
+    /*------------------------------------------------------------------------\r
+    *------------------------------------------------------------------------*/\r
+    if ( isSigNaNA | isSigNaNB ) {\r
+        softfloat_raiseFlags( softfloat_flag_invalid );\r
+    }\r
+    if ( isSigNaNA ) {\r
+        if ( isSigNaNB ) goto returnLargerSignificand;\r
+        return isNaNB ? uiB : uiA;\r
+    } else if ( isNaNA ) {\r
+        if ( isSigNaNB || ! isNaNB ) return uiA;\r
+ returnLargerSignificand:\r
+        uiMagA = uiA<<1;\r
+        uiMagB = uiB<<1;\r
+        if ( uiMagA < uiMagB ) return uiB;\r
+        if ( uiMagB < uiMagA ) return uiA;\r
+        return ( uiA < uiB ) ? uiA : uiB;\r
+    } else {\r
+        return uiB;\r
+    }\r
+\r
+}\r
+\r

diff --git a/softfloat_riscv/s_propagateNaNF64UI.cc b/softfloat_riscv/s_propagateNaNF64UI.cc
new file mode 100755 (executable)
index 0000000..0ff6446
--- /dev/null
+++ b/softfloat_riscv/s_propagateNaNF64UI.cc
@@ -0,0 +1,55 @@
+
+/*** UPDATE COMMENTS. ***/
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "platform.h"
+#include "internals.h"
+#include "specialize.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Takes two double-precision floating-point values `a' and `b', one of which
+| is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a
+| signaling NaN, the invalid exception is raised.
+*----------------------------------------------------------------------------*/
+
+uint_fast64_t
+ softfloat_propagateNaNF64UI( uint_fast64_t uiA, uint_fast64_t uiB )
+{
+    bool isNaNA, isSigNaNA, isNaNB, isSigNaNB;
+    uint_fast64_t uiMagA, uiMagB;
+
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    isNaNA = isNaNF64UI( uiA );
+    isSigNaNA = softfloat_isSigNaNF64UI( uiA );
+    isNaNB = isNaNF64UI( uiB );
+    isSigNaNB = softfloat_isSigNaNF64UI( uiB );
+    /*------------------------------------------------------------------------
+    | Make NaNs non-signaling.
+    *------------------------------------------------------------------------*/
+    uiA |= UINT64_C( 0x0008000000000000 );
+    uiB |= UINT64_C( 0x0008000000000000 );
+    /*------------------------------------------------------------------------
+    *------------------------------------------------------------------------*/
+    if ( isSigNaNA | isSigNaNB ) {
+        softfloat_raiseFlags( softfloat_flag_invalid );
+    }
+    if ( isSigNaNA ) {
+        if ( isSigNaNB ) goto returnLargerSignificand;
+        return isNaNB ? uiB : uiA;
+    } else if ( isNaNA ) {
+        if ( isSigNaNB || ! isNaNB ) return uiA;
+ returnLargerSignificand:
+        uiMagA = uiA & UINT64_C( 0x7FFFFFFFFFFFFFFF );
+        uiMagB = uiB & UINT64_C( 0x7FFFFFFFFFFFFFFF );
+        if ( uiMagA < uiMagB ) return uiB;
+        if ( uiMagB < uiMagA ) return uiA;
+        return ( uiA < uiB ) ? uiA : uiB;
+    } else {
+        return uiB;
+    }
+
+}
+

diff --git a/softfloat_riscv/softfloat_raiseFlags.cc b/softfloat_riscv/softfloat_raiseFlags.cc
new file mode 100755 (executable)
index 0000000..c0c0dc8
--- /dev/null
+++ b/softfloat_riscv/softfloat_raiseFlags.cc
@@ -0,0 +1,51 @@
+
+/*============================================================================
+
+*** FIX.
+
+This C source fragment is part of the SoftFloat IEC/IEEE Floating-point
+Arithmetic Package, Release 2b.
+
+Written by John R. Hauser.  This work was made possible in part by the
+International Computer Science Institute, located at Suite 600, 1947 Center
+Street, Berkeley, California 94704.  Funding was partially provided by the
+National Science Foundation under grant MIP-9311980.  The original version
+of this code was written as part of a project to build a fixed-point vector
+processor in collaboration with the University of California at Berkeley,
+overseen by Profs. Nelson Morgan and John Wawrzynek.  More information
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/
+arithmetic/SoftFloat.html'.
+
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES
+RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.
+
+Derivative works are acceptable, even for commercial purposes, so long as
+(1) the source code for the derivative work includes prominent notice that
+the work is derivative, and (2) the source code includes prominent notice with
+these four paragraphs for those parts of this code that are retained.
+
+=============================================================================*/
+
+#include "platform.h"
+#include "softfloat.h"
+
+/*----------------------------------------------------------------------------
+| Raises the exceptions specified by `flags'.  Floating-point traps can be
+| defined here if desired.  It is currently not possible for such a trap
+| to substitute a result value.  If traps are not implemented, this routine
+| should be simply `float_exception_flags |= flags;'.
+*----------------------------------------------------------------------------*/
+
+void softfloat_raiseFlags( int_fast8_t flags )
+{
+
+    softfloat_exceptionFlags |= flags;
+
+}
+

diff --git a/softfloat_riscv/softfloat_riscv.ac b/softfloat_riscv/softfloat_riscv.ac
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/softfloat_riscv/softfloat_riscv.mk.in b/softfloat_riscv/softfloat_riscv.mk.in
new file mode 100644 (file)
index 0000000..0b996fb
--- /dev/null
+++ b/softfloat_riscv/softfloat_riscv.mk.in
@@ -0,0 +1,21 @@
+softfloat_riscv_subproject_deps = \
+
+softfloat_riscv_hdrs = \
+       softfloat_types.h \
+       platform.h        \
+       specialize.h      \
+
+softfloat_riscv_srcs = \
+       softfloat_raiseFlags.cc \
+       s_commonNaNToF32UI.cc   \
+       s_commonNaNToF64UI.cc   \
+       s_f32UIToCommonNaN.cc   \
+       s_f64UIToCommonNaN.cc   \
+       s_isSigNaNF32UI.cc      \
+       s_isSigNaNF64UI.cc      \
+       s_propagateNaNF32UI.cc  \
+       s_propagateNaNF64UI.cc  \
+
+softfloat_riscv_test_srcs =
+
+softfloat_riscv_install_prog_srcs =

diff --git a/softfloat_riscv/softfloat_types.h b/softfloat_riscv/softfloat_types.h
new file mode 100755 (executable)
index 0000000..9fada89
--- /dev/null
+++ b/softfloat_riscv/softfloat_types.h
@@ -0,0 +1,16 @@
+
+#ifndef softfloat_types_h
+#define softfloat_types_h
+
+/*** COMMENTS. ***/
+
+#include <stdbool.h>
+#include <stdint.h>
+
+typedef uint32_t float32_t;
+typedef uint64_t float64_t;
+typedef struct { uint64_t v; uint16_t x; } floatx80_t;
+typedef struct { uint64_t v[ 2 ]; } float128_t;
+
+#endif
+

diff --git a/softfloat_riscv/specialize.h b/softfloat_riscv/specialize.h
new file mode 100755 (executable)
index 0000000..bf57bc9
--- /dev/null
+++ b/softfloat_riscv/specialize.h
@@ -0,0 +1,113 @@
+\r
+/*============================================================================\r
+\r
+*** FIX.\r
+\r
+This C source fragment is part of the SoftFloat IEC/IEEE Floating-point\r
+Arithmetic Package, Release 2b.\r
+\r
+Written by John R. Hauser.  This work was made possible in part by the\r
+International Computer Science Institute, located at Suite 600, 1947 Center\r
+Street, Berkeley, California 94704.  Funding was partially provided by the\r
+National Science Foundation under grant MIP-9311980.  The original version\r
+of this code was written as part of a project to build a fixed-point vector\r
+processor in collaboration with the University of California at Berkeley,\r
+overseen by Profs. Nelson Morgan and John Wawrzynek.  More information\r
+is available through the Web page `http://www.cs.berkeley.edu/~jhauser/\r
+arithmetic/SoftFloat.html'.\r
+\r
+THIS SOFTWARE IS DISTRIBUTED AS IS, FOR FREE.  Although reasonable effort has\r
+been made to avoid it, THIS SOFTWARE MAY CONTAIN FAULTS THAT WILL AT TIMES\r
+RESULT IN INCORRECT BEHAVIOR.  USE OF THIS SOFTWARE IS RESTRICTED TO PERSONS\r
+AND ORGANIZATIONS WHO CAN AND WILL TAKE FULL RESPONSIBILITY FOR ALL LOSSES,\r
+COSTS, OR OTHER PROBLEMS THEY INCUR DUE TO THE SOFTWARE, AND WHO FURTHERMORE\r
+EFFECTIVELY INDEMNIFY JOHN HAUSER AND THE INTERNATIONAL COMPUTER SCIENCE\r
+INSTITUTE (possibly via similar legal warning) AGAINST ALL LOSSES, COSTS, OR\r
+OTHER PROBLEMS INCURRED BY THEIR CUSTOMERS AND CLIENTS DUE TO THE SOFTWARE.\r
+\r
+Derivative works are acceptable, even for commercial purposes, so long as\r
+(1) the source code for the derivative work includes prominent notice that\r
+the work is derivative, and (2) the source code includes prominent notice with\r
+these four paragraphs for those parts of this code that are retained.\r
+\r
+=============================================================================*/\r
+\r
+#include <stdbool.h>\r
+#include <stdint.h>\r
+\r
+/*----------------------------------------------------------------------------\r
+*----------------------------------------------------------------------------*/\r
+#define init_detectTininess softfloat_tininess_beforeRounding;\r
+\r
+/*----------------------------------------------------------------------------\r
+| Structure used to transfer NaN representations from one format to another.\r
+*----------------------------------------------------------------------------*/\r
+struct commonNaN {\r
+    bool sign;\r
+    uint64_t v64, v0;\r
+};\r
+\r
+/*----------------------------------------------------------------------------\r
+| The pattern for a default generated single-precision NaN.\r
+*----------------------------------------------------------------------------*/\r
+#define defaultNaNF32UI 0xFFFFFFFF\r
+\r
+/*----------------------------------------------------------------------------\r
+| Returns 1 if the single-precision floating-point value `a' is a signaling\r
+| NaN; otherwise, returns 0.\r
+*----------------------------------------------------------------------------*/\r
+#if defined INLINE_LEVEL && ( 1 <= INLINE_LEVEL )\r
+INLINE bool softfloat_isSigNaNF32UI( uint_fast32_t ui )\r
+    { return ( ( ui>>22 & 0x1FF ) == 0x1FE ) && ( ui & 0x003FFFFF ); }\r
+#else\r
+bool softfloat_isSigNaNF32UI( uint_fast32_t );\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+*----------------------------------------------------------------------------*/\r
+struct commonNaN softfloat_f32UIToCommonNaN( uint_fast32_t );\r
+#if defined INLINE_LEVEL && ( 1 <= INLINE_LEVEL )\r
+INLINE uint_fast32_t softfloat_commonNaNToF32UI( struct commonNaN a )\r
+    { return (uint_fast32_t) a.sign<<31 | 0x7FFFFFFF; }\r
+#else\r
+uint_fast32_t softfloat_commonNaNToF32UI( struct commonNaN );\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes two single-precision floating-point values `a' and `b', one of which\r
+| is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a\r
+| signaling NaN, the invalid exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+uint_fast32_t softfloat_propagateNaNF32UI( uint_fast32_t, uint_fast32_t );\r
+\r
+/*----------------------------------------------------------------------------\r
+| The pattern for a default generated double-precision NaN.\r
+*----------------------------------------------------------------------------*/\r
+#define defaultNaNF64UI UINT64_C(0xFFF8000000000000)\r
+\r
+/*----------------------------------------------------------------------------\r
+*----------------------------------------------------------------------------*/\r
+#if defined INLINE_LEVEL && ( 1 <= INLINE_LEVEL )\r
+INLINE bool softfloat_isSigNaNF64UI( uint_fast64_t ui )\r
+{\r
+    return\r
+        ( ( ui>>51 & 0xFFF ) == 0xFFE )\r
+            && ( ui & UINT64_C( 0x0007FFFFFFFFFFFF ) );\r
+}\r
+#else\r
+bool softfloat_isSigNaNF64UI( uint_fast64_t );\r
+#endif\r
+\r
+/*----------------------------------------------------------------------------\r
+*----------------------------------------------------------------------------*/\r
+/*** MIGHT BE INLINE'D. ***/\r
+struct commonNaN softfloat_f64UIToCommonNaN( uint_fast64_t );\r
+uint_fast64_t softfloat_commonNaNToF64UI( struct commonNaN );\r
+\r
+/*----------------------------------------------------------------------------\r
+| Takes two double-precision floating-point values `a' and `b', one of which\r
+| is a NaN, and returns the appropriate NaN result.  If either `a' or `b' is a\r
+| signaling NaN, the invalid exception is raised.\r
+*----------------------------------------------------------------------------*/\r
+uint_fast64_t softfloat_propagateNaNF64UI( uint_fast64_t, uint_fast64_t );\r
+\r