Fix cells_sim.v for Achronix FPGA

diff --git a/techlibs/achronix/speedster22i/cells_sim.v b/techlibs/achronix/speedster22i/cells_sim.v
index da23fed7ecd642cfadb810345815c47d827bb23b..a94dce9b1a431ad28928c12e5903dfa84404f774 100755 (executable)
--- a/techlibs/achronix/speedster22i/cells_sim.v
+++ b/techlibs/achronix/speedster22i/cells_sim.v
@@ -61,7 +61,7 @@ reg [1:0]   s1;
   end
 endfunction
 
-always @(dataa_w or datab_w or datac_w or datad_w or cin_w) begin
+always @(dataa_w or datab_w or datac_w or datad_w) begin
    combout_rt = lut_data(lut_function, dataa_w, datab_w,
                          datac_w, datad_w);
 end