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diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index ecb6cf07d19f7cbbdcfbc0c0e071da170e967ab2..9fa50daca47c2552802f1eec1bbc72c5641f6823 100644 (file)
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -249,4 +249,5 @@ Here's the interesting part: given the fact that SV is a "context" extension, th
 
 It also turns out that by using a single bit set in the source or destination, *all* the sequential ordered standard patterns of Vector ISAs are provided: VSPLAT, VSELECT, VINSERT, VCOMPRESS, VEXPAND.
 
-The only one missing from the list here, because it is non-sequential, is VGATHER: moving registers by specifying a vector of register indices (`regs[rd] = regs[regs[rs]]` in a loop).
+The only one missing from the list here, because it is non-sequential, is VGATHER: moving registers by specifying a vector of register indices (`regs[rd] = regs[regs[rs]]` in a loop).  This one is tricky because it typically does not exist in standard scalar ISAs.  If it did it would be called [[sv/mv.x]]
+