Renamed some of the test cases in tests/simple to avoid name collisions

diff --git a/tests/simple/arraycells.v b/tests/simple/arraycells.v
index ad5098000eefb79428aef2536d5e7296a3325311..704ca3fdab83226642b0d5658ed34aeab091284a 100644 (file)
--- a/tests/simple/arraycells.v
+++ b/tests/simple/arraycells.v
@@ -1,5 +1,5 @@
 
-module test001(a, b, c, y);
+module array_test001(a, b, c, y);
        input a;
        input [31:0] b, c;
        input [31:0] y;

diff --git a/tests/simple/fsm.v b/tests/simple/fsm.v
index 79ca041dde363a2894325a17f78d4a4d411a8f19..2dba14bb042913601f15847643a479b2dd8c3396 100644 (file)
--- a/tests/simple/fsm.v
+++ b/tests/simple/fsm.v
@@ -1,7 +1,7 @@
 
 // `define ASYNC_RESET
 
-module test(clk, reset, button_a, button_b, red_a, green_a, red_b, green_b);
+module fsm_test(clk, reset, button_a, button_b, red_a, green_a, red_b, green_b);
 
 input clk, reset, button_a, button_b;
 output reg red_a, green_a, red_b, green_b;

diff --git a/tests/simple/generate.v b/tests/simple/generate.v
index 39e573a737d294e6cf806cb8e6bbb207678fdeab..24eb4462cd5d159aa63ee069e82ad99b98df3540 100644 (file)
--- a/tests/simple/generate.v
+++ b/tests/simple/generate.v
@@ -1,5 +1,5 @@
 
-module test1(clk, a, b, y);
+module gen_test1(clk, a, b, y);
 
 input clk;
 input [7:0] a, b;
@@ -40,7 +40,7 @@ endmodule
 
 // ------------------------------------------
 
-module test2(clk, a, b, y);
+module gen_test2(clk, a, b, y);
 
 input clk;
 input [7:0] a, b;
@@ -67,7 +67,7 @@ endmodule
 
 // ------------------------------------------
 
-module test3(a, b, sel, y, z);
+module gen_test3(a, b, sel, y, z);
 
 input [3:0] a, b;
 input sel;

diff --git a/tests/simple/i2c_master_tests.v b/tests/simple/i2c_master_tests.v
index f8f5640854c09be39e2595ae120661c53a3bdc7a..3aa596632db5dcba23b44d28173ab60f0935bf86 100644 (file)
--- a/tests/simple/i2c_master_tests.v
+++ b/tests/simple/i2c_master_tests.v
@@ -3,7 +3,7 @@
 // this core that triggered bugs in early versions of yosys.
 
 // from i2c_master_bit_ctrl
-module test01(clk, rst, nReset, al);
+module i2c_test01(clk, rst, nReset, al);
 
        input clk, rst, nReset;
        output reg al;
@@ -26,7 +26,7 @@ module test01(clk, rst, nReset, al);
 endmodule
 
 // from i2c_master_bit_ctrl
-module test02(clk, slave_wait, clk_cnt, cmd, cmd_stop, cnt);
+module i2c_test02(clk, slave_wait, clk_cnt, cmd, cmd_stop, cnt);
 
        input clk, slave_wait, clk_cnt;
        input cmd;

diff --git a/tests/simple/macros.v b/tests/simple/macros.v
index a3e8d70f87e701312081391f43edd275d6e4a7b2..7b4d616eae8cd787e7e02cb977d832e5b709e7d6 100644 (file)
--- a/tests/simple/macros.v
+++ b/tests/simple/macros.v
@@ -237,7 +237,7 @@ end
 endmodule
 
 `define SIZE 4 // comment supported in this part
-module test ( din_a, dout_a );
+module test_comment_in_macro ( din_a, dout_a );
 input [`SIZE-1:0] din_a;
 output [`SIZE-1:0] dout_a;
 assign dout_a = din_a | `SIZE'ha;

diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v
index 3630b57c7e76166f681cc9d58cb10093846a420b..bed5528d424669ef5bd4cd4c5bf79e998eb05740 100644 (file)
--- a/tests/simple/mem2reg.v
+++ b/tests/simple/mem2reg.v
@@ -1,5 +1,5 @@
 
-module test1(in_addr, in_data, out_addr, out_data);
+module mem2reg_test1(in_addr, in_data, out_addr, out_data);
 
 input [1:0] in_addr, out_addr;
 input [3:0] in_data;
@@ -19,7 +19,7 @@ endmodule
 
 // ------------------------------------------------------
 
-module test2(clk, mode, addr, data);
+module mem2reg_test2(clk, mode, addr, data);
 
 input clk, mode;
 input [2:0] addr;
@@ -46,7 +46,7 @@ endmodule
 // ------------------------------------------------------
 
 // http://www.reddit.com/r/yosys/comments/28d9lx/problem_with_concatenation_of_two_dimensional/
-module test3( input clk, input [8:0] din_a, output reg [7:0] dout_a, output [7:0] dout_b);
+module mem2reg_test3( input clk, input [8:0] din_a, output reg [7:0] dout_a, output [7:0] dout_b);
 reg [7:0] dint_c [0:7]; 
 always @(posedge clk)
   begin

diff --git a/tests/simple/memory.v b/tests/simple/memory.v
index ae63e8a16574db10d604e341535da1ef34b6be81..9fed1bf3ba9c7e2a3e1f3a0af959f34676db6e53 100644 (file)
--- a/tests/simple/memory.v
+++ b/tests/simple/memory.v
@@ -1,5 +1,5 @@
 
-module test00(clk, setA, setB, y);
+module memtest00(clk, setA, setB, y);
 
 input clk, setA, setB;
 output y;
@@ -16,7 +16,7 @@ endmodule
 
 // ----------------------------------------------------------
 
-module test01(clk, wr_en, wr_addr, wr_value, rd_addr, rd_value);
+module memtest01(clk, wr_en, wr_addr, wr_value, rd_addr, rd_value);
 
 input clk, wr_en;
 input [3:0] wr_addr, rd_addr;
@@ -36,7 +36,7 @@ endmodule
 
 // ----------------------------------------------------------
 
-module test02(clk, setA, setB, addr, bit, y1, y2, y3, y4);
+module memtest02(clk, setA, setB, addr, bit, y1, y2, y3, y4);
 
 input clk, setA, setB;
 input [1:0] addr;
@@ -77,7 +77,7 @@ endmodule
 
 // ----------------------------------------------------------
 
-module test03(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
+module memtest03(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
 
 input clk, wr_enable;
 input [3:0] wr_addr, wr_data, rd_addr;
@@ -95,7 +95,7 @@ endmodule
 
 // ----------------------------------------------------------
 
-module test04(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
+module memtest04(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
 
 input clk, wr_enable;
 input [3:0] wr_addr, wr_data, rd_addr;
@@ -116,7 +116,7 @@ endmodule
 
 // ----------------------------------------------------------
 
-module test05(clk, addr, wdata, rdata, wen);
+module memtest05(clk, addr, wdata, rdata, wen);
 
 input clk;
 input [1:0] addr;
@@ -137,7 +137,7 @@ endmodule
 
 // ----------------------------------------------------------
 
-module test06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
+module memtest06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
     (* gentb_constant=0 *) wire rst;
     reg [7:0] test [0:7];
     integer i;
@@ -156,7 +156,7 @@ module test06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, outpu
     assign dout = test[idx];
 endmodule
 
-module test06_async(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
+module memtest06_async(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
     (* gentb_constant=0 *) wire rst;
     reg [7:0] test [0:7];
     integer i;
@@ -177,7 +177,7 @@ endmodule
 
 // ----------------------------------------------------------
 
-module test07(clk, addr, woffset, wdata, rdata);
+module memtest07(clk, addr, woffset, wdata, rdata);
 
 input clk;
 input [1:0] addr;

diff --git a/tests/simple/operators.v b/tests/simple/operators.v
index 7439101c8c28e8ecae9e7959338339eb33606a57..2f0fdb82043e5018f95adcd50cca2b59cdddeacb 100644 (file)
--- a/tests/simple/operators.v
+++ b/tests/simple/operators.v
@@ -1,4 +1,4 @@
-module test(clk, mode, u1, s1, u2, s2, y);
+module optest(clk, mode, u1, s1, u2, s2, y);
 
 input clk;
 input [6:0] mode;

diff --git a/tests/simple/paramods.v b/tests/simple/paramods.v
index 8d0134a674508e032a6ae03d1704c622b03baae1..23cb276f22fa58ab4d87e07a08928ad9908d5662 100644 (file)
--- a/tests/simple/paramods.v
+++ b/tests/simple/paramods.v
@@ -1,5 +1,5 @@
 
-module test1(a, b, x, y);
+module pm_test1(a, b, x, y);
 
 input [7:0] a, b;
 output [7:0] x, y;
@@ -11,7 +11,7 @@ endmodule
 
 // -----------------------------------
 
-module test2(a, b, x, y);
+module pm_test2(a, b, x, y);
 
 input [7:0] a, b;
 output [7:0] x, y;
@@ -23,7 +23,7 @@ endmodule
 
 // -----------------------------------
 
-module test3(a, b, x, y);
+module pm_test3(a, b, x, y);
 
 input [7:0] a, b;
 output [7:0] x, y;

diff --git a/tests/simple/partsel.v b/tests/simple/partsel.v
index acfc1ca5d3bbf7fbe32a26633cf1c77746f17b49..9b1a99859f7445d89d8707c5d26ca36b367ce57c 100644 (file)
--- a/tests/simple/partsel.v
+++ b/tests/simple/partsel.v
@@ -1,4 +1,4 @@
-module test001(input [2:0] idx, input [31:0] data, output [3:0] slice_up, slice_down);
+module partsel_test001(input [2:0] idx, input [31:0] data, output [3:0] slice_up, slice_down);
 wire [5:0] offset = idx << 2;
 assign slice_up = data[offset +: 4];
 assign slice_down = data[offset + 3 -: 4];

diff --git a/tests/simple/repwhile.v b/tests/simple/repwhile.v
index cde37c563e4e6a5cf4d36abb27360da6ac14b65c..5d0c75fa60e6f7fcbf91f14847e68a1b85e8aa5b 100644 (file)
--- a/tests/simple/repwhile.v
+++ b/tests/simple/repwhile.v
@@ -1,4 +1,4 @@
-module test001(input [5:0] a, output [7:0] y, output [31:0] x);
+module repwhile_test001(input [5:0] a, output [7:0] y, output [31:0] x);
 
        function [7:0] mylog2;
                input [31:0] value;

diff --git a/tests/simple/signedexpr.v b/tests/simple/signedexpr.v
index 3eb5e93df6f5ca1e6713bbdb281f43fb359eaa6a..8bba4a4b16b39d28dbd99a9085d547f25da4f3f0 100644 (file)
--- a/tests/simple/signedexpr.v
+++ b/tests/simple/signedexpr.v
@@ -1,4 +1,4 @@
-module test01(a, b, xu, xs, yu, ys, zu, zs);
+module signed_test01(a, b, xu, xs, yu, ys, zu, zs);
 
 input signed [1:0] a;
 input signed [2:0] b;

diff --git a/tests/simple/task_func.v b/tests/simple/task_func.v
index 3a09cbc35a2743196e89802666a697c448f15af1..8dbc90c5662215a992eb1f0b97a3a9ebc4df0726 100644 (file)
--- a/tests/simple/task_func.v
+++ b/tests/simple/task_func.v
@@ -1,5 +1,5 @@
 
-module test01(clk, a, b, c, x, y, z, w);
+module task_func_test01(clk, a, b, c, x, y, z, w);
 
 input clk;
 input [7:0] a, b, c;

diff --git a/tests/simple/undef_eqx_nex.v b/tests/simple/undef_eqx_nex.v
index 63912a2fa62b31e14598ae405f1fdf06fed15ac7..b0178677bc0fa37664ec2f57b4bcf8181a6e07b0 100644 (file)
--- a/tests/simple/undef_eqx_nex.v
+++ b/tests/simple/undef_eqx_nex.v
@@ -1,4 +1,4 @@
-module test(y);
+module undef_eqx_nex(y);
 output [7:0] y;
 assign y[0] = 0/0;
 assign y[1] = 0/1;

diff --git a/tests/simple/usb_phy_tests.v b/tests/simple/usb_phy_tests.v
new file mode 100644 (file)
index 0000000..bc45e71
--- /dev/null
+++ b/tests/simple/usb_phy_tests.v
@@ -0,0 +1,36 @@
+
+// from usb_rx_phy
+module usb_phy_test01(clk, rst, rx_en, fs_ce);
+
+input          clk, rst;
+input          rx_en;
+output reg     fs_ce;
+reg    [1:0]   dpll_next_state;
+reg    [1:0]   dpll_state;
+
+always @(posedge clk)
+       dpll_state <= rst ? 0 : dpll_next_state;
+
+always @*
+   begin
+       fs_ce = 1'b0;
+       case(dpll_state)
+          2'h0:
+               if(rx_en)       dpll_next_state = 2'h0;
+               else            dpll_next_state = 2'h1;
+          2'h1:begin
+               fs_ce = 1'b1;
+               if(rx_en)       dpll_next_state = 2'h3;
+               else            dpll_next_state = 2'h2;
+               end
+          2'h2:
+               if(rx_en)       dpll_next_state = 2'h0;
+               else            dpll_next_state = 2'h3;
+          2'h3:
+               if(rx_en)       dpll_next_state = 2'h0;
+               else            dpll_next_state = 2'h0;
+       endcase
+   end
+
+endmodule
+

diff --git a/tests/simple/usb_phy_tetsts.v b/tests/simple/usb_phy_tetsts.v
deleted file mode 100644 (file)
index 2375183..0000000
--- a/tests/simple/usb_phy_tetsts.v
+++ /dev/null
@@ -1,36 +0,0 @@
-
-// from usb_rx_phy
-module test01(clk, rst, rx_en, fs_ce);
-
-input          clk, rst;
-input          rx_en;
-output reg     fs_ce;
-reg    [1:0]   dpll_next_state;
-reg    [1:0]   dpll_state;
-
-always @(posedge clk)
-       dpll_state <= rst ? 0 : dpll_next_state;
-
-always @*
-   begin
-       fs_ce = 1'b0;
-       case(dpll_state)
-          2'h0:
-               if(rx_en)       dpll_next_state = 2'h0;
-               else            dpll_next_state = 2'h1;
-          2'h1:begin
-               fs_ce = 1'b1;
-               if(rx_en)       dpll_next_state = 2'h3;
-               else            dpll_next_state = 2'h2;
-               end
-          2'h2:
-               if(rx_en)       dpll_next_state = 2'h0;
-               else            dpll_next_state = 2'h3;
-          2'h3:
-               if(rx_en)       dpll_next_state = 2'h0;
-               else            dpll_next_state = 2'h0;
-       endcase
-   end
-
-endmodule
-