sv: Add lexing and parsing of .* (wildcard port conns)
authorDavid Shah <dave@ds0.me>
Fri, 22 Nov 2019 08:24:01 +0000 (08:24 +0000)
committerDavid Shah <dave@ds0.me>
Sun, 2 Feb 2020 16:12:33 +0000 (16:12 +0000)
Signed-off-by: David Shah <dave@ds0.me>
frontends/verilog/verilog_lexer.l
frontends/verilog/verilog_parser.y

index ca23df3e8c27c68224b2be6f15885bbf1645394d..39520bd5118aa4d484493235e6a7af9ac81c9b83 100644 (file)
@@ -431,6 +431,8 @@ import[ \t\r\n]+\"(DPI|DPI-C)\"[ \t\r\n]+function[ \t\r\n]+ {
 "+:" { return TOK_POS_INDEXED; }
 "-:" { return TOK_NEG_INDEXED; }
 
+".*" { return TOK_AUTOCONNECT_ALL; }
+
 [-+]?[=*]> {
        if (!specify_mode) REJECT;
        frontend_verilog_yylval.string = new std::string(yytext);
index a30935e0a3d2a0312edb9478bf61c39eb689b79a..cb413e13af100ea0880d7c41ef3513a9c426f2c5 100644 (file)
@@ -138,7 +138,7 @@ struct specify_rise_fall {
 %token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
 %token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
 %token TOK_PACKAGE TOK_ENDPACKAGE TOK_PACKAGESEP
-%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR
+%token TOK_INTERFACE TOK_ENDINTERFACE TOK_MODPORT TOK_VAR TOK_AUTOCONNECT_ALL
 %token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_WAND TOK_WOR TOK_REG TOK_LOGIC
 %token TOK_INTEGER TOK_SIGNED TOK_ASSIGN TOK_ALWAYS TOK_INITIAL
 %token TOK_ALWAYS_FF TOK_ALWAYS_COMB TOK_ALWAYS_LATCH
@@ -1580,6 +1580,9 @@ cell_port:
                node->children.back()->str = *$3;
                delete $3;
                free_attr($1);
+       } |
+       attr TOK_AUTOCONNECT_ALL {
+               astbuf2->attributes[ID(autoconnect)] = AstNode::mkconst_int(1, false);
        };
 
 always_comb_or_latch: