soc/interconnect/axi: generate wishbone.sel for reads.

diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py
index 2c444d60bfedb28e61f89166ae53025f208bf03a..e95e01e03433a56180364783022ddb588fb51923 100644 (file)
--- a/litex/soc/interconnect/axi.py
+++ b/litex/soc/interconnect/axi.py
@@ -365,6 +365,7 @@ class AXILite2Wishbone(Module):
             wishbone.stb.eq(1),
             wishbone.cyc.eq(1),
             wishbone.adr.eq(_r_addr[wishbone_adr_shift:]),
+            wishbone.sel.eq(2**len(wishbone.sel) - 1),
             If(wishbone.ack,
                 axi_lite.ar.ready.eq(1),
                 NextValue(_data, wishbone.dat_r),