now O3CPU is totally independent of the ISA... all alpha specific stuff is the cpu...

src/cpu/o3/alpha/cpu.cc:
src/cpu/o3/alpha/cpu_impl.hh:
src/cpu/o3/alpha/impl.hh:
    filenames
src/cpu/o3/alpha/thread_context.hh:
    public
src/cpu/o3/base_dyn_inst.cc:
src/cpu/o3/bpred_unit.cc:
src/cpu/o3/commit.cc:
src/cpu/o3/cpu.cc:
src/cpu/o3/decode.cc:
src/cpu/o3/fetch.cc:
src/cpu/o3/iew.cc:
src/cpu/o3/inst_queue.cc:
src/cpu/o3/lsq.cc:
src/cpu/o3/lsq_unit.cc:
src/cpu/o3/mem_dep_unit.cc:
src/cpu/o3/rename.cc:
src/cpu/o3/rob.cc:
    use O3CPUImpl ... not Alpha
src/cpu/o3/checker_builder.cc:
    filename

--HG--
extra : convert_revision : 6eb739909699ade1e2a9d63637b182413ceebc69

diff --git a/src/cpu/o3/alpha/cpu.cc b/src/cpu/o3/alpha/cpu.cc
index 87a4d03a774fd89c75abfc18193488905bb7e588..ed10b2fd119ab7feef7d74aa57080607f7a793ae 100644 (file)
--- a/src/cpu/o3/alpha/cpu.cc
+++ b/src/cpu/o3/alpha/cpu.cc
@@ -28,7 +28,7 @@
  * Authors: Kevin Lim
  */
 
-#include "cpu/o3/alphaimpl.hh"
+#include "cpu/o3/alpha/impl.hh"
 #include "cpu/o3/alpha/cpu_impl.hh"
 #include "cpu/o3/alpha/dyn_inst.hh"
 

diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh
index 2da683398b64992efe06921a0f64d249c50aed8c..0473e60c2344e0ffa3f8890f7e3ee6149c934d7b 100644 (file)
--- a/src/cpu/o3/alpha/cpu_impl.hh
+++ b/src/cpu/o3/alpha/cpu_impl.hh
@@ -40,7 +40,7 @@
 
 #include "cpu/o3/alpha/cpu.hh"
 #include "cpu/o3/alpha/params.hh"
-#include "cpu/o3/alpha/tc.hh"
+#include "cpu/o3/alpha/thread_context.hh"
 #include "cpu/o3/comm.hh"
 #include "cpu/o3/thread_state.hh"
 
@@ -120,7 +120,7 @@ AlphaO3CPU<Impl>::AlphaO3CPU(Params *params)
         // CheckerThreadContext.
 #if USE_CHECKER
         if (params->checker) {
-            tc = new CheckerThreadContext<AlphaTC<Impl>>(
+            tc = new CheckerThreadContext<AlphaTC<Impl> >(
                 alpha_tc, this->checker);
         }
 #endif

diff --git a/src/cpu/o3/alpha/impl.hh b/src/cpu/o3/alpha/impl.hh
index cdcdff34a8842761836eef404ba07623e6ea787f..8cd8692c600a0b0f67c799f5c4896afc28a212d4 100644 (file)
--- a/src/cpu/o3/alpha/impl.hh
+++ b/src/cpu/o3/alpha/impl.hh
@@ -81,8 +81,14 @@ struct AlphaSimpleImpl
 
     enum {
       MaxWidth = 8,
-      MaxThreads = 2
+      MaxThreads = 4
     };
 };
 
+/** The O3Impl to be used. */
+typedef AlphaSimpleImpl O3CPUImpl;
+
+/** The O3Impl to be used. */
+typedef DynInst O3DynInst;
+
 #endif // __CPU_O3_ALPHA_IMPL_HH__

diff --git a/src/cpu/o3/alpha/thread_context.hh b/src/cpu/o3/alpha/thread_context.hh
index 890bff3ffb6b8341675f050f9679f53965da2825..57190d65e3901fa7701f696965731c37e078b88f 100644 (file)
--- a/src/cpu/o3/alpha/thread_context.hh
+++ b/src/cpu/o3/alpha/thread_context.hh
@@ -34,6 +34,7 @@
 template <class Impl>
 class AlphaTC : public O3ThreadContext<Impl>
 {
+  public:
 #if FULL_SYSTEM
     /** Returns a pointer to the ITB. */
     virtual AlphaITB *getITBPtr() { return cpu->itb; }

diff --git a/src/cpu/o3/base_dyn_inst.cc b/src/cpu/o3/base_dyn_inst.cc
index a0089fb8b00e92b0c1c42cba82df65e1d8d72ca1..0979c5c8f19353b3bd02ed1e6b2abc53e961f1d0 100644 (file)
--- a/src/cpu/o3/base_dyn_inst.cc
+++ b/src/cpu/o3/base_dyn_inst.cc
@@ -32,8 +32,8 @@
 #include "cpu/o3/isa_specific.hh"
 
 // Explicit instantiation
-template class BaseDynInst<AlphaSimpleImpl>;
+template class BaseDynInst<O3CPUImpl>;
 
 template <>
 int
-BaseDynInst<AlphaSimpleImpl>::instcount = 0;
+BaseDynInst<O3CPUImpl>::instcount = 0;

diff --git a/src/cpu/o3/bpred_unit.cc b/src/cpu/o3/bpred_unit.cc
index 4087fa07bd3ec98682020fa8bf338c001690656c..08fd4e8eafc567362d5e1954e9ee169dc9b0f6b5 100644 (file)
--- a/src/cpu/o3/bpred_unit.cc
+++ b/src/cpu/o3/bpred_unit.cc
@@ -31,4 +31,4 @@
 #include "cpu/o3/bpred_unit_impl.hh"
 #include "cpu/o3/isa_specific.hh"
 
-template class BPredUnit<AlphaSimpleImpl>;
+template class BPredUnit<O3CPUImpl>;

diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker_builder.cc
index 58c40d00c9d37bca76eb050ef91327be0cf948bd..782d963b0c95b599bacc5e0969ce5a9e04e5f067 100644 (file)
--- a/src/cpu/o3/checker_builder.cc
+++ b/src/cpu/o3/checker_builder.cc
@@ -32,8 +32,8 @@
 
 #include "cpu/checker/cpu_impl.hh"
 #include "cpu/inst_seq.hh"
-#include "cpu/o3/alpha_dyn_inst.hh"
-#include "cpu/o3/alpha_impl.hh"
+#include "cpu/o3/alpha/dyn_inst.hh"
+#include "cpu/o3/alpha/impl.hh"
 #include "sim/builder.hh"
 #include "sim/process.hh"
 #include "sim/sim_object.hh"

diff --git a/src/cpu/o3/commit.cc b/src/cpu/o3/commit.cc
index 9bbb526dc92562d5f2a5bd385c877e8601822440..637d59f526ed79338637b4cd6ccea8356e77da23 100644 (file)
--- a/src/cpu/o3/commit.cc
+++ b/src/cpu/o3/commit.cc
@@ -31,4 +31,4 @@
 #include "cpu/o3/isa_specific.hh"
 #include "cpu/o3/commit_impl.hh"
 
-template class DefaultCommit<AlphaSimpleImpl>;
+template class DefaultCommit<O3CPUImpl>;

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index c2282d617782628317c0478d596c1d44ec55576f..87fee8361422ad117379ec560212c4255d88dbd0 100644 (file)
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1211,4 +1211,4 @@ FullO3CPU<Impl>::updateThreadPriority()
 }
 
 // Forward declaration of FullO3CPU.
-template class FullO3CPU<AlphaSimpleImpl>;
+template class FullO3CPU<O3CPUImpl>;

diff --git a/src/cpu/o3/decode.cc b/src/cpu/o3/decode.cc
index 52d55983a818aaf4b58aa6afa4b0c03ceae12443..896e38331c24d7412c121d1438b5462f1ad8396c 100644 (file)
--- a/src/cpu/o3/decode.cc
+++ b/src/cpu/o3/decode.cc
@@ -31,4 +31,4 @@
 #include "cpu/o3/isa_specific.hh"
 #include "cpu/o3/decode_impl.hh"
 
-template class DefaultDecode<AlphaSimpleImpl>;
+template class DefaultDecode<O3CPUImpl>;

diff --git a/src/cpu/o3/fetch.cc b/src/cpu/o3/fetch.cc
index 39b9879a40e077cf43f257b9df1d138df442c0a9..d809b07e4736f6a28865f318ad37f31932e0bae0 100644 (file)
--- a/src/cpu/o3/fetch.cc
+++ b/src/cpu/o3/fetch.cc
@@ -31,4 +31,4 @@
 #include "cpu/o3/isa_specific.hh"
 #include "cpu/o3/fetch_impl.hh"
 
-template class DefaultFetch<AlphaSimpleImpl>;
+template class DefaultFetch<O3CPUImpl>;

diff --git a/src/cpu/o3/iew.cc b/src/cpu/o3/iew.cc
index bf8eb61ac7418a1261d34874a13a1e3b889702de..f99be7fe0a8ed3ab51ba193fe91c297750d6a7c5 100644 (file)
--- a/src/cpu/o3/iew.cc
+++ b/src/cpu/o3/iew.cc
@@ -32,4 +32,4 @@
 #include "cpu/o3/iew_impl.hh"
 #include "cpu/o3/inst_queue.hh"
 
-template class DefaultIEW<AlphaSimpleImpl>;
+template class DefaultIEW<O3CPUImpl>;

diff --git a/src/cpu/o3/inst_queue.cc b/src/cpu/o3/inst_queue.cc
index 88f3f33a05296e96c775984df49947c2e5e7d463..a539066f93749bd59ac133a24dad1fe8a31d3f3d 100644 (file)
--- a/src/cpu/o3/inst_queue.cc
+++ b/src/cpu/o3/inst_queue.cc
@@ -32,4 +32,4 @@
 #include "cpu/o3/inst_queue_impl.hh"
 
 // Force instantiation of InstructionQueue.
-template class InstructionQueue<AlphaSimpleImpl>;
+template class InstructionQueue<O3CPUImpl>;

diff --git a/src/cpu/o3/lsq.cc b/src/cpu/o3/lsq.cc
index 872576c32a9cca89b3d33a5e173488af17f03275..5279472815ad776ffd0b20af367db8fce83563dc 100644 (file)
--- a/src/cpu/o3/lsq.cc
+++ b/src/cpu/o3/lsq.cc
@@ -32,5 +32,5 @@
 #include "cpu/o3/lsq_impl.hh"
 
 // Force the instantiation of LDSTQ for all the implementations we care about.
-template class LSQ<AlphaSimpleImpl>;
+template class LSQ<O3CPUImpl>;
 

diff --git a/src/cpu/o3/lsq_unit.cc b/src/cpu/o3/lsq_unit.cc
index 9b244ac7192a6a6f33e7617db7f90137b289b8ec..3ca3fa66746680943e325407aeab06a3c96336ed 100644 (file)
--- a/src/cpu/o3/lsq_unit.cc
+++ b/src/cpu/o3/lsq_unit.cc
@@ -33,5 +33,5 @@
 #include "cpu/o3/lsq_unit_impl.hh"
 
 // Force the instantiation of LDSTQ for all the implementations we care about.
-template class LSQUnit<AlphaSimpleImpl>;
+template class LSQUnit<O3CPUImpl>;
 

diff --git a/src/cpu/o3/mem_dep_unit.cc b/src/cpu/o3/mem_dep_unit.cc
index 3edac95ac16ffbb90c7b34d144e6deb440e43e3f..6a14dcbff4960abc51551a182c8516b3c8dc93d3 100644 (file)
--- a/src/cpu/o3/mem_dep_unit.cc
+++ b/src/cpu/o3/mem_dep_unit.cc
@@ -33,17 +33,17 @@
 #include "cpu/o3/mem_dep_unit_impl.hh"
 
 // Force instantation of memory dependency unit using store sets and
-// AlphaSimpleImpl.
-template class MemDepUnit<StoreSet, AlphaSimpleImpl>;
+// O3CPUImpl.
+template class MemDepUnit<StoreSet, O3CPUImpl>;
 
 #ifdef DEBUG
 template <>
 int
-MemDepUnit<StoreSet, AlphaSimpleImpl>::MemDepEntry::memdep_count = 0;
+MemDepUnit<StoreSet, O3CPUImpl>::MemDepEntry::memdep_count = 0;
 template <>
 int
-MemDepUnit<StoreSet, AlphaSimpleImpl>::MemDepEntry::memdep_insert = 0;
+MemDepUnit<StoreSet, O3CPUImpl>::MemDepEntry::memdep_insert = 0;
 template <>
 int
-MemDepUnit<StoreSet, AlphaSimpleImpl>::MemDepEntry::memdep_erase = 0;
+MemDepUnit<StoreSet, O3CPUImpl>::MemDepEntry::memdep_erase = 0;
 #endif

diff --git a/src/cpu/o3/rename.cc b/src/cpu/o3/rename.cc
index f972190b77008898828a4b484f4af86bbc17bbfb..443ada0cb452797932766f69cb588ef23084a2f6 100644 (file)
--- a/src/cpu/o3/rename.cc
+++ b/src/cpu/o3/rename.cc
@@ -31,4 +31,4 @@
 #include "cpu/o3/isa_specific.hh"
 #include "cpu/o3/rename_impl.hh"
 
-template class DefaultRename<AlphaSimpleImpl>;
+template class DefaultRename<O3CPUImpl>;

diff --git a/src/cpu/o3/rob.cc b/src/cpu/o3/rob.cc
index ccef6b1554a7f0c6fb8ede7d3134ed72b7724870..9976049cdb2eaa94179411b41ebfe6324394e1a2 100644 (file)
--- a/src/cpu/o3/rob.cc
+++ b/src/cpu/o3/rob.cc
@@ -33,4 +33,4 @@
 #include "cpu/o3/rob_impl.hh"
 
 // Force instantiation of InstructionQueue.
-template class ROB<AlphaSimpleImpl>;
+template class ROB<O3CPUImpl>;