[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

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+Date: Thu, 26 Mar 2020 11:02:24 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: changed
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Specification
+X-Bugzilla-Version: unspecified
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
+X-Bugzilla-Status: CONFIRMED
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+Message-ID: <bug-186-13-HmItjmDZGW@http.bugs.libre-riscv.org/>
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+References: <bug-186-13@http.bugs.libre-riscv.org/>
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+Auto-Submitted: auto-generated
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+Subject: [libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and
+ RISC-V
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