gallium: add support for formatted image loads
authorRhys Perry <pendingchaos02@gmail.com>
Wed, 16 Jan 2019 23:18:25 +0000 (23:18 +0000)
committerMarek Olšák <marek.olsak@amd.com>
Mon, 15 Apr 2019 20:18:07 +0000 (16:18 -0400)
v3: rebase
v3: make use of u_pipe_screen_get_param_defaults

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
src/gallium/auxiliary/util/u_screen.c
src/gallium/docs/source/screen.rst
src/gallium/drivers/nouveau/nv30/nv30_screen.c
src/gallium/drivers/nouveau/nv50/nv50_screen.c
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
src/gallium/drivers/swr/swr_screen.cpp
src/gallium/drivers/vc4/vc4_screen.c
src/gallium/include/pipe/p_defines.h

index a449db856f66fdb38ecf8f593c12e09588f7fcc0..f864a7a320bff3fa3ba541a78f6c3dac355ae8f5 100644 (file)
@@ -323,6 +323,7 @@ u_pipe_screen_get_param_defaults(struct pipe_screen *pscreen,
    case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
    case PIPE_CAP_TGSI_ATOMFADD:
    case PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS:
+   case PIPE_CAP_IMAGE_LOAD_FORMATTED:
       return 0;
 
    case PIPE_CAP_MAX_GS_INVOCATIONS:
index f29c05756a82d992a7eed50e9f6c8db6ce6138ea..21ca07f2437d6ad1dc9bb77e8028f747d9f1246a 100644 (file)
@@ -508,6 +508,7 @@ The integer capabilities:
   arrays should be skipped and enforce keeping the declared array sizes instead.
   A driver might rely on the input mapping that was defined with the original
   GLSL code.
+* ``PIPE_CAP_IMAGE_LOAD_FORMATTED``: True if a format for image loads does not need to be specified in the shader IR
 
 .. _pipe_capf:
 
index 53551ebc037d01b4c06b8e9406f6e4be41078806..b5dc033bd2d43a34fd8e7ae3651a7cd0a3b11bcf 100644 (file)
@@ -246,6 +246,7 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
+   case PIPE_CAP_IMAGE_LOAD_FORMATTED:
       return 0;
 
    case PIPE_CAP_MAX_GS_INVOCATIONS:
index b9bfce21364d6814ab1551358b1fde4d439b54b3..423b6af3b64bbfaec1239e181cd9352f84de6379 100644 (file)
@@ -318,6 +318,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
    case PIPE_CAP_NIR_COMPACT_ARRAYS:
    case PIPE_CAP_COMPUTE:
+   case PIPE_CAP_IMAGE_LOAD_FORMATTED:
       return 0;
 
    case PIPE_CAP_VENDOR_ID:
index 2fb2097d731cdf35264d5eeb806b8ba4d89e45da..79224ac99a75aa958c325d824a2d347d1be9e051 100644 (file)
@@ -352,6 +352,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
    case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
    case PIPE_CAP_NIR_COMPACT_ARRAYS:
+   case PIPE_CAP_IMAGE_LOAD_FORMATTED:
       return 0;
 
    case PIPE_CAP_VENDOR_ID:
index ea63368f75002b7e13de94347f420cf2ea633923..3a2a6133127701e2d8f2b7147f80a7c996e0da91 100644 (file)
@@ -365,6 +365,7 @@ swr_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
    case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
    case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
+   case PIPE_CAP_IMAGE_LOAD_FORMATTED:
       return 0;
    case PIPE_CAP_MAX_GS_INVOCATIONS:
       return 32;
index 5fc8c35f8a952dcefcd418476601e9a9f6a64659..ca9471fe5cb63a68f1c55722644a62cdfd943fad 100644 (file)
@@ -296,6 +296,7 @@ vc4_screen_get_shader_param(struct pipe_screen *pscreen,
         case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
         case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
+        case PIPE_SHADER_CAP_IMAGE_LOAD_FORMATTED:
                 return 0;
         case PIPE_SHADER_CAP_SCALAR_ISA:
                 return 1;
index feb30693a96d33c0fa0df758df25b24576484665..b927991e43308629f4867e3466d8cd6751b60b14 100644 (file)
@@ -867,6 +867,7 @@ enum pipe_cap
    PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK,
    PIPE_CAP_COMPUTE_SHADER_DERIVATIVES,
    PIPE_CAP_TGSI_SKIP_SHRINK_IO_ARRAYS,
+   PIPE_CAP_IMAGE_LOAD_FORMATTED,
 };
 
 /**