test/test_targets: update

diff --git a/test/test_targets.py b/test/test_targets.py
index 615e54482ac98ed626c5135a1e9f88c351920505..f6fc56b6ba3c6c4e73d724a346bfe06dff2c15e3 100644 (file)
--- a/test/test_targets.py
+++ b/test/test_targets.py
@@ -57,6 +57,16 @@ class TestTargets(unittest.TestCase):
 
     # lattice boards
 
+    def test_versa_ecp5(self):
+        from litex.boards.targets.versa_ecp5 import BaseSoC
+        errors = build_test([BaseSoC()])
+        self.assertEqual(errors, 0)
+
+    def test_versa_ulx3s(self):
+        from litex.boards.targets.ulx3s import BaseSoC
+        errors = build_test([BaseSoC()])
+        self.assertEqual(errors, 0)
+
     # build simple design for all platforms
     def test_simple(self):
         platforms = [
@@ -76,8 +86,8 @@ class TestTargets(unittest.TestCase):
             "papilio_pro",
             "tinyfpga_b",
             "tinyfpga_bx",
-            "versa",
-            "versaecp55g"
+            "versa_ecp3",
+            "versa_ecp5"
         ]
         for p in platforms:
             os.system("litex_simple litex.boards.platforms." + p +