add sign-extension bitwidth macros

diff --git a/riscv/sv_reg.h b/riscv/sv_reg.h
index 6375a1adef78b64c6294631895174a5b5710428c..f704f351034b8cb2171739a621d3f57d6deab009 100644 (file)
--- a/riscv/sv_reg.h
+++ b/riscv/sv_reg.h
@@ -1,6 +1,9 @@
 #ifndef SV_REG_H
 #define SV_REG_H
 
+#define sext_bwid(x,wid) (((sreg_t)(x) << (64-wid)) >> (64-wid))
+#define zext_bwid(x,wid) (((reg_t)(x) << (64-wid)) >> (64-wid))
+
 class sv_sreg_t;
 
 class sv_regbase_t {
@@ -29,7 +32,7 @@ public:
                        0x1, // 8-default/2: default/2
                        0x2, // 8-default*2: default*2
                        0x3  // 8-8: 8
-    };
+                    };
     return tb[elwidth|(r.elwidth<<2)];
     }
 };