gas/testsuite/

2008-08-27  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/intel.s: Add tests for fidivr.

	* gas/i386/intel.d: Updated.

opcodes/

2008-08-27  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Correct fidivr operand size.

	* i386-tbl.h: Regenerated.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 1b0b40f173110462e2cb41b1cf830283a0fcfbfb..5dc3e5035581c7171ef2fa02b3a86b670fa3377d 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2008-08-27  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * gas/i386/intel.s: Add tests for fidivr.
+
+       * gas/i386/intel.d: Updated.
+
 2008-08-26  Jie Zhang  <jie.zhang@analog.com>
 
        * gas/bfin/arith_mode.d: New test.

diff --git a/gas/testsuite/gas/i386/intel.d b/gas/testsuite/gas/i386/intel.d
index 5a764b4fe06673df16b51fa2e18d7b923cc2dc0c..ac9c336f1d71e7a83c1569b48d5119fa25702d38 100644 (file)
--- a/gas/testsuite/gas/i386/intel.d
+++ b/gas/testsuite/gas/i386/intel.d
@@ -688,4 +688,6 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    de e3                   fsubp  %st,%st\(3\)
 [      ]*[a-f0-9]+:    de e3                   fsubp  %st,%st\(3\)
 [      ]*[a-f0-9]+:    de e3                   fsubp  %st,%st\(3\)
+[      ]*[a-f0-9]+:    de 3b                   fidivr \(%ebx\)
+[      ]*[a-f0-9]+:    da 3b                   fidivrl \(%ebx\)
 #pass

diff --git a/gas/testsuite/gas/i386/intel.s b/gas/testsuite/gas/i386/intel.s
index 6b42343011c4e9118f9ab0e1d2931bf03c81469b..288ad0e179a4feb89f35c7f5aa07f33356b5b981 100644 (file)
--- a/gas/testsuite/gas/i386/intel.s
+++ b/gas/testsuite/gas/i386/intel.s
@@ -686,3 +686,6 @@ fsubrp
 fsubrp st(3)
 fsubrp st(3),st
 fsubrp st,st(3)
+
+fidivr  word ptr [ebx]
+fidivr  dword ptr [ebx]

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 2e0d49e89bdcc5771dd34210d0b5d18e18ec1348..953d6546c83c288c1f204e0cd5ffd6474f283825 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2008-08-27  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-opc.tbl: Correct fidivr operand size.
+
+       * i386-tbl.h: Regenerated.
+
 2008-08-24  Alan Modra  <amodra@bigpond.net.au>
 
        * configure.in: Update a number of obsolete autoconf macros.

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index b02604608655f90ed9424533d8ab336e1a86d446..1c9d3126bab70bc467e3f7f01d44db896e4923d6 100644 (file)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -698,7 +698,7 @@ fdivr, 0, 0xdef9, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|U
 fdivr, 0, 0xdef1, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Ugh|ATTMnemonic, { 0 }
 fdivr, 2, 0xd8f8, None, 2, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc }
 fdivr, 1, 0xd8, 0x7, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
-fidivr, 1, 0xde, 0x7, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
+fidivr, 1, 0xde, 0x7, 1, 0, Modrm|FloatMF|No_bSuf|No_wSuf|No_qSuf|No_ldSuf, { Word|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
 
 fdivrp, 2, 0xdef8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatAcc, FloatReg }
 fdivrp, 1, 0xdef8, None, 2, 0, ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTMnemonic|ATTSyntax, { FloatReg }

diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index a176145c929e9db1097d541db9dd6c88d36484ef..e78f62e1f4d40fe23fcae24ca00f89c0e20bf059 100644 (file)
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -5120,7 +5120,7 @@ const template i386_optab[] =
       1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 
-         1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 
+         1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 
          0, 0, 1, 0, 0, 0 } } } },
   { "fdivrp", 2, 0xdef8, None, 2,
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,