Include Wishbone to ASMI bridge

diff --git a/top.py b/top.py
index 8d2bb1f96291080099d781cba3b9da7bbf0446b8..50c8f0bdb00f2fccf123c06b7a665a725f64743c 100644 (file)
--- a/top.py
+++ b/top.py
@@ -1,21 +1,30 @@
 from migen.fhdl.structure import *
-from migen.fhdl import tools, verilog, autofragment
-from migen.bus import wishbone, csr, wishbone2csr
+from migen.fhdl import verilog, autofragment
+from migen.bus import wishbone, asmibus, wishbone2asmi, csr, wishbone2csr
 
 from milkymist import m1reset, clkfx, lm32, norflash, uart, sram
 import constraints
 
+MHz = 1000000
+clk_freq = 80*MHz
+sram_size = 4096 # in bytes
+l2_size = 8192 # in bytes
+
 def get():
-       MHz = 1000000
-       clk_freq = 80*MHz
-       sram_size = 4096 # in bytes
-       
-       clkfx_sys = clkfx.ClkFX(50*MHz, clk_freq)
-       reset0 = m1reset.M1Reset()
+       #
+       # ASMI
+       #
+       asmihub0 = asmibus.Hub(24, 64, 8) # TODO: get hub from memory controller
+       asmiport_wb = asmihub0.get_port()
+       asmihub0.finalize()
        
+       #
+       # WISHBONE
+       #
        cpu0 = lm32.LM32()
        norflash0 = norflash.NorFlash(25, 12)
        sram0 = sram.SRAM(sram_size//4)
+       wishbone2asmi0 = wishbone2asmi.WB2ASMI(l2_size//4, asmiport_wb)
        wishbone2csr0 = wishbone2csr.WB2CSR()
        
        # norflash     0x00000000 (shadow @0x80000000)
@@ -23,7 +32,7 @@ def get():
        # USB          0x20000000 (shadow @0xa0000000)
        # Ethernet     0x30000000 (shadow @0xb0000000)
        # SDRAM        0x40000000 (shadow @0xc0000000)
-       # CSR bridge   0x60000000 (shadow @0xe0000000)  
+       # CSR bridge   0x60000000 (shadow @0xe0000000)
        wishbonecon0 = wishbone.InterconnectShared(
                [
                        cpu0.ibus,
@@ -31,18 +40,31 @@ def get():
                ], [
                        (binc("000"), norflash0.bus),
                        (binc("001"), sram0.bus),
+                       (binc("10"), wishbone2asmi0.wishbone),
                        (binc("11"), wishbone2csr0.wishbone)
                ],
                register=True,
                offset=1)
        
+       #
+       # CSR
+       #
        uart0 = uart.UART(0, clk_freq, baud=115200)
        csrcon0 = csr.Interconnect(wishbone2csr0.csr, [uart0.bank.interface])
        
+       #
+       # Interrupts
+       #
        interrupts = Fragment([
                cpu0.interrupt[0].eq(uart0.events.irq)
        ])
        
+       #
+       # Housekeeping
+       #
+       clkfx_sys = clkfx.ClkFX(50*MHz, clk_freq)
+       reset0 = m1reset.M1Reset()
+       
        frag = autofragment.from_local() + interrupts
        src_verilog, vns = verilog.convert(frag,
                {clkfx_sys.clkin, reset0.trigger_reset},