log_header(design, "Executing CHECK pass (checking for obvious problems).\n");
- pool<IdString> fftypes;
- fftypes.insert(ID($sr));
- fftypes.insert(ID($ff));
- fftypes.insert(ID($dff));
- fftypes.insert(ID($dffe));
- fftypes.insert(ID($dffsr));
- fftypes.insert(ID($adff));
- fftypes.insert(ID($dlatch));
- fftypes.insert(ID($dlatchsr));
- fftypes.insert(ID($_DFFE_NN_));
- fftypes.insert(ID($_DFFE_NP_));
- fftypes.insert(ID($_DFFE_PN_));
- fftypes.insert(ID($_DFFE_PP_));
- fftypes.insert(ID($_DFFSR_NNN_));
- fftypes.insert(ID($_DFFSR_NNP_));
- fftypes.insert(ID($_DFFSR_NPN_));
- fftypes.insert(ID($_DFFSR_NPP_));
- fftypes.insert(ID($_DFFSR_PNN_));
- fftypes.insert(ID($_DFFSR_PNP_));
- fftypes.insert(ID($_DFFSR_PPN_));
- fftypes.insert(ID($_DFFSR_PPP_));
- fftypes.insert(ID($_DFF_NN0_));
- fftypes.insert(ID($_DFF_NN1_));
- fftypes.insert(ID($_DFF_NP0_));
- fftypes.insert(ID($_DFF_NP1_));
- fftypes.insert(ID($_DFF_N_));
- fftypes.insert(ID($_DFF_PN0_));
- fftypes.insert(ID($_DFF_PN1_));
- fftypes.insert(ID($_DFF_PP0_));
- fftypes.insert(ID($_DFF_PP1_));
- fftypes.insert(ID($_DFF_P_));
- fftypes.insert(ID($_DLATCHSR_NNN_));
- fftypes.insert(ID($_DLATCHSR_NNP_));
- fftypes.insert(ID($_DLATCHSR_NPN_));
- fftypes.insert(ID($_DLATCHSR_NPP_));
- fftypes.insert(ID($_DLATCHSR_PNN_));
- fftypes.insert(ID($_DLATCHSR_PNP_));
- fftypes.insert(ID($_DLATCHSR_PPN_));
- fftypes.insert(ID($_DLATCHSR_PPP_));
- fftypes.insert(ID($_DLATCH_N_));
- fftypes.insert(ID($_DLATCH_P_));
- fftypes.insert(ID($_FF_));
-
for (auto module : design->selected_whole_modules_warn())
{
if (module->has_processes_warn())
{
for (auto cell : module->cells())
{
- if (fftypes.count(cell->type) == 0)
+ if (RTLIL::builtin_ff_cell_types().count(cell->type) == 0)
continue;
for (auto bit : sigmap(cell->getPort(ID::Q)))
pool<SigBit> ffbits;
pool<Wire*> initwires;
- pool<IdString> fftypes;
- fftypes.insert(ID($dff));
- fftypes.insert(ID($dffe));
- fftypes.insert(ID($dffsr));
- fftypes.insert(ID($adff));
-
- std::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'};
-
- for (auto c1 : list_np)
- fftypes.insert(stringf("$_DFF_%c_", c1));
-
- for (auto c1 : list_np)
- for (auto c2 : list_np)
- fftypes.insert(stringf("$_DFFE_%c%c_", c1, c2));
-
- for (auto c1 : list_np)
- for (auto c2 : list_np)
- for (auto c3 : list_01)
- fftypes.insert(stringf("$_DFF_%c%c%c_", c1, c2, c3));
-
- for (auto c1 : list_np)
- for (auto c2 : list_np)
- for (auto c3 : list_np)
- fftypes.insert(stringf("$_DFFSR_%c%c%c_", c1, c2, c3));
-
for (auto cell : module->cells())
{
- if (!fftypes.count(cell->type))
+ if (!RTLIL::builtin_ff_cell_types().count(cell->type))
continue;
for (auto bit : sigmap(cell->getPort(ID::Q)))
for (auto &it : *conn) {
RTLIL::SigSpec sig;
if (cell->output(it.first)) {
- if (it.first == ID::Q && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") ||
- cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") ||
- cell->type.in(ID($adff), ID($sr), ID($ff), ID($_FF_)))) {
+ if (it.first == ID::Q && RTLIL::builtin_ff_cell_types().count(cell->type)) {
// For the 'Q' output of state elements,
// use its (* init *) attribute value
for (const auto &b : dff_init_map(it.second))