Revert "radv/gfx9: fix block compression texture views."
authorBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fri, 29 Dec 2017 09:59:27 +0000 (10:59 +0100)
committerBas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fri, 29 Dec 2017 10:21:43 +0000 (11:21 +0100)
This reverts commit 59515780433837ad3975f8ed20b93cf2fe6870e5.

The mentioned commit causes a hang in DoW3 on Vega.

Fixes: 59515780433 "radv/gfx9: fix block compression texture views."
Acked-by: Dave Airlie <airlied@redhat.com>
src/amd/vulkan/radv_image.c

index a579a1ef5dc9161bbc6c5155804e978b63f0d98d..a1b660a74cd2424d1dcdecd591e588c2d3093b2b 100644 (file)
@@ -1067,41 +1067,6 @@ radv_image_view_init(struct radv_image_view *iview,
                                                   vk_format_get_blockwidth(image->vk_format));
                iview->extent.height = round_up_u32(iview->extent.height * vk_format_get_blockheight(iview->vk_format),
                                                    vk_format_get_blockheight(image->vk_format));
-               /* Comment ported from amdvlk -
-                * If we have the following image:
-                *              Uncompressed pixels   Compressed block sizes (4x4)
-                *      mip0:       22 x 22                   6 x 6
-                *      mip1:       11 x 11                   3 x 3
-                *      mip2:        5 x  5                   2 x 2
-                *      mip3:        2 x  2                   1 x 1
-                *      mip4:        1 x  1                   1 x 1
-                *
-                * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
-                * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
-                * divide-by-two integer math):
-                *      mip0:  6x6
-                *      mip1:  3x3
-                *      mip2:  1x1
-                *      mip3:  1x1
-                *
-                * This means that mip2 will be missing texels.
-                *
-                * Fix this by calculating the base mip's width and height, then convert that, and round it
-                * back up to get the level 0 size. Take the max of the converted size and the scaled up size.
-                */
-                if (device->physical_device->rad_info.chip_class >= GFX9 &&
-                    vk_format_is_compressed(image->vk_format)) {
-                        unsigned lvl_width  = radv_minify(image->info.width , range->baseMipLevel);
-                        unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
-
-                        lvl_width = round_up_u32(lvl_width * vk_format_get_blockwidth(iview->vk_format),
-                                                 vk_format_get_blockwidth(image->vk_format));
-                        lvl_height = round_up_u32(lvl_height * vk_format_get_blockheight(iview->vk_format),
-                                                  vk_format_get_blockheight(image->vk_format));
-
-                        iview->extent.width = MAX2(iview->extent.width, lvl_width << range->baseMipLevel);
-                        iview->extent.height = MAX2(iview->extent.height, lvl_height << range->baseMipLevel);
-                }
        }
 
        iview->base_layer = range->baseArrayLayer;