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mem: Hide WriteInvalidate requests from prefetchers
author
Curtis Dunham
<Curtis.Dunham@arm.com>
Tue, 23 Dec 2014 14:31:19 +0000
(09:31 -0500)
committer
Curtis Dunham
<Curtis.Dunham@arm.com>
Tue, 23 Dec 2014 14:31:19 +0000
(09:31 -0500)
Without this tweak, a prefetcher will happily prefetch data that will
promptly be invalidated and overwritten by a WriteInvalidate.
src/mem/cache/prefetch/base.cc
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diff --git
a/src/mem/cache/prefetch/base.cc
b/src/mem/cache/prefetch/base.cc
index 119397bb5339250e2dcee448e950379de3694e0c..3ab2d76a6a84c45444f70c3d68453e38834df8fc 100644
(file)
--- a/
src/mem/cache/prefetch/base.cc
+++ b/
src/mem/cache/prefetch/base.cc
@@
-83,7
+83,8
@@
BasePrefetcher::observeAccess(const PacketPtr &pkt) const
{
Addr addr = pkt->getAddr();
bool fetch = pkt->req->isInstFetch();
- bool read= pkt->isRead();
+ bool read = pkt->isRead();
+ bool inv = pkt->isInvalidate();
bool is_secure = pkt->isSecure();
if (pkt->req->isUncacheable()) return false;
@@
-91,6
+92,7
@@
BasePrefetcher::observeAccess(const PacketPtr &pkt) const
if (!fetch && !onData) return false;
if (!fetch && read && !onRead) return false;
if (!fetch && !read && !onWrite) return false;
+ if (!fetch && !read && inv) return false;
if (onMiss) {
return !inCache(addr, is_secure) &&