Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle)

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index b7a196602117e1d53ef99297de3ede0abacc20e5..d7e1f9afa04c73be8e18d6cd061f0b9eedb8ff42 100644 (file)
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -460,7 +460,6 @@ module SB_RAM40_4K (
                        if (!WMASK_I[13]) memory[WADDR[7:0]][13] <= WDATA_I[13];
                        if (!WMASK_I[14]) memory[WADDR[7:0]][14] <= WDATA_I[14];
                        if (!WMASK_I[15]) memory[WADDR[7:0]][15] <= WDATA_I[15];
-                       if (!WMASK_I[16]) memory[WADDR[7:0]][16] <= WDATA_I[16];
                end
        end