cse.c (cse_insn): When changing (set (pc) (reg)) to (set (pc) (label_ref))...

        * cse.c (cse_insn): When changing (set (pc) (reg)) to
        (set (pc) (label_ref)), verify the change creates a valid insn.

From-SVN: r31407

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2a61193cddb030c7aded8c41cfc5814343046013..08ce9e2e328a9d1f134d3af6d6c8381d0706c1ff 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,8 @@
 Fri Jan 14 00:28:06 2000  Jeffrey A Law  (law@cygnus.com)
 
+       * cse.c (cse_insn): When changing (set (pc) (reg)) to
+       (set (pc) (label_ref)), verify the change creates a valid insn.
+
        * fr30.c (call_operand): Tighten and rework to match rules for
        call RTL expressions.
        * fr30.h (PREDICATE_CODES, case call_operand): Only allow MEMs.

diff --git a/gcc/cse.c b/gcc/cse.c
index 25821abdb2b8a7f1b6a56ed8dc7a477eac660d5b..40d30a79d389c529ff7e9961966c246f1a3ef368 100644 (file)
--- a/gcc/cse.c
+++ b/gcc/cse.c
@@ -5189,8 +5189,18 @@ cse_insn (insn, libcall_insn)
 
                trial = gen_rtx_LABEL_REF (Pmode, get_label_after (trial));
 
-             SET_SRC (sets[i].rtl) = trial;
-             cse_jumps_altered = 1;
+             if (trial == pc_rtx)
+               {
+                 SET_SRC (sets[i].rtl) = trial;
+                 cse_jumps_altered = 1;
+                 break;
+               }
+
+             /* We must actually validate the change.  Consider a target
+                where unconditional jumps are more complex than
+                (set (pc) (label_ref)) such as the fr30.  */
+             if (validate_change (insn, &SET_SRC (sets[i].rtl), trial, 0))
+               cse_jumps_altered = 1;
              break;
            }