read_verilog cells_box.v before techmap

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index c10e42532a93e87ce0c3a365dd267305e2ec3f1a..d5e9b80c8caa1613c6f8c92733ae3aa33df5769c 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -282,8 +282,8 @@ struct SynthXilinxPass : public Pass
                if (check_label(active, run_from, run_to, "map_luts"))
                {
                        Pass::call(design, "opt -full");
-                       Pass::call(design, "techmap -map +/techmap.v");
                        Pass::call(design, "read_verilog +/xilinx/cells_box.v");
+                       Pass::call(design, "techmap -map +/techmap.v");
                        if (abc == "abc9")
                                Pass::call(design, abc + " -lut +/xilinx/cells.lut -box +/xilinx/cells.box" + string(retime ? " -dff" : ""));
                        else