if (util_cpu_caps.has_f16c &&
(src_length == 4 || src_length == 8)) {
- const char *intrinsic = NULL;
- if (src_length == 4) {
- src = lp_build_pad_vector(gallivm, src, 8);
- intrinsic = "llvm.x86.vcvtph2ps.128";
- }
- else {
- intrinsic = "llvm.x86.vcvtph2ps.256";
+ if (LLVM_VERSION_MAJOR < 11) {
+ const char *intrinsic = NULL;
+ if (src_length == 4) {
+ src = lp_build_pad_vector(gallivm, src, 8);
+ intrinsic = "llvm.x86.vcvtph2ps.128";
+ }
+ else {
+ intrinsic = "llvm.x86.vcvtph2ps.256";
+ }
+ return lp_build_intrinsic_unary(builder, intrinsic,
+ lp_build_vec_type(gallivm, f32_type), src);
+ } else {
+ /*
+ * XXX: could probably use on other archs as well.
+ * But if the cpu doesn't support it natively it looks like the backends still
+ * can't lower it and will try to call out to external libraries, which will crash.
+ */
+ /*
+ * XXX: lp_build_vec_type() would use int16 vector. Probably need to revisit
+ * this at some point.
+ */
+ src = LLVMBuildBitCast(builder, src,
+ LLVMVectorType(LLVMHalfTypeInContext(gallivm->context), src_length), "");
+ return LLVMBuildFPExt(builder, src, lp_build_vec_type(gallivm, f32_type), "");
}
- return lp_build_intrinsic_unary(builder, intrinsic,
- lp_build_vec_type(gallivm, f32_type), src);
}
- /* Convert int16 vector to int32 vector by zero ext (might generate bad code) */
h = LLVMBuildZExt(builder, src, int_vec_type, "");
return lp_build_smallfloat_to_float(gallivm, f32_type, h, 10, 5, 0, true);
}