/* condition codes - 3 bits */
AF_CC_SHIFT = 29,
- AF_CC_MASK = (7 << AF_CC_SHIFT),
- AF_CC_E = (0 << AF_CC_SHIFT),
- AF_CC_GT = (1 << AF_CC_SHIFT),
- AF_CC_GE = (2 << AF_CC_SHIFT),
- AF_CC_NE = (3 << AF_CC_SHIFT),
- AF_CC_LT = (4 << AF_CC_SHIFT),
- AF_CC_LE = (5 << AF_CC_SHIFT),
+ AF_CC_MASK = (7U << AF_CC_SHIFT),
+ AF_CC_E = (0U << AF_CC_SHIFT),
+ AF_CC_GT = (1U << AF_CC_SHIFT),
+ AF_CC_GE = (2U << AF_CC_SHIFT),
+ AF_CC_NE = (3U << AF_CC_SHIFT),
+ AF_CC_LT = (4U << AF_CC_SHIFT),
+ AF_CC_LE = (5U << AF_CC_SHIFT),
};
/* flags for FETCH instructions (TEX/VTX) */
* (0 if instruction doesn't exist for chip class) */
int slots[4];
/* flags (mostly autogenerated from instruction name) */
- int flags;
+ unsigned int flags;
};
/* FETCH instruction info */