* ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,

	divwe, divdeuo, divweuo, divdeo, divweo for A2.  Add icswepx.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index b59dc1361e644702acd79c6d57114bc8ec3f34bf..6725e021bc0e20ac85c5114bee0965ec7e1545ab 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2010-05-19  Alan Modra  <amodra@gmail.com>
+
+       * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
+       divwe, divdeuo, divweuo, divdeo, divweo for A2.  Add icswepx.
+
 2010-05-13  Alan Modra  <amodra@gmail.com>
 
        * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index b51da53411840de60f7dcac6bac3ff54cb9e36b8..0e882e74cefe8b45f0d0e74378a7afa335c43d6a 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -4110,10 +4110,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"dcblc",      X(31,390),      X_MASK, PPCCHLK|PPC476|TITAN, PPCNONE,  {CT, RA, RB}},
 {"stdfcmx",    APU(31,391,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
 
-{"divdeu",     XO(31,393,0,0), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
-{"divdeu.",    XO(31,393,0,1), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
-{"divweu",     XO(31,395,0,0), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
-{"divweu.",    XO(31,395,0,1), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
+{"divdeu",     XO(31,393,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
+{"divdeu.",    XO(31,393,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
+{"divweu",     XO(31,395,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
+{"divweu.",    XO(31,395,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
 
 {"dcblce",     X(31,398),      X_MASK,      PPCCHLK,   PPCNONE,        {CT, RA, RB}},
 
@@ -4131,10 +4131,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"mtdcrux",    X(31,419),      X_MASK,      PPC464,    PPCNONE,        {RA, RS}},
 
-{"divde",      XO(31,425,0,0), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
-{"divde.",     XO(31,425,0,1), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
-{"divwe",      XO(31,427,0,0), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
-{"divwe.",     XO(31,427,0,1), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
+{"divde",      XO(31,425,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
+{"divde.",     XO(31,425,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
+{"divwe",      XO(31,427,0,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
+{"divwe.",     XO(31,427,0,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
 
 {"slbie",      X(31,434),      XRTRA_MASK,  PPC64,     PPCNONE,        {RB}},
 
@@ -4681,10 +4681,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"stvlxl",     X(31,903),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
 {"stdfcmux",   APU(31,903,0),  APU_MASK,    PPC405,    PPCNONE,        {FCRT, RA, RB}},
 
-{"divdeuo",    XO(31,393,1,0), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
-{"divdeuo.",   XO(31,393,1,1), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
-{"divweuo",    XO(31,395,1,0), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
-{"divweuo.",   XO(31,395,1,1), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
+{"divdeuo",    XO(31,393,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
+{"divdeuo.",   XO(31,393,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
+{"divweuo",    XO(31,395,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
+{"divweuo.",   XO(31,395,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
 
 {"stxvw4x",    X(31,908),      XX1_MASK,    PPCVSX,    PPCNONE,        {XS6, RA, RB}},
 
@@ -4719,10 +4719,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"stvrxl",     X(31,935),      X_MASK,      CELL,      PPCNONE,        {VS, RA0, RB}},
 
-{"divdeo",     XO(31,425,1,0), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
-{"divdeo.",    XO(31,425,1,1), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
-{"divweo",     XO(31,427,1,0), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
-{"divweo.",    XO(31,427,1,1), XO_MASK,     POWER7,    PPCNONE,        {RT, RA, RB}},
+{"divdeo",     XO(31,425,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
+{"divdeo.",    XO(31,425,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
+{"divweo",     XO(31,427,1,0), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
+{"divweo.",    XO(31,427,1,1), XO_MASK,  POWER7|PPCA2, PPCNONE,        {RT, RA, RB}},
 
 {"tlbrehi",    XTLB(31,946,0), XTLB_MASK,   PPC403,    PPCA2,          {RT, RA}},
 {"tlbrelo",    XTLB(31,946,1), XTLB_MASK,   PPC403,    PPCA2,          {RT, RA}},
@@ -4730,6 +4730,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"sthcix",     X(31,949),      X_MASK,      POWER6,    PPCNONE,        {RS, RA0, RB}},
 
+{"icswepx",    XRC(31,950,0),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA, RB}},
+{"icswepx.",   XRC(31,950,1),  X_MASK,      PPCA2,     PPCNONE,        {RS, RA, RB}},
+
 {"stfqux",     X(31,951),      X_MASK,      POWER2,    PPCNONE,        {FRS, RA, RB}},
 
 {"sraiq",      XRC(31,952,0),  X_MASK,      M601,      PPCNONE,        {RA, RS, SH}},