PowerPC VLE extended instructions in powerpc_macros

This moves VLE insn out of the macro table.  "e_slwi" and "e_srwi"
already exist in vle_opcodes as distinct instructions rather than
encodings of e_rlwinm.

opcodes/
	* ppc-opc.c (vle_opcodes): Typo fix e_rlwinm operand.
	Add "e_inslwi", "e_insrwi", "e_rotlwi", "e_rotrwi", "e_clrlwi",
	"e_clrrwi", "e_extlwi", "e_extrwi", and "e_clrlslwi".
	(powerpc_macros): Delete same.  Delete "e_slwi" and "e_srwi" too.
gas/
	* testsuite/gas/ppc/vle-simple-5.d: Update.

diff --git a/gas/testsuite/gas/ppc/vle-simple-5.d b/gas/testsuite/gas/ppc/vle-simple-5.d
index 817df09d1cd83ae2bd0c1e5e050746b7079a2636..faae5f34abf92bf3f7f292fb52b85bddea61acb6 100644 (file)
--- a/gas/testsuite/gas/ppc/vle-simple-5.d
+++ b/gas/testsuite/gas/ppc/vle-simple-5.d
@@ -7,14 +7,14 @@
 Disassembly of section .text:
 
 0+0 <.text>:
-   0:  74 42 00 01     e_rlwinm r2,r2,0,0,0
+   0:  74 42 00 01     e_clrrwi r2,r2,31
    4:  74 62 7d bf     e_rlwinm r2,r3,15,22,31
    8:  74 a4 f8 48     e_rlwimi r4,r5,31,1,4
    c:  74 e6 c9 4c     e_rlwimi r6,r7,25,5,6
-  10:  74 41 50 3f     e_rlwinm r1,r2,10,0,31
-  14:  74 83 c0 3f     e_rlwinm r3,r4,24,0,31
+  10:  74 41 50 3f     e_rotlwi r1,r2,10
+  14:  74 83 c0 3f     e_rotlwi r3,r4,24
   18:  7c 62 f8 70     e_slwi  r2,r3,31
   1c:  7c 25 f4 70     e_srwi  r5,r1,30
-  20:  74 64 07 7f     e_rlwinm r4,r3,0,29,31
-  24:  74 41 00 07     e_rlwinm r1,r2,0,0,3
+  20:  74 64 07 7f     e_clrlwi r4,r3,29
+  24:  74 41 00 07     e_clrrwi r1,r2,28
   28:  74 e6 d8 49     e_rlwinm r6,r7,27,1,4

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 45d071963090d05af8e634acc6c858c752860293..12c1c414b7de0f95d2565385400ec750df98094c 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -10366,7 +10366,16 @@ const struct powerpc_opcode vle_opcodes[] = {
 {"e_add2i.",   I16A(28,17),    I16A_MASK,      PPCVLE, 0,              {RA, VLESIMM}},
 {"e_li",       LI20(28,0),     LI20_MASK,      PPCVLE, 0,              {RT, IMM20}},
 {"e_rlwimi",   M(29,0),        M_MASK,         PPCVLE, 0,              {RA, RS, SH, MB, ME}},
-{"e_rlwinm",   M(29,1),        M_MASK,         PPCVLE, 0,              {RA, RT, SH, MBE, ME}},
+{"e_inslwi",   M(29,0),        M_MASK,         PPCVLE, EXT,            {RA, RS, ILWn, ILWb}},
+{"e_insrwi",   M(29,0),        M_MASK,         PPCVLE, EXT,            {RA, RS, IRWn, IRWb}},
+{"e_rotlwi",   MME(29,31,1),   MMBME_MASK,     PPCVLE, EXT,            {RA, RS, SH}},
+{"e_rotrwi",   MME(29,31,1),   MMBME_MASK,     PPCVLE, EXT,            {RA, RS, RRWn}},
+{"e_clrlwi",   MME(29,31,1),   MSHME_MASK,     PPCVLE, EXT,            {RA, RS, MB}},
+{"e_clrrwi",   M(29,1),        MSHMB_MASK,     PPCVLE, EXT,            {RA, RS, CRWn}},
+{"e_rlwinm",   M(29,1),        M_MASK,         PPCVLE, 0,              {RA, RS, SH, MBE, ME}},
+{"e_extlwi",   M(29,1),        MMB_MASK,       PPCVLE, EXT,            {RA, RS, ELWn, SH}},
+{"e_extrwi",   MME(29,31,1),   MME_MASK,       PPCVLE, EXT,            {RA, RS, ERWn, ERWb}},
+{"e_clrlslwi", M(29,1),        M_MASK,         PPCVLE, EXT,            {RA, RS, CSLWb, CSLWn}},
 {"e_b",                BD24(30,0,0),   BD24_MASK,      PPCVLE, 0,              {B24}},
 {"e_bl",       BD24(30,0,1),   BD24_MASK,      PPCVLE, 0,              {B24}},
 {"e_bdnz",     EBD15(30,8,BO32DNZ,0),  EBD15_MASK, PPCVLE, EXT,        {B15}},
@@ -10486,18 +10495,6 @@ const unsigned int vle_num_opcodes =
    support extracting the whole word (32 bits in this case).  */
 
 const struct powerpc_macro powerpc_macros[] = {
-{"e_extlwi", 4,        PPCVLE, "e_rlwinm %0,%1,%3,0,(%2)-1"},
-{"e_extrwi", 4,        PPCVLE, "e_rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"},
-{"e_inslwi", 4,        PPCVLE, "e_rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
-{"e_insrwi", 4,        PPCVLE, "e_rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
-{"e_rotlwi", 3,        PPCVLE, "e_rlwinm %0,%1,%2,0,31"},
-{"e_rotrwi", 3,        PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31"},
-{"e_slwi",   3,        PPCVLE, "e_rlwinm %0,%1,%2,0,31-(%2)"},
-{"e_srwi",   3,        PPCVLE, "e_rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31"},
-{"e_clrlwi", 3,        PPCVLE, "e_rlwinm %0,%1,0,%2,31"},
-{"e_clrrwi", 3,        PPCVLE, "e_rlwinm %0,%1,0,0,31-(%2)"},
-{"e_clrlslwi",4, PPCVLE, "e_rlwinm %0,%1,%3,(%2)-(%3),31-(%3)"},
-
 /* old SPE instructions have new names with the same opcodes */
 {"evsadd",      3, PPCSPE|PPCVLE, "efsadd %0,%1,%2"},
 {"evssub",      3, PPCSPE|PPCVLE, "efssub %0,%1,%2"},