sim: remove PureSimulable (superseded by Module)

diff --git a/examples/sim/fir.py b/examples/sim/fir.py
index 2a4817d55f29cb2ddbc39836b948723a9e8bb55f..1e65b59a6006786c1e5c5d1e5020a2ab4134e671 100644 (file)
--- a/examples/sim/fir.py
+++ b/examples/sim/fir.py
@@ -6,10 +6,11 @@ from scipy import signal
 import matplotlib.pyplot as plt
 
 from migen.fhdl.structure import *
+from migen.fhdl.module import Module
 from migen.fhdl import verilog
 from migen.genlib.misc import optree
 from migen.fhdl import autofragment
-from migen.sim.generic import Simulator, PureSimulable
+from migen.sim.generic import Simulator
 
 # A synthesizable FIR filter.
 class FIR:
@@ -36,7 +37,7 @@ class FIR:
 
 # A test bench for our FIR filter.
 # Generates a sine wave at the input and records the output.
-class TB(PureSimulable):
+class TB(Module):
        def __init__(self, fir, frequency):
                self.fir = fir
                self.frequency = frequency

diff --git a/migen/actorlib/sim.py b/migen/actorlib/sim.py
index de11f1c9796812cda5ec14f380460cd5d4f3ac7d..c8c84aa1d600c9e083e097de49e9c0d5c9e6b9ff 100644 (file)
--- a/migen/actorlib/sim.py
+++ b/migen/actorlib/sim.py
@@ -1,7 +1,7 @@
 from migen.fhdl.structure import *
+from migen.fhdl.module import Module
 from migen.flow.actor import *
 from migen.flow.transactions import *
-from migen.sim.generic import PureSimulable
 
 # Generators yield None or a tuple of Tokens.
 # Tokens for Sink endpoints are pulled and the "value" field filled in.
@@ -9,7 +9,7 @@ from migen.sim.generic import PureSimulable
 #
 # NB: the possibility to push several tokens at once is important to interact
 # with actors that only accept a group of tokens when all of them are available.
-class TokenExchanger(PureSimulable):
+class TokenExchanger(Module):
        def __init__(self, generator, actor):
                self.generator = generator
                self.actor = actor

diff --git a/migen/bus/csr.py b/migen/bus/csr.py
index 44076e7ffaba312c081879a03f9714f5b3a70454..82b68aed074ee0d73dcfed9c017ca40bbc83c436 100644 (file)
--- a/migen/bus/csr.py
+++ b/migen/bus/csr.py
@@ -1,8 +1,8 @@
 from migen.fhdl.structure import *
 from migen.fhdl.specials import Memory
+from migen.fhdl.module import Module
 from migen.bus.simple import *
 from migen.bus.transactions import *
-from migen.sim.generic import PureSimulable
 from migen.bank.description import RegisterField
 from migen.genlib.misc import chooser
 
@@ -19,7 +19,7 @@ class Interface(SimpleInterface):
 class Interconnect(SimpleInterconnect):
        pass
 
-class Initiator(PureSimulable):
+class Initiator(Module):
        def __init__(self, generator, bus=None):
                self.generator = generator
                if bus is None:

diff --git a/migen/bus/memory.py b/migen/bus/memory.py
index 895d130e85a5ae9eb7006b05bb1f611bd59c1476..c99f0e725a397c777d23056600e7e74dc6b48dc3 100644 (file)
--- a/migen/bus/memory.py
+++ b/migen/bus/memory.py
@@ -1,5 +1,5 @@
+from migen.fhdl.module import Module
 from migen.bus.transactions import *
-from migen.sim.generic import PureSimulable
 
 def _byte_mask(orig, dat_w, sel):
        r = 0
@@ -15,7 +15,7 @@ def _byte_mask(orig, dat_w, sel):
                shift += 8
        return r
 
-class Initiator(PureSimulable):
+class Initiator(Module):
        def __init__(self, generator, mem):
                self.generator = generator
                self.mem = mem

diff --git a/migen/bus/wishbone.py b/migen/bus/wishbone.py
index 23abfa6e75de72800f1cf93cfd2a1e74ee182af1..89ef3dda668c2bc412b1d13c4faafece98187274 100644 (file)
--- a/migen/bus/wishbone.py
+++ b/migen/bus/wishbone.py
@@ -1,10 +1,11 @@
 from migen.fhdl.structure import *
 from migen.fhdl.specials import Memory
+from migen.fhdl.module import Module
 from migen.genlib import roundrobin
 from migen.genlib.misc import optree
 from migen.bus.simple import *
 from migen.bus.transactions import *
-from migen.sim.generic import Proxy, PureSimulable
+from migen.sim.generic import Proxy
 
 _desc = Description(
        (M_TO_S,        "adr",          30),
@@ -116,7 +117,7 @@ class InterconnectShared:
        def get_fragment(self):
                return self._arbiter.get_fragment() + self._decoder.get_fragment()
 
-class Tap(PureSimulable):
+class Tap(Module):
        def __init__(self, bus, handler=print):
                self.bus = bus
                self.handler = handler
@@ -133,7 +134,7 @@ class Tap(PureSimulable):
                                        s.rd(self.bus.dat_r))
                        self.handler(transaction)
 
-class Initiator(PureSimulable):
+class Initiator(Module):
        def __init__(self, generator, bus=None):
                self.generator = generator
                if bus is None:
@@ -180,7 +181,7 @@ class TargetModel:
        def can_ack(self, bus):
                return True
 
-class Target(PureSimulable):
+class Target(Module):
        def __init__(self, model, bus=None):
                if bus is None:
                        bus = Interface()

diff --git a/migen/flow/hooks.py b/migen/flow/hooks.py
index 9272d9be77e9605f3d9dc139c65137cac87cb05b..7d2d36586a9bcb695b829bfdba4eed986c4131b1 100644 (file)
--- a/migen/flow/hooks.py
+++ b/migen/flow/hooks.py
@@ -1,8 +1,8 @@
 from migen.fhdl.structure import *
+from migen.fhdl.module import Module
 from migen.flow.actor import *
-from migen.sim.generic import PureSimulable
 
-class EndpointSimHook(PureSimulable):
+class EndpointSimHook(Module):
        def __init__(self, endpoint):
                self.endpoint = endpoint
        

diff --git a/migen/sim/generic.py b/migen/sim/generic.py
index ff47e6568de86aa639d4541869c5e76f1fb63d7d..960c15bbe0b6ab798d24ecdc43379149a1c800ff 100644 (file)
--- a/migen/sim/generic.py
+++ b/migen/sim/generic.py
@@ -203,10 +203,3 @@ class Proxy:
                item = getattr(self._obj, name)
                assert(isinstance(item, Signal))
                self._sim.wr(item, value)
-
-class PureSimulable:
-       def do_simulation(self, s):
-               raise NotImplementedError("Need to overload do_simulation")
-       
-       def get_fragment(self):
-               return Fragment(sim=[self.do_simulation])