Add fmvis instruction + tests, bug #887

diff --git a/openpower/isa/av.mdwn b/openpower/isa/av.mdwn
index 72cbd1cb4c28e7ea6a8fb0439b9b005a5b6daf62..64bde71f7e12f9eae9dfddf2013814fe441a2b5f 100644 (file)
--- a/openpower/isa/av.mdwn
+++ b/openpower/isa/av.mdwn
@@ -206,3 +206,16 @@ Special Registers Altered:
 
     None
 
+# Load Floating-Point Immediate 
+
+X-Form
+
+* fmvis FRS,FRS,SI
+
+Pseudo-code:
+
+    FRS <- EXTS(SI)
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isatables/RM-2P-1S1D.csv b/openpower/isatables/RM-2P-1S1D.csv
index 31d93e24f81d7a87537577df40875ecec10c65aa..a505496c2b8d2b1e08179bc234de1de29d777fec 100644 (file)
--- a/openpower/isatables/RM-2P-1S1D.csv
+++ b/openpower/isatables/RM-2P-1S1D.csv
@@ -27,6 +27,7 @@ oris,NORMAL,,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
 xori,NORMAL,,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
 xoris,NORMAL,,2P,EXTRA3,d:RA,s:RS,0,0,RS,0,0,RA,0,0,0
 subfic,NORMAL,,2P,EXTRA3,d:RT,s:RA,0,0,RA,0,0,RT,0,0,0
+fmvis,NORMAL,,2P,EXTRA3,TODO,0,0,0,FRS,0,0,FRS,0,0,0
 cntlzw,NORMAL,,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
 cntlzd,NORMAL,,2P,EXTRA3,d:RA;d:CR0,s:RS,0,0,RS,0,0,RA,0,CR0,0
 subfze,NORMAL,,2P,EXTRA3,d:RT;d:CR0,s:RA,0,0,RA,0,0,RT,0,CR0,0

diff --git a/openpower/isatables/minor_22.csv b/openpower/isatables/minor_22.csv
index 8d01d5a41764da378c727164c17fc9fbbd070358..ddc7fa203a1fd31f67d0e2cb398d3b5fad9167ce 100644 (file)
--- a/openpower/isatables/minor_22.csv
+++ b/openpower/isatables/minor_22.csv
@@ -19,3 +19,4 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 # Vector bitmanip
 0110001110-,ALU,OP_CPROP,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,cprop,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg
 ------10001,ALU,OP_BMASK,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,bmask,BM2,,1,unofficial until submitted and approved/renumbered by the opf isa wg
+------00011,ALU,OP_FMVIS,FRS,CONST_UI,NONE,FRS,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,fmvis,DX,,1,unofficial until submitted and approved/renumbered by the opf isa wg

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 729dbe9bc371aa408417462fb54f0b4051953907..c6096b25936af62f73f4eb84d36d0e669e09bc76 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1236,6 +1236,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
                     'setvl', 'svindex', 'svremap', 'svstep', 'svshape',
                     'grev', 'ternlogi', 'bmask', 'cprop',
                     'absdu', 'absds', 'absdacs', 'absdacu', 'avgadd',
+                    'fmvis',
                     ]:
             illegal = False
             ins_name = dotstrp

diff --git a/src/openpower/decoder/isa/test_caller_fmvis.py b/src/openpower/decoder/isa/test_caller_fmvis.py
new file mode 100644 (file)
index 0000000..ce44d03
--- /dev/null
+++ b/src/openpower/decoder/isa/test_caller_fmvis.py
@@ -0,0 +1,38 @@
+""" Decoder tests
+
+related bugs:
+
+ *
+"""
+
+import unittest
+import sys
+
+# These tests utilize the run_hdl=False parameter to compare
+# simulator with expected states
+from soc.simple.test.test_runner import TestRunner
+from openpower.test.alu.fmvis_cases import FMVISTestCase
+
+
+if __name__ == "__main__":
+
+    # allow list of testing to be selected by command-line
+    testing = sys.argv[1:]
+    sys.argv = sys.argv[:1]
+
+    if not testing:
+        testing = ['fmvis']
+
+    unittest.main(exit=False)
+    suite = unittest.TestSuite()
+
+    # dictionary  of data for tests
+    tests = {'fmvis': FMVISTestCase().test_data}
+
+    # walk through all tests, those requested get added
+    for tname, data in tests.items():
+        if tname in testing:
+            suite.addTest(TestRunner(data, run_hdl=False))
+
+    runner = unittest.TextTestRunner()
+    runner.run(suite)

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 39338032708f8b574d5a299a7ea8d9d3f0ae8101..a5e928806aedae9ce3cae898fd744cd693c5f7f7 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -294,6 +294,7 @@ _insns = [
     "fmul", "fmuls", "fdiv", "fdivs",                   # FP mul / div
     "fmr", "fabs", "fnabs", "fneg", "fcpsgn",           # FP move/abs/neg
     "fsins", "fcoss",                                   # FP SIN/COS
+    "fmvis",                                            # FP load immediate
     'grev', 'grev.', 'grevi', 'grevi.',
     'grevw', 'grevw.', 'grevwi', 'grevwi.',
     "hrfid", "icbi", "icbt", "isel", "isync",
@@ -461,6 +462,7 @@ class MicrOp(Enum):
     OP_CPROP = 93
     OP_BMASK = 94
     OP_SVINDEX = 95
+    OP_FMVIS = 96
 
 
 @unique

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 2b44fd230e8f81579370156538bde2eb36e79713..735f9f37935a3893dfe9cb890fd330ecc20daa4c 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -332,6 +332,24 @@ def av(fields, XO, Rc):
     )
 
 
+def fmvis(fields):
+    # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
+    # V3.0B 1.6.6 DX-FORM
+    # |0     |6 |7|8|9  |10  |11|12|13  |15|16|17     |26|27    |31  |
+    # | PO   |   FRS         |     d1      |      d0     |   XO |d2  |
+    PO = 22
+    XO = 0b000011
+    (FRS, d0, d1, d2) = fields
+    return instruction(
+        (PO , 0 , 5),
+        (FRS, 6 , 10),
+        (d0 , 11, 15),
+        (d1 , 16, 26),
+        (XO , 27, 30),
+        (d2 , 31, 31),
+    )
+
+
 CUSTOM_INSNS = {}
 for (name, hook) in (
             ("setvl", setvl),
@@ -339,6 +357,7 @@ for (name, hook) in (
             ("fsins", fsins),
             ("fcoss", fcoss),
             ("ternlogi", ternlogi),
+            ("fmvis", fmvis)
         ):
     CUSTOM_INSNS[name] = functools.partial(hook, Rc=False)
     CUSTOM_INSNS[f"{name}."] = functools.partial(hook, Rc=True)
@@ -369,6 +388,7 @@ for (name, XO) in (
             ("absdacu", 0b1111110110),
             ("absdacs", 0b0111110110),
             ("cprop"  , 0b0110001110),
+            ("fmvis"  , 0b0000000011),
         ):
     CUSTOM_INSNS[name] = functools.partial(av, XO=XO, Rc=False)
     CUSTOM_INSNS[f"{name}."] = functools.partial(av, XO=XO, Rc=True)
@@ -1303,7 +1323,6 @@ class SVP64Asm:
                 insn |= 1 << (31-31)     # Rc=1     , bit 31
             log("fcoss", bin(insn))
             yield ".long 0x%x" % insn
-
         else:
             yield "%s %s" % (v30b_op+rc, ", ".join(v30b_newfields))
         log("new v3.0B fields", v30b_op, v30b_newfields)

diff --git a/src/openpower/test/alu/fmvis_cases.py b/src/openpower/test/alu/fmvis_cases.py
new file mode 100644 (file)
index 0000000..3e057e4
--- /dev/null
+++ b/src/openpower/test/alu/fmvis_cases.py
@@ -0,0 +1,26 @@
+from openpower.sv.trans.svp64 import SVP64Asm
+import random
+from openpower.test.common import TestAccumulatorBase
+from openpower.endian import bigendian
+from openpower.simulator.program import Program
+from openpower.decoder.selectable_int import SelectableInt
+from openpower.decoder.power_enums import XER_bits
+from openpower.decoder.isa.caller import special_sprs
+from openpower.decoder.helpers import exts
+from openpower.test.state import ExpectedState
+import unittest
+
+class FMVISTestCase(TestAccumulatorBase):
+
+    def case_0_fmvis(self):
+        lst = SVP64Asm(["fmvis 5, 5, 0x4000",
+                        "fmvis 6, 6, 0x2122",
+                        "fmvis 7, 7, 0x3E80",
+                       ])
+        lst = list(lst)
+
+        expected_fprs = [0] * 32
+        expected_fprs[5] = 0x40000000
+        expected_fprs[6] = 0x21220000
+        expected_fprs[7] = 0x3E800000
+        self.add_case(Program(lst, bigendian), expected_fprs)