// it's a CAM that's used to generate 2 tables (below)
// just as in RV, writing to entries in this CAM *clears*
// all entries with a higher index
-typedef struct {
- unsigned int type : 1; // 0=INT, 1=FP
- uint64_t regkey : 5; // 5 bits
- unsigned int elwidth: 2; // 0=8-bit, 1=dflt, 2=dflt/2 3=dflt*2
- uint64_t regidx : 6; // yes 6 bits
- unsigned int isvec : 1; // vector=1, scalar=0
- unsigned int packed : 1; // Packed SIMD=1
-} sv_reg_csr_entry;
+union sv_reg_csr_entry {
+ struct {
+ unsigned int type : 1; // 0=INT, 1=FP
+ uint64_t regkey : 5; // 5 bits
+ unsigned int elwidth: 2; // 0=8-bit, 1=dflt, 2=dflt/2 3=dflt*2
+ uint64_t regidx : 6; // yes 6 bits
+ unsigned int isvec : 1; // vector=1, scalar=0
+ unsigned int packed : 1; // Packed SIMD=1
+ } b;
+ unsigned short u;
+};
// TODO: define separate SV CSRs for M-mode and S-Mode
// M-Mode and S-Mode will need a minimum of 2 for int-only
unsigned int active : 1; // enabled=1, disabled=0
} sv_reg_entry;
-typedef struct {
- unsigned int type : 1; // 0=INT, 1=FP
- uint64_t regkey: 5; // 5 bits
- unsigned int zero : 1; // zeroing=1, skipping=0
- unsigned int inv : 1; // inversion=1
- uint64_t regidx: 6; // 6 bits
- unsigned int active: 1; // enabled=1, disabled=0
-} sv_pred_csr_entry;
+union sv_pred_csr_entry {
+ struct {
+ unsigned int type : 1; // 0=INT, 1=FP
+ uint64_t regkey: 5; // 5 bits
+ unsigned int zero : 1; // zeroing=1, skipping=0
+ unsigned int inv : 1; // inversion=1
+ uint64_t regidx: 6; // 6 bits
+ unsigned int active: 1; // enabled=1, disabled=0
+ } b;
+ unsigned short u;
+};
typedef struct {
uint64_t regkey: 5; // 5 bits