build/io/InferedSDRTristate: pass clock domain to SDROutput/SDRInput.

diff --git a/litex/build/io.py b/litex/build/io.py
index f18f08ac24113e171bf3ce2db9ff45b10f2186da..42f9531ee215e518e59b6afdce6af89f5fbc3787 100644 (file)
--- a/litex/build/io.py
+++ b/litex/build/io.py
@@ -81,8 +81,8 @@ class InferedSDRTristate(Module):
         _o  = Signal()
         _oe = Signal()
         _i  = Signal()
-        self.specials += SDROutput(o, _o)
-        self.specials += SDRInput(_i, i)
+        self.specials += SDROutput(o, _o, clk)
+        self.specials += SDRInput(_i, i, clk)
         self.submodules += InferedSDRIO(oe, _oe, clk, clk_domain)
         self.specials += Tristate(io, _o, _oe, _i)