#include "arch/sparc/sparc_traits.hh"
#include "arch/sparc/types.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
#include "cpu/static_inst_fwd.hh"
namespace BigEndianGuest {}
const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
const Addr BytesInPageMask = ULL(0x1FFF);
-#if FULL_SYSTEM
enum InterruptTypes
{
IT_TRAP_LEVEL_ZERO,
NumInterruptTypes
};
-#endif
-
// Memory accesses cannot be unaligned
const bool HasUnalignedMemAcc = false;
}
Import('*')
-if env['FULL_SYSTEM']:
- SimObject('VncServer.py')
- Source('vncserver.cc')
- DebugFlag('VNC')
-
Source('convert.cc')
+SimObject('VncServer.py')
+Source('vncserver.cc')
+DebugFlag('VNC')
SimObject('FuncUnit.py')
SimObject('ExeTracer.py')
SimObject('IntelTrace.py')
+SimObject('IntrControl.py')
SimObject('NativeTrace.py')
Source('activity.cc')
Source('exetrace.cc')
Source('func_unit.cc')
Source('inteltrace.cc')
+Source('intr_control.cc')
Source('nativetrace.cc')
Source('pc_event.cc')
Source('quiesce_event.cc')
Source('thread_state.cc')
if env['FULL_SYSTEM']:
- SimObject('IntrControl.py')
-
- Source('intr_control.cc')
Source('profile.cc')
if env['TARGET_ISA'] == 'sparc':
void
IntrControl::post(int cpu_id, int int_num, int index)
{
+#if FULL_SYSTEM
DPRINTF(IntrControl, "post %d:%d (cpu %d)\n", int_num, index, cpu_id);
std::vector<ThreadContext *> &tcvec = sys->threadContexts;
BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr();
cpu->postInterrupt(int_num, index);
+#else
+ panic("Called IntrControl::post in SE mode.\n");
+#endif
}
void
IntrControl::clear(int cpu_id, int int_num, int index)
{
+#if FULL_SYSTEM
DPRINTF(IntrControl, "clear %d:%d (cpu %d)\n", int_num, index, cpu_id);
std::vector<ThreadContext *> &tcvec = sys->threadContexts;
BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr();
cpu->clearInterrupt(int_num, index);
+#else
+ panic("Called IntrControl::clear in SE mode.\n");
+#endif
}
IntrControl *
if env['TARGET_ISA'] == 'no':
Return()
-if env['FULL_SYSTEM']:
- SimObject('BadDevice.py')
- SimObject('CopyEngine.py')
- SimObject('Device.py')
- SimObject('DiskImage.py')
- SimObject('Ethernet.py')
- SimObject('Ide.py')
- SimObject('Pci.py')
- SimObject('Platform.py')
- SimObject('SimpleDisk.py')
- SimObject('Terminal.py')
- SimObject('Uart.py')
+SimObject('BadDevice.py')
+SimObject('CopyEngine.py')
+SimObject('Device.py')
+SimObject('DiskImage.py')
+SimObject('Ethernet.py')
+SimObject('Ide.py')
+SimObject('Pci.py')
+SimObject('Platform.py')
+SimObject('SimpleDisk.py')
+SimObject('Terminal.py')
+SimObject('Uart.py')
- Source('baddev.cc')
- Source('copy_engine.cc')
- Source('disk_image.cc')
- Source('etherbus.cc')
- Source('etherdevice.cc')
- Source('etherdump.cc')
- Source('etherint.cc')
- Source('etherlink.cc')
- Source('etherpkt.cc')
- Source('ethertap.cc')
- Source('i8254xGBe.cc')
- Source('ide_ctrl.cc')
- Source('ide_disk.cc')
- Source('intel_8254_timer.cc')
- Source('io_device.cc')
- Source('isa_fake.cc')
- Source('mc146818.cc')
- Source('ns_gige.cc')
- Source('pciconfigall.cc')
- Source('pcidev.cc')
- Source('pktfifo.cc')
- Source('platform.cc')
- Source('ps2.cc')
- Source('simple_disk.cc')
- Source('sinic.cc')
- Source('terminal.cc')
- Source('uart.cc')
- Source('uart8250.cc')
+Source('baddev.cc')
+Source('copy_engine.cc')
+Source('disk_image.cc')
+Source('etherbus.cc')
+Source('etherdevice.cc')
+Source('etherdump.cc')
+Source('etherint.cc')
+Source('etherlink.cc')
+Source('etherpkt.cc')
+Source('ethertap.cc')
+Source('i8254xGBe.cc')
+Source('ide_ctrl.cc')
+Source('ide_disk.cc')
+Source('intel_8254_timer.cc')
+Source('io_device.cc')
+Source('isa_fake.cc')
+Source('mc146818.cc')
+Source('ns_gige.cc')
+Source('pciconfigall.cc')
+Source('pcidev.cc')
+Source('pktfifo.cc')
+Source('platform.cc')
+Source('ps2.cc')
+Source('simple_disk.cc')
+Source('sinic.cc')
+Source('terminal.cc')
+Source('uart.cc')
+Source('uart8250.cc')
- DebugFlag('DiskImageRead')
- DebugFlag('DiskImageWrite')
- DebugFlag('DMA')
- DebugFlag('DMACopyEngine')
- DebugFlag('Ethernet')
- DebugFlag('EthernetCksum')
- DebugFlag('EthernetDMA')
- DebugFlag('EthernetData')
- DebugFlag('EthernetDesc')
- DebugFlag('EthernetEEPROM')
- DebugFlag('EthernetIntr')
- DebugFlag('EthernetPIO')
- DebugFlag('EthernetSM')
- DebugFlag('IdeCtrl')
- DebugFlag('IdeDisk')
- DebugFlag('Intel8254Timer')
- DebugFlag('IsaFake')
- DebugFlag('MC146818')
- DebugFlag('PCIDEV')
- DebugFlag('PciConfigAll')
- DebugFlag('SimpleDisk')
- DebugFlag('SimpleDiskData')
- DebugFlag('Terminal')
- DebugFlag('TerminalVerbose')
- DebugFlag('Uart')
-
- CompoundFlag('DiskImageAll', [ 'DiskImageRead', 'DiskImageWrite' ])
- CompoundFlag('EthernetAll', [ 'Ethernet', 'EthernetPIO', 'EthernetDMA',
- 'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM',
- 'EthernetCksum', 'EthernetEEPROM' ])
- CompoundFlag('EthernetNoData', [ 'Ethernet', 'EthernetPIO', 'EthernetDesc',
- 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ])
- CompoundFlag('IdeAll', [ 'IdeCtrl', 'IdeDisk' ])
+DebugFlag('DiskImageRead')
+DebugFlag('DiskImageWrite')
+DebugFlag('DMA')
+DebugFlag('DMACopyEngine')
+DebugFlag('Ethernet')
+DebugFlag('EthernetCksum')
+DebugFlag('EthernetDMA')
+DebugFlag('EthernetData')
+DebugFlag('EthernetDesc')
+DebugFlag('EthernetEEPROM')
+DebugFlag('EthernetIntr')
+DebugFlag('EthernetPIO')
+DebugFlag('EthernetSM')
+DebugFlag('IdeCtrl')
+DebugFlag('IdeDisk')
+DebugFlag('Intel8254Timer')
+DebugFlag('IsaFake')
+DebugFlag('MC146818')
+DebugFlag('PCIDEV')
+DebugFlag('PciConfigAll')
+DebugFlag('SimpleDisk')
+DebugFlag('SimpleDiskData')
+DebugFlag('Terminal')
+DebugFlag('TerminalVerbose')
+DebugFlag('Uart')
+CompoundFlag('DiskImageAll', [ 'DiskImageRead', 'DiskImageWrite' ])
+CompoundFlag('EthernetAll', [ 'Ethernet', 'EthernetPIO', 'EthernetDMA',
+ 'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM',
+ 'EthernetCksum', 'EthernetEEPROM' ])
+CompoundFlag('EthernetNoData', [ 'Ethernet', 'EthernetPIO', 'EthernetDesc',
+ 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ])
+CompoundFlag('IdeAll', [ 'IdeCtrl', 'IdeDisk' ])
#
# Authors: Nathan Binkert
+from m5.defines import buildEnv
from m5.params import *
from m5.proxy import *
from Device import BasicPioDevice
cpu = Param.BaseCPU(Parent.cpu[0], "Processor")
disk = Param.SimpleDisk("Simple Disk")
terminal = Param.Terminal(Parent.any, "The console terminal")
- system = Param.AlphaSystem(Parent.any, "system object")
+ if buildEnv['FULL_SYSTEM']: # No AlphaSystem in SE mode.
+ system = Param.AlphaSystem(Parent.any, "system object")
Import('*')
-if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'alpha':
+if env['TARGET_ISA'] == 'alpha':
SimObject('AlphaBackdoor.py')
SimObject('Tsunami.py')
#include <cstddef>
#include <string>
+#include "config/full_system.hh"
+
+#if FULL_SYSTEM //XXX No AlphaSystem in SE mode.
#include "arch/alpha/system.hh"
+#endif
#include "base/inifile.hh"
#include "base/str.hh"
#include "base/trace.hh"
AlphaBackdoor::AlphaBackdoor(const Params *p)
: BasicPioDevice(p), disk(p->disk), terminal(p->terminal),
- system(p->system), cpu(p->cpu)
+#if FULL_SYSTEM //XXX No system pointer in SE mode.
+ system(p->system),
+#endif
+ cpu(p->cpu)
{
pioSize = sizeof(struct AlphaAccess);
void
AlphaBackdoor::startup()
{
+#if FULL_SYSTEM //XXX No system pointer in SE mode.
system->setAlphaAccess(pioAddr);
alphaAccess->numCPUs = system->numContexts();
alphaAccess->kernStart = system->getKernelStart();
alphaAccess->mem_size = system->physmem->size();
alphaAccess->cpuClock = cpu->frequency() / 1000000; // In MHz
alphaAccess->intrClockFrequency = params()->platform->intrFrequency();
+#endif
}
Tick
/** the system console (the terminal) is accessable from the console */
Terminal *terminal;
+#if FULL_SYSTEM //XXX No AlphaSystem defined in SE mode.
/** a pointer to the system we are running in */
AlphaSystem *system;
+#endif
/** a pointer to the CPU boot cpu */
BaseCPU *cpu;
Tsunami::Tsunami(const Params *p)
: Platform(p), system(p->system)
{
+#if FULL_SYSTEM //XXX No platform pointer in SE mode.
// set the back pointer from the system to myself
system->platform = this;
+#endif
for (int i = 0; i < Tsunami::Max_CPUs; i++)
intr_sum_type[i] = 0;
Import('*')
-if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'arm':
+if env['TARGET_ISA'] == 'arm':
SimObject('RealView.py')
Source('a9scu.cc')
#include "debug/Checkpoint.hh"
#include "debug/GIC.hh"
#include "debug/IPI.hh"
+#include "debug/Interrupt.hh"
#include "dev/arm/gic.hh"
#include "dev/arm/realview.hh"
#include "dev/terminal.hh"
RealView::RealView(const Params *p)
: Platform(p), system(p->system)
{
+#if FULL_SYSTEM //XXX No platform pointer on the system object in SE mode.
// set the back pointer from the system to myself
system->platform = this;
+#endif
}
Tick
Import('*')
-if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'mips':
+if env['TARGET_ISA'] == 'mips':
SimObject('Malta.py')
DebugFlag('Malta')
#include "config/the_isa.hh"
#include "cpu/intr_control.hh"
+#include "debug/Malta.hh"
#include "dev/mips/malta.hh"
#include "dev/mips/malta_cchip.hh"
#include "dev/mips/malta_io.hh"
Malta::Malta(const Params *p)
: Platform(p), system(p->system)
{
+#if FULL_SYSTEM //XXX No platform pointer on the system object in SE mode.
// set the back pointer from the system to myself
system->platform = this;
+#endif
for (int i = 0; i < Malta::Max_CPUs; i++)
intr_sum_type[i] = 0;
#include "config/the_isa.hh"
#include "cpu/intr_control.hh"
#include "cpu/thread_context.hh"
+#include "debug/Malta.hh"
#include "dev/mips/malta.hh"
#include "dev/mips/malta_cchip.hh"
#include "dev/mips/maltareg.h"
#include "base/time.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
+#include "debug/Malta.hh"
#include "dev/mips/malta.hh"
#include "dev/mips/malta_cchip.hh"
#include "dev/mips/malta_io.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
+#include "debug/Malta.hh"
#include "dev/mips/malta.hh"
#include "dev/mips/malta_pchip.hh"
#include "dev/mips/maltareg.h"
for (int i = 0, j = 0; i < count; i += SectorSize, j++)
image->read(data + i, block + j);
+#if FULL_SYSTEM //XXX No functional port in SE mode.
system->functionalPort->writeBlob(addr, data, count);
+#endif
DPRINTF(SimpleDisk, "read block=%#x len=%d\n", (uint64_t)block, count);
DDUMP(SimpleDiskData, data, count);
Import('*')
-if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'sparc':
+if env['TARGET_ISA'] == 'sparc':
SimObject('T1000.py')
Source('dtod.cc')
#include "base/bitfield.hh"
#include "base/trace.hh"
#include "cpu/intr_control.hh"
+#include "cpu/thread_context.hh"
#include "debug/Iob.hh"
#include "dev/sparc/iob.hh"
#include "dev/platform.hh"
T1000::T1000(const Params *p)
: Platform(p), system(p->system)
{
+#if FULL_SYSTEM //XXX No platform pointer on system objects in SE mode.
// set the back pointer from the system to myself
system->platform = this;
+#endif
}
Tick
Import('*')
-if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
+if env['TARGET_ISA'] == 'x86':
SimObject('Pc.py')
Source('pc.cc')
* Authors: Gabe Black
*/
+#include "config/full_system.hh"
+
+#if FULL_SYSTEM
#include "arch/x86/interrupts.hh"
+#endif
+
#include "arch/x86/intmessage.hh"
#include "debug/I82094AA.hh"
#include "dev/x86/i82094aa.hh"
DPRINTF(I82094AA, "Entry was masked.\n");
return;
} else {
+#if FULL_SYSTEM //XXX No interrupt controller in SE mode.
TriggerIntMessage message = 0;
message.destination = entry.dest;
if (entry.deliveryMode == DeliveryMode::ExtInt) {
}
intPort->sendMessage(apics, message,
sys->getMemoryMode() == Enums::timing);
+#endif
}
}
{
southBridge = NULL;
// set the back pointer from the system to myself
+#if FULL_SYSTEM //XXX No platform pointer in SE mode.
system->platform = this;
+#endif
}
void