SE/FS: Build the devices in SE mode.
authorGabe Black <gblack@eecs.umich.edu>
Fri, 30 Sep 2011 07:28:33 +0000 (00:28 -0700)
committerGabe Black <gblack@eecs.umich.edu>
Fri, 30 Sep 2011 07:28:33 +0000 (00:28 -0700)
25 files changed:
src/arch/sparc/isa_traits.hh
src/base/vnc/SConscript
src/cpu/SConscript
src/cpu/intr_control.cc
src/dev/SConscript
src/dev/alpha/AlphaBackdoor.py
src/dev/alpha/SConscript
src/dev/alpha/backdoor.cc
src/dev/alpha/backdoor.hh
src/dev/alpha/tsunami.cc
src/dev/arm/SConscript
src/dev/arm/gic.cc
src/dev/arm/realview.cc
src/dev/mips/SConscript
src/dev/mips/malta.cc
src/dev/mips/malta_cchip.cc
src/dev/mips/malta_io.cc
src/dev/mips/malta_pchip.cc
src/dev/simple_disk.cc
src/dev/sparc/SConscript
src/dev/sparc/iob.cc
src/dev/sparc/t1000.cc
src/dev/x86/SConscript
src/dev/x86/i82094aa.cc
src/dev/x86/pc.cc

index 620d9c40221301acd5fbae20f1c9199e3a99e321..9b02a4d80f619d7caebec08a1cb641e09ed18970 100644 (file)
@@ -35,7 +35,6 @@
 #include "arch/sparc/sparc_traits.hh"
 #include "arch/sparc/types.hh"
 #include "base/types.hh"
-#include "config/full_system.hh"
 #include "cpu/static_inst_fwd.hh"
 
 namespace BigEndianGuest {}
@@ -78,7 +77,6 @@ const Addr VAddrAMask = ULL(0xFFFFFFFF);
 const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
 const Addr BytesInPageMask = ULL(0x1FFF);
 
-#if FULL_SYSTEM
 enum InterruptTypes
 {
     IT_TRAP_LEVEL_ZERO,
@@ -91,8 +89,6 @@ enum InterruptTypes
     NumInterruptTypes
 };
 
-#endif
-
 // Memory accesses cannot be unaligned
 const bool HasUnalignedMemAcc = false;
 }
index 089509b9b77baba0b3caa5c3a233639b99251748..62448cd706a2960a49f09495477ecc0a04ef3eb0 100644 (file)
 
 Import('*')
 
-if env['FULL_SYSTEM']:
-    SimObject('VncServer.py')
-    Source('vncserver.cc')
-    DebugFlag('VNC')
-
 Source('convert.cc')
 
+SimObject('VncServer.py')
+Source('vncserver.cc')
+DebugFlag('VNC')
index a1074cb8b6bb73c51b405d2895a482158949fff7..370b8390981427b402cd6841bebd8ef0131200a1 100644 (file)
@@ -109,6 +109,7 @@ SimObject('BaseCPU.py')
 SimObject('FuncUnit.py')
 SimObject('ExeTracer.py')
 SimObject('IntelTrace.py')
+SimObject('IntrControl.py')
 SimObject('NativeTrace.py')
 
 Source('activity.cc')
@@ -118,6 +119,7 @@ Source('decode.cc')
 Source('exetrace.cc')
 Source('func_unit.cc')
 Source('inteltrace.cc')
+Source('intr_control.cc')
 Source('nativetrace.cc')
 Source('pc_event.cc')
 Source('quiesce_event.cc')
@@ -127,9 +129,6 @@ Source('thread_context.cc')
 Source('thread_state.cc')
 
 if env['FULL_SYSTEM']:
-    SimObject('IntrControl.py')
-
-    Source('intr_control.cc')
     Source('profile.cc')
 
     if env['TARGET_ISA'] == 'sparc':
index 8f3808889e69979fd5caecd9f3db8cadb39853d7..62be4ea1930953923e139e8ed3d9bd67d98747ac 100644 (file)
@@ -48,19 +48,27 @@ IntrControl::IntrControl(const Params *p)
 void
 IntrControl::post(int cpu_id, int int_num, int index)
 {
+#if FULL_SYSTEM
     DPRINTF(IntrControl, "post  %d:%d (cpu %d)\n", int_num, index, cpu_id);
     std::vector<ThreadContext *> &tcvec = sys->threadContexts;
     BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr();
     cpu->postInterrupt(int_num, index);
+#else
+    panic("Called IntrControl::post in SE mode.\n");
+#endif
 }
 
 void
 IntrControl::clear(int cpu_id, int int_num, int index)
 {
+#if FULL_SYSTEM
     DPRINTF(IntrControl, "clear %d:%d (cpu %d)\n", int_num, index, cpu_id);
     std::vector<ThreadContext *> &tcvec = sys->threadContexts;
     BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr();
     cpu->clearInterrupt(int_num, index);
+#else
+    panic("Called IntrControl::clear in SE mode.\n");
+#endif
 }
 
 IntrControl *
index 744e7b3c1fdee328d18cb040a7d1e7a28d2fd826..c041081b598fa7afa6e0a3a5e9d23b5f647eb024 100644 (file)
@@ -34,79 +34,77 @@ Import('*')
 if env['TARGET_ISA'] == 'no':
     Return()
 
-if env['FULL_SYSTEM']:
-    SimObject('BadDevice.py')
-    SimObject('CopyEngine.py')
-    SimObject('Device.py')
-    SimObject('DiskImage.py')
-    SimObject('Ethernet.py')
-    SimObject('Ide.py')
-    SimObject('Pci.py')
-    SimObject('Platform.py')
-    SimObject('SimpleDisk.py')
-    SimObject('Terminal.py')
-    SimObject('Uart.py')
+SimObject('BadDevice.py')
+SimObject('CopyEngine.py')
+SimObject('Device.py')
+SimObject('DiskImage.py')
+SimObject('Ethernet.py')
+SimObject('Ide.py')
+SimObject('Pci.py')
+SimObject('Platform.py')
+SimObject('SimpleDisk.py')
+SimObject('Terminal.py')
+SimObject('Uart.py')
 
-    Source('baddev.cc')
-    Source('copy_engine.cc')
-    Source('disk_image.cc')
-    Source('etherbus.cc')
-    Source('etherdevice.cc')
-    Source('etherdump.cc')
-    Source('etherint.cc')
-    Source('etherlink.cc')
-    Source('etherpkt.cc')
-    Source('ethertap.cc')
-    Source('i8254xGBe.cc')
-    Source('ide_ctrl.cc')
-    Source('ide_disk.cc')
-    Source('intel_8254_timer.cc')
-    Source('io_device.cc')
-    Source('isa_fake.cc')
-    Source('mc146818.cc')
-    Source('ns_gige.cc')
-    Source('pciconfigall.cc')
-    Source('pcidev.cc')
-    Source('pktfifo.cc')
-    Source('platform.cc')
-    Source('ps2.cc')
-    Source('simple_disk.cc')
-    Source('sinic.cc')
-    Source('terminal.cc')
-    Source('uart.cc')
-    Source('uart8250.cc')
+Source('baddev.cc')
+Source('copy_engine.cc')
+Source('disk_image.cc')
+Source('etherbus.cc')
+Source('etherdevice.cc')
+Source('etherdump.cc')
+Source('etherint.cc')
+Source('etherlink.cc')
+Source('etherpkt.cc')
+Source('ethertap.cc')
+Source('i8254xGBe.cc')
+Source('ide_ctrl.cc')
+Source('ide_disk.cc')
+Source('intel_8254_timer.cc')
+Source('io_device.cc')
+Source('isa_fake.cc')
+Source('mc146818.cc')
+Source('ns_gige.cc')
+Source('pciconfigall.cc')
+Source('pcidev.cc')
+Source('pktfifo.cc')
+Source('platform.cc')
+Source('ps2.cc')
+Source('simple_disk.cc')
+Source('sinic.cc')
+Source('terminal.cc')
+Source('uart.cc')
+Source('uart8250.cc')
 
-    DebugFlag('DiskImageRead')
-    DebugFlag('DiskImageWrite')
-    DebugFlag('DMA')
-    DebugFlag('DMACopyEngine')
-    DebugFlag('Ethernet')
-    DebugFlag('EthernetCksum')
-    DebugFlag('EthernetDMA')
-    DebugFlag('EthernetData')
-    DebugFlag('EthernetDesc')
-    DebugFlag('EthernetEEPROM')
-    DebugFlag('EthernetIntr')
-    DebugFlag('EthernetPIO')
-    DebugFlag('EthernetSM')
-    DebugFlag('IdeCtrl')
-    DebugFlag('IdeDisk')
-    DebugFlag('Intel8254Timer')
-    DebugFlag('IsaFake')
-    DebugFlag('MC146818')
-    DebugFlag('PCIDEV')
-    DebugFlag('PciConfigAll')
-    DebugFlag('SimpleDisk')
-    DebugFlag('SimpleDiskData')
-    DebugFlag('Terminal')
-    DebugFlag('TerminalVerbose')
-    DebugFlag('Uart')
-
-    CompoundFlag('DiskImageAll', [ 'DiskImageRead', 'DiskImageWrite' ])
-    CompoundFlag('EthernetAll', [ 'Ethernet', 'EthernetPIO', 'EthernetDMA',
-        'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM',
-        'EthernetCksum', 'EthernetEEPROM' ])
-    CompoundFlag('EthernetNoData', [ 'Ethernet', 'EthernetPIO', 'EthernetDesc',
-        'EthernetIntr', 'EthernetSM', 'EthernetCksum' ])
-    CompoundFlag('IdeAll', [ 'IdeCtrl', 'IdeDisk' ])
+DebugFlag('DiskImageRead')
+DebugFlag('DiskImageWrite')
+DebugFlag('DMA')
+DebugFlag('DMACopyEngine')
+DebugFlag('Ethernet')
+DebugFlag('EthernetCksum')
+DebugFlag('EthernetDMA')
+DebugFlag('EthernetData')
+DebugFlag('EthernetDesc')
+DebugFlag('EthernetEEPROM')
+DebugFlag('EthernetIntr')
+DebugFlag('EthernetPIO')
+DebugFlag('EthernetSM')
+DebugFlag('IdeCtrl')
+DebugFlag('IdeDisk')
+DebugFlag('Intel8254Timer')
+DebugFlag('IsaFake')
+DebugFlag('MC146818')
+DebugFlag('PCIDEV')
+DebugFlag('PciConfigAll')
+DebugFlag('SimpleDisk')
+DebugFlag('SimpleDiskData')
+DebugFlag('Terminal')
+DebugFlag('TerminalVerbose')
+DebugFlag('Uart')
 
+CompoundFlag('DiskImageAll', [ 'DiskImageRead', 'DiskImageWrite' ])
+CompoundFlag('EthernetAll', [ 'Ethernet', 'EthernetPIO', 'EthernetDMA',
+    'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM',
+    'EthernetCksum', 'EthernetEEPROM' ])
+CompoundFlag('EthernetNoData', [ 'Ethernet', 'EthernetPIO', 'EthernetDesc',
+    'EthernetIntr', 'EthernetSM', 'EthernetCksum' ])
+CompoundFlag('IdeAll', [ 'IdeCtrl', 'IdeDisk' ])
index fa9627164ad2964cf2a5ab60e430c7bc72a295e7..f7402f5937421e4fdd6985269bbda342ea155c39 100644 (file)
@@ -26,6 +26,7 @@
 #
 # Authors: Nathan Binkert
 
+from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
 from Device import BasicPioDevice
@@ -35,4 +36,5 @@ class AlphaBackdoor(BasicPioDevice):
     cpu = Param.BaseCPU(Parent.cpu[0], "Processor")
     disk = Param.SimpleDisk("Simple Disk")
     terminal = Param.Terminal(Parent.any, "The console terminal")
-    system = Param.AlphaSystem(Parent.any, "system object")
+    if buildEnv['FULL_SYSTEM']: # No AlphaSystem in SE mode.
+        system = Param.AlphaSystem(Parent.any, "system object")
index 32baa6f487d676ca89d1a387b66ea3f00111f4a1..9c8a5b4cee7e4051314e270e6ca972609994ae5d 100644 (file)
@@ -31,7 +31,7 @@
 
 Import('*')
 
-if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'alpha':
+if env['TARGET_ISA'] == 'alpha':
     SimObject('AlphaBackdoor.py')
     SimObject('Tsunami.py')
 
index 31ab628664a5368d897d79a31b84f0392f835095..4d9d046ded56ef2661b6e28b033ef712eb1e5e00 100644 (file)
 #include <cstddef>
 #include <string>
 
+#include "config/full_system.hh"
+
+#if FULL_SYSTEM //XXX No AlphaSystem in SE mode.
 #include "arch/alpha/system.hh"
+#endif
 #include "base/inifile.hh"
 #include "base/str.hh"
 #include "base/trace.hh"
@@ -60,7 +64,10 @@ using namespace AlphaISA;
 
 AlphaBackdoor::AlphaBackdoor(const Params *p)
     : BasicPioDevice(p), disk(p->disk), terminal(p->terminal),
-      system(p->system), cpu(p->cpu)
+#if FULL_SYSTEM //XXX No system pointer in SE mode.
+      system(p->system),
+#endif
+      cpu(p->cpu)
 {
 
     pioSize = sizeof(struct AlphaAccess);
@@ -84,6 +91,7 @@ AlphaBackdoor::AlphaBackdoor(const Params *p)
 void
 AlphaBackdoor::startup()
 {
+#if FULL_SYSTEM //XXX No system pointer in SE mode.
     system->setAlphaAccess(pioAddr);
     alphaAccess->numCPUs = system->numContexts();
     alphaAccess->kernStart = system->getKernelStart();
@@ -92,6 +100,7 @@ AlphaBackdoor::startup()
     alphaAccess->mem_size = system->physmem->size();
     alphaAccess->cpuClock = cpu->frequency() / 1000000; // In MHz
     alphaAccess->intrClockFrequency = params()->platform->intrFrequency();
+#endif
 }
 
 Tick
index 2acaba9a3696970a014bf41c9dcfaa8272f98762..5249ce71fc5f05ecfb17da4e00d590e46b6c632c 100644 (file)
@@ -92,8 +92,10 @@ class AlphaBackdoor : public BasicPioDevice
     /** the system console (the terminal) is accessable from the console */
     Terminal *terminal;
 
+#if FULL_SYSTEM //XXX No AlphaSystem defined in SE mode.
     /** a pointer to the system we are running in */
     AlphaSystem *system;
+#endif
 
     /** a pointer to the CPU boot cpu */
     BaseCPU *cpu;
index 34aab6ed02f718a93cf24366fa1f6029ebb33caf..16e2bfb28b522f6a539f36b013d237bc635bab14 100644 (file)
@@ -52,8 +52,10 @@ using namespace TheISA;
 Tsunami::Tsunami(const Params *p)
     : Platform(p), system(p->system)
 {
+#if FULL_SYSTEM //XXX No platform pointer in SE mode.
     // set the back pointer from the system to myself
     system->platform = this;
+#endif
 
     for (int i = 0; i < Tsunami::Max_CPUs; i++)
         intr_sum_type[i] = 0;
index 07a3e14ae532307f80f6c55317666cee2d7d0037..deedcb49fc87449255e3f1b9a11113cc17951de2 100644 (file)
@@ -39,7 +39,7 @@
 
 Import('*')
 
-if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'arm':
+if env['TARGET_ISA'] == 'arm':
     SimObject('RealView.py')
 
     Source('a9scu.cc')
index 2dac18c0887f398e502088cfb972106e956e2383..ddea4873f8fe050e01a830d654657a507d1c88f1 100644 (file)
@@ -45,6 +45,7 @@
 #include "debug/Checkpoint.hh"
 #include "debug/GIC.hh"
 #include "debug/IPI.hh"
+#include "debug/Interrupt.hh"
 #include "dev/arm/gic.hh"
 #include "dev/arm/realview.hh"
 #include "dev/terminal.hh"
index 8cc318f899360c6e7a618f7b401498ae4433b218..ed6365efcfb7f61d7a44717ca00eb61fb3be5604 100644 (file)
@@ -61,8 +61,10 @@ using namespace TheISA;
 RealView::RealView(const Params *p)
     : Platform(p), system(p->system)
 {
+#if FULL_SYSTEM //XXX No platform pointer on the system object in SE mode.
     // set the back pointer from the system to myself
     system->platform = this;
+#endif
 }
 
 Tick
index 369dbfed2cc2fb5d36c1791b06738bf7decaeb56..801b1916d1e22420dc2f20e0923ee2c3d9c5205a 100755 (executable)
@@ -31,7 +31,7 @@
 
 Import('*')
 
-if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'mips':
+if env['TARGET_ISA'] == 'mips':
     SimObject('Malta.py')
 
     DebugFlag('Malta')
index bcf970745b248215eca59e81988219180b19922a..df949c2cf93dd2ec58c85f56d29b3f46db07851a 100755 (executable)
@@ -39,6 +39,7 @@
 
 #include "config/the_isa.hh"
 #include "cpu/intr_control.hh"
+#include "debug/Malta.hh"
 #include "dev/mips/malta.hh"
 #include "dev/mips/malta_cchip.hh"
 #include "dev/mips/malta_io.hh"
@@ -53,8 +54,10 @@ using namespace TheISA;
 Malta::Malta(const Params *p)
     : Platform(p), system(p->system)
 {
+#if FULL_SYSTEM //XXX No platform pointer on the system object in SE mode.
     // set the back pointer from the system to myself
     system->platform = this;
+#endif
 
     for (int i = 0; i < Malta::Max_CPUs; i++)
         intr_sum_type[i] = 0;
index b2d5069c52542c5545efe866b3bf1e4c72a18fc4..e5eafeec22b643cf0f45c7d63026354a5ed6f4ac 100755 (executable)
@@ -42,6 +42,7 @@
 #include "config/the_isa.hh"
 #include "cpu/intr_control.hh"
 #include "cpu/thread_context.hh"
+#include "debug/Malta.hh"
 #include "dev/mips/malta.hh"
 #include "dev/mips/malta_cchip.hh"
 #include "dev/mips/maltareg.h"
index bd9288487c530b88ce298868c8068e05a42fea7f..1ae5442bf0feb250d41557c696321b30bf19568f 100755 (executable)
@@ -43,6 +43,7 @@
 #include "base/time.hh"
 #include "base/trace.hh"
 #include "config/the_isa.hh"
+#include "debug/Malta.hh"
 #include "dev/mips/malta.hh"
 #include "dev/mips/malta_cchip.hh"
 #include "dev/mips/malta_io.hh"
index 7832a31bd57e66233bcf121ad4d9e7911d7e7d2e..dd1993cc693827378a0a9b339412e918acc0925f 100755 (executable)
@@ -39,6 +39,7 @@
 
 #include "base/trace.hh"
 #include "config/the_isa.hh"
+#include "debug/Malta.hh"
 #include "dev/mips/malta.hh"
 #include "dev/mips/malta_pchip.hh"
 #include "dev/mips/maltareg.h"
index 4bf24b1cd64032c9c0fbc677c38f07311d559348..890c90dbfb1d5362f9ee46119b6dd361027376ca 100644 (file)
@@ -70,7 +70,9 @@ SimpleDisk::read(Addr addr, baddr_t block, int count) const
     for (int i = 0, j = 0; i < count; i += SectorSize, j++)
         image->read(data + i, block + j);
 
+#if FULL_SYSTEM //XXX No functional port in SE mode.
     system->functionalPort->writeBlob(addr, data, count);
+#endif
 
     DPRINTF(SimpleDisk, "read  block=%#x len=%d\n", (uint64_t)block, count);
     DDUMP(SimpleDiskData, data, count);
index 772aa48647b0fb680295811c7e832b848fb865e0..e82e5ee054a2b03591d8de704c4c96e45e432f98 100644 (file)
@@ -31,7 +31,7 @@
 
 Import('*')
 
-if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'sparc':
+if env['TARGET_ISA'] == 'sparc':
     SimObject('T1000.py')
 
     Source('dtod.cc')
index 748a08c81a8011ae7846bc9632c9b0446f0575bc..cbb0bbde0dac7786bd6e64f99dde8b64d90007f0 100644 (file)
@@ -42,6 +42,7 @@
 #include "base/bitfield.hh"
 #include "base/trace.hh"
 #include "cpu/intr_control.hh"
+#include "cpu/thread_context.hh"
 #include "debug/Iob.hh"
 #include "dev/sparc/iob.hh"
 #include "dev/platform.hh"
index c00d942c940bc7d7bf598614df9f9d2b9f8f68aa..2c3d3c071fd2f9b59a0a9e6037a98940913720a2 100644 (file)
@@ -49,8 +49,10 @@ using namespace TheISA;
 T1000::T1000(const Params *p)
     : Platform(p), system(p->system)
 {
+#if FULL_SYSTEM //XXX No platform pointer on system objects in SE mode.
     // set the back pointer from the system to myself
     system->platform = this;
+#endif
 }
 
 Tick
index eeb68cf44aee6852873bc2c12bfda6262051064a..038e4824b8d1730751a6ba25a427490fa0b4f9b8 100644 (file)
@@ -30,7 +30,7 @@
 
 Import('*')
 
-if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'x86':
+if env['TARGET_ISA'] == 'x86':
     SimObject('Pc.py')
     Source('pc.cc')
 
index 584090a9eb5665b440a72033eac3a8eb8ed518f1..be7852e86f6f67d508920ef84848916561b9c5af 100644 (file)
  * Authors: Gabe Black
  */
 
+#include "config/full_system.hh"
+
+#if FULL_SYSTEM
 #include "arch/x86/interrupts.hh"
+#endif
+
 #include "arch/x86/intmessage.hh"
 #include "debug/I82094AA.hh"
 #include "dev/x86/i82094aa.hh"
@@ -167,6 +172,7 @@ X86ISA::I82094AA::signalInterrupt(int line)
         DPRINTF(I82094AA, "Entry was masked.\n");
         return;
     } else {
+#if FULL_SYSTEM //XXX No interrupt controller in SE mode.
         TriggerIntMessage message = 0;
         message.destination = entry.dest;
         if (entry.deliveryMode == DeliveryMode::ExtInt) {
@@ -225,6 +231,7 @@ X86ISA::I82094AA::signalInterrupt(int line)
         }
         intPort->sendMessage(apics, message,
                 sys->getMemoryMode() == Enums::timing);
+#endif
     }
 }
 
index 7912a45e162c9267c30e55c5e83a952a3b2511d0..ec2bb209c1c241fcce8fcfc5514e396e29b35903 100644 (file)
@@ -56,7 +56,9 @@ Pc::Pc(const Params *p)
 {
     southBridge = NULL;
     // set the back pointer from the system to myself
+#if FULL_SYSTEM //XXX No platform pointer in SE mode.
     system->platform = this;
+#endif
 }
 
 void