Multi-arch GDB_TARGET_IS_MIPS64.

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index 0b14ff32fafdeb26389a1a030021f0b1a0743136..011481705c0f5c24c1d098b2b09b1a4b4d2c74f4 100644 (file)
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,13 @@
+Mon Jun 12 14:26:02 2000  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * mips-tdep.c (GDB_TARGET_IS_MIPS64): Define.
+       (struct gdbarch_tdep): Add gdb_target_is_mips64.
+       (mips_addr_bits_remove): Update.
+       (mips_gdbarch_init): Initialize.
+
+       * config/mips/tm-mips64.h (GDB_TARGET_IS_MIPS64,
+       GDB_TARGET_IS_MIPS64): Delete.
+
 Mon Jun 12 12:17:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 
        * mips-tdep.c: Include "symcat.h".

diff --git a/gdb/config/mips/tm-mips.h b/gdb/config/mips/tm-mips.h
index 3f007cdfa6f212b439e09ecfdfb1ba152367bb31..220e242de96d5888eb055ca11ac5865a67ee558a 100644 (file)
--- a/gdb/config/mips/tm-mips.h
+++ b/gdb/config/mips/tm-mips.h
@@ -35,10 +35,6 @@ struct value;
 #include "coff/sym.h"          /* Needed for PDR below.  */
 #include "coff/symconst.h"
 
-#if !defined (GDB_TARGET_IS_MIPS64)
-#define GDB_TARGET_IS_MIPS64 0
-#endif
-
 #if !defined (MIPS_EABI)
 #define MIPS_EABI 0
 #endif

diff --git a/gdb/config/mips/tm-mips64.h b/gdb/config/mips/tm-mips64.h
index f13fa7a37b9bd12895a638e03a068accc26ee592..cb193e6112349e8b1fe58428b2a919e2006396bb 100644 (file)
--- a/gdb/config/mips/tm-mips64.h
+++ b/gdb/config/mips/tm-mips64.h
@@ -1,5 +1,5 @@
 /* Target machine parameters for MIPS r4000
-   Copyright 1994, 1996 Free Software Foundation, Inc.
+   Copyright 1994, 1996, 2000 Free Software Foundation, Inc.
    Contributed by Ian Lance Taylor (ian@cygnus.com)
 
    This file is part of GDB.
@@ -19,8 +19,6 @@
    Foundation, Inc., 59 Temple Place - Suite 330,
    Boston, MA 02111-1307, USA.  */
 
-#define GDB_TARGET_IS_MIPS64 1
-
 /* Use eight byte registers.  */
 #define MIPS_REGSIZE 8
 

diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c
index ef1d3f0908f6cf9149b02a104153fc11f8b72ac8..f3223a45b5ae8d8a3c16e8ae3b7c0950abb3c6f0 100644 (file)
--- a/gdb/mips-tdep.c
+++ b/gdb/mips-tdep.c
@@ -122,6 +122,7 @@ struct gdbarch_tdep
     int mips_fp_register_double;
     int mips_regs_have_home_p;
     int mips_default_stack_argsize;
+    int gdb_target_is_mips64;
   };
 
 #if GDB_MULTI_ARCH
@@ -215,7 +216,10 @@ mips_stack_argsize (void)
     return 4;
 }
 
-
+#if GDB_MULTI_ARCH
+#undef GDB_TARGET_IS_MIPS64
+#define GDB_TARGET_IS_MIPS64 (gdbarch_tdep (current_gdbarch)->gdb_target_is_mips64 + 0)
+#endif
 
 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
 
@@ -1308,31 +1312,34 @@ CORE_ADDR
 mips_addr_bits_remove (addr)
      CORE_ADDR addr;
 {
-#if GDB_TARGET_IS_MIPS64
-  if (mask_address_p && (addr >> 32 == (CORE_ADDR) 0xffffffff))
+  if (GDB_TARGET_IS_MIPS64)
+    {
+      if (mask_address_p && (addr >> 32 == (CORE_ADDR) 0xffffffff))
+       {
+         /* This hack is a work-around for existing boards using
+            PMON, the simulator, and any other 64-bit targets that
+            doesn't have true 64-bit addressing.  On these targets,
+            the upper 32 bits of addresses are ignored by the
+            hardware.  Thus, the PC or SP are likely to have been
+            sign extended to all 1s by instruction sequences that
+            load 32-bit addresses.  For example, a typical piece of
+            code that loads an address is this: lui $r2, <upper 16
+            bits> ori $r2, <lower 16 bits> But the lui sign-extends
+            the value such that the upper 32 bits may be all 1s.  The
+            workaround is simply to mask off these bits.  In the
+            future, gcc may be changed to support true 64-bit
+            addressing, and this masking will have to be disabled.  */
+         addr &= (CORE_ADDR) 0xffffffff;
+       }
+    }
+  else
     {
-      /* This hack is a work-around for existing boards using PMON,
-         the simulator, and any other 64-bit targets that doesn't have
-         true 64-bit addressing.  On these targets, the upper 32 bits
-         of addresses are ignored by the hardware.  Thus, the PC or SP
-         are likely to have been sign extended to all 1s by instruction
-         sequences that load 32-bit addresses.  For example, a typical
-         piece of code that loads an address is this:
-         lui $r2, <upper 16 bits>
-         ori $r2, <lower 16 bits>
-         But the lui sign-extends the value such that the upper 32 bits
-         may be all 1s.  The workaround is simply to mask off these bits.
-         In the future, gcc may be changed to support true 64-bit
-         addressing, and this masking will have to be disabled.  */
+      /* Even when GDB is configured for some 32-bit targets
+        (e.g. mips-elf), BFD is configured to handle 64-bit targets,
+        so CORE_ADDR is 64 bits.  So we still have to mask off
+        useless bits from addresses.  */
       addr &= (CORE_ADDR) 0xffffffff;
     }
-#else
-  /* Even when GDB is configured for some 32-bit targets (e.g. mips-elf),
-     BFD is configured to handle 64-bit targets, so CORE_ADDR is 64 bits.
-     So we still have to mask off useless bits from addresses.  */
-  addr &= (CORE_ADDR) 0xffffffff;
-#endif
-
   return addr;
 }
 
@@ -3942,6 +3949,7 @@ mips_gdbarch_init (info, arches)
       tdep->mips_last_arg_regnum = ZERO_REGNUM + 7;
       tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 15;
       tdep->mips_regs_have_home_p = 1;
+      tdep->gdb_target_is_mips64 = 0;
       set_gdbarch_long_bit (gdbarch, 32);
       set_gdbarch_ptr_bit (gdbarch, 32);
       set_gdbarch_long_long_bit (gdbarch, 64);
@@ -3953,6 +3961,7 @@ mips_gdbarch_init (info, arches)
       tdep->mips_last_arg_regnum = ZERO_REGNUM + 7;
       tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 15;
       tdep->mips_regs_have_home_p = 1;
+      tdep->gdb_target_is_mips64 = 1;
       set_gdbarch_long_bit (gdbarch, 32);
       set_gdbarch_ptr_bit (gdbarch, 32);
       set_gdbarch_long_long_bit (gdbarch, 64);
@@ -3964,6 +3973,7 @@ mips_gdbarch_init (info, arches)
       tdep->mips_last_arg_regnum = ZERO_REGNUM + 11;
       tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19;
       tdep->mips_regs_have_home_p = 0;
+      tdep->gdb_target_is_mips64 = 0;
       set_gdbarch_long_bit (gdbarch, 32);
       set_gdbarch_ptr_bit (gdbarch, 32);
       set_gdbarch_long_long_bit (gdbarch, 64);
@@ -3975,6 +3985,7 @@ mips_gdbarch_init (info, arches)
       tdep->mips_last_arg_regnum = ZERO_REGNUM + 11;
       tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19;
       tdep->mips_regs_have_home_p = 0;
+      tdep->gdb_target_is_mips64 = 1;
       set_gdbarch_long_bit (gdbarch, 64);
       set_gdbarch_ptr_bit (gdbarch, 64);
       set_gdbarch_long_long_bit (gdbarch, 64);
@@ -3986,6 +3997,7 @@ mips_gdbarch_init (info, arches)
       tdep->mips_last_arg_regnum = ZERO_REGNUM + 11;
       tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19;
       tdep->mips_regs_have_home_p = 0;
+      tdep->gdb_target_is_mips64 = 0;
       set_gdbarch_long_bit (gdbarch, 32);
       set_gdbarch_ptr_bit (gdbarch, 32);
       set_gdbarch_long_long_bit (gdbarch, 64);
@@ -3997,6 +4009,7 @@ mips_gdbarch_init (info, arches)
       tdep->mips_last_arg_regnum = ZERO_REGNUM + 11;
       tdep->mips_last_fp_arg_regnum = FP0_REGNUM + 19;
       tdep->mips_regs_have_home_p = 1;
+      tdep->gdb_target_is_mips64 = 0;
       set_gdbarch_long_bit (gdbarch, 32);
       set_gdbarch_ptr_bit (gdbarch, 32);
       set_gdbarch_long_long_bit (gdbarch, 64);