[submodule "misoc/cores/mor1kx/verilog"]
path = misoc/cores/mor1kx/verilog
url = https://github.com/openrisc/mor1kx.git
-[submodule "misoc/software/compiler-rt"]
- path = misoc/software/compiler-rt
+[submodule "misoc/software/compiler_rt"]
+ path = misoc/software/compiler_rt
url = http://llvm.org/git/compiler-rt.git
[submodule "misoc/software/unwinder"]
path = misoc/software/unwinder
+++ /dev/null
-import binascii
-
-
-def insert_crc(i_filename, fbi_mode=False, o_filename=None):
- if o_filename is None:
- o_filename = i_filename
-
- with open(i_filename, 'rb') as f:
- fdata = f.read()
- fcrc = binascii.crc32(fdata).to_bytes(4, byteorder="big")
- flength = len(fdata).to_bytes(4, byteorder="big")
-
- with open(o_filename, 'wb') as f:
- if fbi_mode:
- f.write(flength)
- f.write(fcrc)
- f.write(fdata)
- else:
- f.write(fdata)
- f.write(fcrc)
+++ /dev/null
-#!/usr/bin/env python3
-
-import os
-import sys
-import argparse
-
-from migen.util.misc import autotype
-
-from misoc_import import misoc_import
-
-if __name__ == "__main__":
- parser = argparse.ArgumentParser(description="Program extra data to flash memory.")
- parser.add_argument("-f", "--flash-proxy-dir", default=None, help="set search directory for flash proxy bitstreams")
- parser.add_argument("-X", "--external", default="", help="use external directory for platforms and imports")
- parser.add_argument("-Op", "--platform-option", default=[], nargs=2, action="append", help="set platform-specific option")
- parser.add_argument("platform", help="target platform")
- parser.add_argument("file", help="file to flash")
- parser.add_argument("address", help="flash address to write")
- args = parser.parse_args()
-
- external_platform = ""
- if args.external:
- external_platform = os.path.join(args.external, "platforms")
- sys.path.insert(1, os.path.abspath(args.external))
-
- platform_module = misoc_import("mibuild.platforms", external_platform, args.platform)
- platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option)
- platform = platform_module.Platform(**platform_kwargs)
-
- prog = platform.create_programmer()
- prog.set_flash_proxy_dir(args.flash_proxy_dir)
- prog.flash(int(args.address, 0), args.file)
+++ /dev/null
-#!/usr/bin/env python3
-
-import sys
-import os
-import argparse
-import subprocess
-import struct
-
-from migen.build.tools import write_to_file
-from migen.util.misc import autotype
-from migen.fhdl import simplify
-
-from misoc.integration import cpu_interface
-from misoc.integration import sdram_init
-
-from misoc_import import misoc_import
-
-
-def _get_args():
- parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter,
- description="""\
-MiSoC - a high performance and small footprint SoC based on Migen.
-
-This program builds and/or loads MiSoC components.
-One or several actions can be specified:
-
-clean delete previous build(s).
-build-bitstream build FPGA bitstream. Implies build-bios on targets with
- integrated BIOS.
-build-headers build software header files with CPU/CSR/IRQ/SDRAM_PHY definitions.
-build-csr-csv save CSR map into CSV file.
-build-bios build BIOS. Implies build-header.
-
-load-bitstream load bitstream into volatile storage.
-flash-bitstream load bitstream into non-volatile storage.
-flash-bios load BIOS into non-volatile storage.
-
-all clean, build-bitstream, build-bios, flash-bitstream, flash-bios.
-
-Load/flash actions use the existing outputs, and do not trigger new builds.
-""")
-
- parser.add_argument("-t", "--target", default="mlabs_video", help="SoC type to build")
- parser.add_argument("-s", "--sub-target", default="", help="variant of the SoC type to build")
- parser.add_argument("-p", "--platform", default=None, help="platform to build for")
- parser.add_argument("-Ot", "--target-option", default=[], nargs=2, action="append", help="set target-specific option")
- parser.add_argument("-Op", "--platform-option", default=[], nargs=2, action="append", help="set platform-specific option")
- parser.add_argument("-X", "--external", default="", help="use external directory for targets, platforms and imports")
- parser.add_argument("--csr_csv", default="csr.csv", help="CSV file to save the CSR map into")
-
- parser.add_argument("-d", "--decorate", default=[], action="append", help="apply simplification decorator to top-level")
- parser.add_argument("-Ob", "--build-option", default=[], nargs=2, action="append", help="set build option")
- parser.add_argument("-f", "--flash-proxy-dir", default=None, help="set search directory for flash proxy bitstreams")
-
- parser.add_argument("action", nargs="+", help="specify an action")
-
- return parser.parse_args()
-
-if __name__ == "__main__":
- args = _get_args()
-
- external_target = ""
- external_platform = ""
- if args.external:
- external_target = os.path.join(args.external, "targets")
- external_platform = os.path.join(args.external, "platforms")
- sys.path.insert(0, os.path.abspath(args.external))
-
- # create top-level SoC object
- target_module = misoc_import("targets", external_target, args.target)
- if args.sub_target:
- top_class = getattr(target_module, args.sub_target)
- else:
- top_class = target_module.default_subtarget
-
- if args.platform is None:
- if hasattr(top_class, "default_platform"):
- platform_name = top_class.default_platform
- else:
- raise ValueError("Target has no default platform, specify a platform with -p your_platform")
- else:
- platform_name = args.platform
- platform_module = misoc_import("migen.build.platforms", external_platform, platform_name)
- platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option)
- platform = platform_module.Platform(**platform_kwargs)
- if args.external:
- platform.soc_ext_path = os.path.abspath(args.external)
-
- build_name = args.target + "-" + top_class.__name__.lower() + "-" + platform_name
- top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
- soc = top_class(platform, **top_kwargs)
- soc.finalize()
- memory_regions = soc.get_memory_regions()
- csr_regions = soc.get_csr_regions()
-
- # decode actions
- action_list = ["clean", "build-bitstream", "build-headers", "build-csr-csv", "build-bios",
- "load-bitstream", "flash-bitstream", "flash-bios", "all"]
- actions = {k: False for k in action_list}
- for action in args.action:
- if action in actions:
- actions[action] = True
- else:
- print("Unknown action: {}. Valid actions are:".format(action))
- for a in action_list:
- print(" "+a)
- sys.exit(1)
-
- print("""\
- __ ___ _ ____ _____
- / |/ / (_) / __/__ / ___/
- / /|_/ / / / _\ \/ _ \/ /__
- /_/ /_/ /_/ /___/\___/\___/
-
-a high performance and small footprint SoC based on Migen
-
-====== Building for: ======
-Platform: {}
-Target: {}
-Subtarget: {}
-CPU type: {}
-===========================""".format(platform_name, args.target, top_class.__name__, soc.cpu_type))
-
- # dependencies
- if actions["all"]:
- actions["clean"] = True
- actions["build-bitstream"] = True
- actions["build-bios"] = True
- if not actions["load-bitstream"]:
- actions["flash-bitstream"] = True
- if not soc.integrated_rom_size:
- actions["flash-bios"] = True
- if actions["build-bitstream"] and soc.integrated_rom_size:
- actions["build-bios"] = True
- if actions["build-bios"]:
- actions["build-headers"] = True
-
- if actions["clean"]:
- subprocess.check_call("rm -rvf build/*", shell=True) # Need shell for the build/* globbing
- subprocess.check_call(["make", "-C", os.path.join("software", "libcompiler-rt"), "clean"])
- subprocess.check_call(["make", "-C", os.path.join("software", "libbase"), "clean"])
- subprocess.check_call(["make", "-C", os.path.join("software", "libnet"), "clean"])
- subprocess.check_call(["make", "-C", os.path.join("software", "bios"), "clean"])
-
- if actions["build-headers"]:
- boilerplate = """/*
- * Platform: {}
- * Target: {}
- * Subtarget: {}
- * CPU type: {}
- */
-
-""".format(platform_name, args.target, top_class.__name__, soc.cpu_type)
- genhdir = os.path.join("software", "include", "generated")
- if soc.cpu_type != "none":
- cpu_mak = cpu_interface.get_cpu_mak(soc.cpu_type)
- write_to_file(os.path.join(genhdir, "cpu.mak"), cpu_mak)
- linker_output_format = cpu_interface.get_linker_output_format(soc.cpu_type)
- write_to_file(os.path.join(genhdir, "output_format.ld"), linker_output_format)
-
- linker_regions = cpu_interface.get_linker_regions(memory_regions)
- write_to_file(os.path.join(genhdir, "regions.ld"), boilerplate + linker_regions)
-
- for sdram_phy in ["sdrphy", "ddrphy"]:
- if hasattr(soc, sdram_phy):
- sdram_phy_header = sdram_init.get_sdram_phy_header(getattr(soc, sdram_phy).settings)
- write_to_file(os.path.join(genhdir, "sdram_phy.h"), boilerplate + sdram_phy_header)
- mem_header = cpu_interface.get_mem_header(memory_regions, getattr(soc, "flash_boot_address", None))
- write_to_file(os.path.join(genhdir, "mem.h"), boilerplate + mem_header)
- csr_header = cpu_interface.get_csr_header(csr_regions, sorted(soc.get_constants()))
- write_to_file(os.path.join(genhdir, "csr.h"), boilerplate + csr_header)
-
- if actions["build-csr-csv"]:
- csr_csv = cpu_interface.get_csr_csv(csr_regions)
- write_to_file(args.csr_csv, csr_csv)
-
- if actions["build-bios"]:
- ret = subprocess.call(["make", "-C", os.path.join("software", "bios")])
- if ret:
- raise OSError("BIOS build failed")
-
- bios_file = os.path.join("software", "bios", "bios.bin")
-
- if actions["build-bitstream"]:
- if soc.integrated_rom_size:
- with open(bios_file, "rb") as boot_file:
- boot_data = []
- while True:
- w = boot_file.read(4)
- if not w:
- break
- boot_data.append(struct.unpack(">I", w)[0])
- soc.init_rom(boot_data)
-
- for decorator in args.decorate:
- soc = getattr(simplify, decorator)(soc)
- build_kwargs = dict((k, autotype(v)) for k, v in args.build_option)
- vns = platform.build(soc, build_name=build_name, **build_kwargs)
- soc.do_exit(vns)
-
- if actions["load-bitstream"]:
- prog = platform.create_programmer()
- prog.load_bitstream(os.path.join("build", build_name + platform.bitstream_ext))
-
- if actions["flash-bitstream"]:
- prog = platform.create_programmer()
- prog.set_flash_proxy_dir(args.flash_proxy_dir)
- if prog.needs_bitreverse:
- flashbit = os.path.join("build", build_name + ".fpg")
- subprocess.check_call([os.path.join("tools", "byteswap"),
- os.path.join("build", build_name + ".bin"),
- flashbit])
- else:
- flashbit = os.path.join("build", build_name + ".bin")
- prog.flash(0, flashbit)
-
- if actions["flash-bios"]:
- prog = platform.create_programmer()
- prog.set_flash_proxy_dir(args.flash_proxy_dir)
- prog.flash(soc.cpu_reset_address, bios_file)
-import subprocess
-
from migen import *
from misoc.interconnect.csr import *
-def get_id():
- output = subprocess.check_output(["git", "rev-parse", "HEAD"]).decode("ascii")
- return int(output[:8], 16)
-
-
class Identifier(Module, AutoCSR):
def __init__(self, sysid, frequency, revision=None):
self._sysid = CSRStatus(16)
- self._revision = CSRStatus(32)
self._frequency = CSRStatus(32)
###
- if revision is None:
- revision = get_id()
-
self.comb += [
self._sysid.status.eq(sysid),
- self._revision.status.eq(revision),
self._frequency.status.eq(frequency)
]
--- /dev/null
+import os
+import subprocess
+import struct
+
+from misoc.integration import cpu_interface, sdram_init
+
+
+# in build order (for dependencies)
+misoc_software_packages = [
+ "libbase",
+ "libcompiler_rt",
+ "libdyld",
+ "libnet",
+ "libunwind",
+ "bios"
+]
+
+
+misoc_directory = os.path.abspath(os.path.join(os.path.dirname(__file__), ".."))
+
+
+class Builder:
+ def __init__(self, soc, output_dir):
+ self.soc = soc
+ # From Python doc: makedirs() will become confused if the path
+ # elements to create include '..'
+ self.output_dir = os.path.abspath(output_dir)
+
+ self.software_packages = []
+ for name in misoc_software_packages:
+ self.add_software_package(
+ name, os.path.join(misoc_directory, "software", name))
+
+ def add_software_package(self, name, src_dir):
+ self.software_packages.append((name, src_dir))
+
+ def _generate_includes(self):
+ cpu_type = self.soc.cpu_type
+ memory_regions = self.soc.get_memory_regions()
+ flash_boot_address = getattr(self.soc, "flash_boot_address", None)
+ csr_regions = self.soc.get_csr_regions()
+ constants = self.soc.get_constants()
+ # TODO: cleanup
+ sdram_phy_settings = None
+ for sdram_phy in "sdrphy", "ddrphy":
+ if hasattr(self.soc, sdram_phy):
+ sdram_phy_settings = getattr(self.soc, sdram_phy).settings
+
+ buildinc_dir = os.path.join(self.output_dir, "software", "include")
+ generated_dir = os.path.join(buildinc_dir, "generated")
+ os.makedirs(generated_dir, exist_ok=True)
+ with open(os.path.join(generated_dir, "variables.mak"), "w") as f:
+ def define(k, v):
+ f.write("{}={}\n".format(k, v))
+ for k, v in cpu_interface.get_cpu_mak(cpu_type):
+ define(k, v)
+ define("MISOC_DIRECTORY", misoc_directory)
+ define("BUILDINC_DIRECTORY", buildinc_dir)
+ for name, src_dir in self.software_packages:
+ define(name.upper() + "_DIRECTORY", src_dir)
+
+ with open(os.path.join(generated_dir, "output_format.ld"), "w") as f:
+ f.write(cpu_interface.get_linker_output_format(cpu_type))
+ with open(os.path.join(generated_dir, "regions.ld"), "w") as f:
+ f.write(cpu_interface.get_linker_regions(memory_regions))
+
+ with open(os.path.join(generated_dir, "mem.h"), "w") as f:
+ f.write(cpu_interface.get_mem_header(memory_regions, flash_boot_address))
+ with open(os.path.join(generated_dir, "csr.h"), "w") as f:
+ f.write(cpu_interface.get_csr_header(csr_regions, constants))
+
+ if sdram_phy_settings is not None:
+ with open(os.path.join(generated_dir, "sdram_phy.h"), "w") as f:
+ f.write(sdram_init.get_sdram_phy_header(sdram_phy_settings))
+
+ def _generate_software(self, compile):
+ for name, src_dir in self.software_packages:
+ dst_dir = os.path.join(self.output_dir, "software", name)
+ os.makedirs(dst_dir, exist_ok=True)
+ src = os.path.join(src_dir, "Makefile")
+ dst = os.path.join(dst_dir, "Makefile")
+ try:
+ os.remove(dst)
+ except FileNotFoundError:
+ pass
+ os.symlink(src, dst)
+ if compile:
+ subprocess.check_call(["make", "-C", dst_dir])
+
+ def _initialize_rom(self):
+ bios_file = os.path.join(self.output_dir, "software" "bios",
+ "bios.bin")
+ if self.soc.integrated_rom_size:
+ with open(bios_file, "rb") as boot_file:
+ boot_data = []
+ while True:
+ w = boot_file.read(4)
+ if not w:
+ break
+ boot_data.append(struct.unpack(">I", w)[0])
+ self.soc.initialize_rom(boot_data)
+
+ def build(self, compile_software=True, compile_gateware=True):
+ self.soc.finalize()
+
+ if self.soc.integrated_rom_size and not compile_software:
+ raise ValueError("Software must be compiled in order to "
+ "intitialize integrated ROM")
+
+ self._generate_includes()
+ self._generate_software(compile_software)
+ self._initialize_rom()
+ self.soc.build(build_dir=os.path.join(self.output_dir, "gateware"),
+ run=compile_gateware)
from misoc.interconnect.csr import CSRStatus
-def get_cpu_mak(cpu_type):
- if cpu_type == "lm32":
+def get_cpu_mak(cpu):
+ if cpu == "lm32":
triple = "lm32-elf"
cpuflags = "-mbarrel-shift-enabled -mmultiply-enabled -mdivide-enabled -msign-extend-enabled"
clang = ""
- elif cpu_type == "or1k":
+ elif cpu == "or1k":
triple = "or1k-linux"
cpuflags = "-mhard-mul -mhard-div -mror -mffl1 -maddc"
clang = "1"
else:
- raise ValueError("Unsupported CPU type: "+cpu_type)
- return "TRIPLE={}\nCPU={}\nCPUFLAGS={}\nCLANG={}".format(triple, cpu_type, cpuflags, clang)
+ raise ValueError("Unsupported CPU type: "+cpu)
+ return [
+ ("TRIPLE", triple),
+ ("CPU", cpu),
+ ("CPUFLAGS", cpuflags),
+ ("CLANG", clang)
+ ]
def get_linker_output_format(cpu_type):
raise NotImplementedError("More than one CPU is not supported")
self.submodules.cpu_or_bridge = cpu_or_bridge
- def init_rom(self, data):
+ def initialize_rom(self, data):
self.rom.mem.init = data
def add_wb_master(self, wbm):
for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
if hasattr(self, k):
self.comb += self.cpu_or_bridge.interrupt[v].eq(getattr(self, k).ev.irq)
+
+ def build(self, *args, **kwargs):
+ self.platform.build(self, *args, **kwargs)
-MSCDIR=../..
-include $(MSCDIR)/software/common.mak
+include ../include/generated/variables.mak
+include $(MISOC_DIRECTORY)/software/common.mak
OBJECTS=isr.o sdram.o main.o boot-helper-$(CPU).o boot.o dataflow.o
%.bin: %.elf
$(OBJCOPY) -O binary $< $@
chmod -x $@
- $(MSCDIR)/mkmscimg.py $@
+ $(PYTHON) -m misoc.tools.mkmscimg $@
-bios.elf: linker.ld $(OBJECTS) libs
+bios.elf: $(BIOS_DIRECTORY)/linker.ld $(OBJECTS)
%.elf:
$(LD) $(LDFLAGS) -T $< -N -o $@ \
- $(MSCDIR)/software/libbase/crt0-$(CPU).o \
+ ../libbase/crt0-$(CPU).o \
$(OBJECTS) \
- -L$(MSCDIR)/software/libnet \
- -L$(MSCDIR)/software/libbase \
- -L$(MSCDIR)/software/libcompiler-rt \
- -lnet -lbase-nofloat -lcompiler-rt
+ -L../libnet \
+ -L../libbase \
+ -L../libcompiler_rt \
+ -lnet -lbase-nofloat -lcompiler_rt
chmod -x $@
-main.o: main.c
+main.o: $(BIOS_DIRECTORY)/main.c
$(compile-dep)
-%.o: %.c
+%.o: $(BIOS_DIRECTORY)/%.c
$(compile-dep)
-%.o: %.S
+%.o: $(BIOS_DIRECTORY)/%.S
$(assemble)
-libs:
- $(MAKE) -C $(MSCDIR)/software/libcompiler-rt
- $(MAKE) -C $(MSCDIR)/software/libbase
- $(MAKE) -C $(MSCDIR)/software/libnet
-
clean:
$(RM) $(OBJECTS) $(OBJECTS:.o=.d) bios.elf bios.bin .*~ *~
-.PHONY: all main.o clean libs
+.PHONY: all main.o clean
else if(strcmp(token, "netboot") == 0) netboot();
#endif
- else if(strcmp(token, "revision") == 0) printf("%08x\n", MSC_GIT_ID);
-
else if(strcmp(token, "help") == 0) help();
#ifdef __lm32__
irq_setmask(0);
irq_setie(1);
uart_init();
- puts("\nMiSoC BIOS http://m-labs.hk\n"
- "(c) Copyright 2007-2014 Sebastien Bourdeauducq");
- printf("Revision %08x built "__DATE__" "__TIME__"\n\n", MSC_GIT_ID);
+ puts("\nMiSoC BIOS\n"
+ "(c) Copyright 2007-2015 M-Labs Limited\n"
+ "Built "__DATE__" "__TIME__"\n");
crcbios();
id_print();
#ifdef CSR_ETHMAC_BASE
-include $(MSCDIR)/software/include/generated/cpu.mak
TARGET_PREFIX=$(TRIPLE)-
RM ?= rm -f
LD_quiet = @echo " LD " $@ && $(LD_normal)
OBJCOPY_quiet = @echo " OBJCOPY " $@ && $(OBJCOPY_normal)
-MSC_GIT_ID := $(shell cd $(MSCDIR) && $(PYTHON) -c "from misoc.cores.identifier import get_id; print(hex(get_id()), end='')")
-
ifeq ($(V),1)
CC = $(CC_normal)
CX = $(CX_normal)
# Toolchain options
#
-INCLUDES = -I$(MSCDIR)/software/include/base -I$(MSCDIR)/software/include -I$(MSCDIR)/common
-COMMONFLAGS = -Os $(CPUFLAGS) -fomit-frame-pointer -Wall -fno-builtin -nostdinc -DMSC_GIT_ID=$(MSC_GIT_ID) $(INCLUDES)
+INCLUDES = -I$(MISOC_DIRECTORY)/software/include/base -I$(MISOC_DIRECTORY)/software/include -I$(MISOC_DIRECTORY)/common -I$(BUILDINC_DIRECTORY)
+COMMONFLAGS = -Os $(CPUFLAGS) -fomit-frame-pointer -Wall -fno-builtin -nostdinc $(INCLUDES)
CFLAGS = $(COMMONFLAGS) -fexceptions -Wstrict-prototypes -Wold-style-definition -Wmissing-prototypes
-CXXFLAGS = $(COMMONFLAGS) -std=c++11 -I$(MSCDIR)/software/include/basec++ -fexceptions -fno-rtti -ffreestanding
-LDFLAGS = -nostdlib -nodefaultlibs -L$(MSCDIR)/software/include
+CXXFLAGS = $(COMMONFLAGS) -std=c++11 -I$(MISOC_DIRECTORY)/software/include/basec++ -fexceptions -fno-rtti -ffreestanding
+LDFLAGS = -nostdlib -nodefaultlibs -L$(BUILDINC_DIRECTORY)
# compile and generate dependencies, based on
# http://scottmcpeak.com/autodepend/autodepend.html
+++ /dev/null
-Subproject commit a1448787a069603414e716adc8a41f866e28a4b4
--- /dev/null
+Subproject commit a1448787a069603414e716adc8a41f866e28a4b4
-MSCDIR=../..
-include $(MSCDIR)/software/common.mak
+include ../include/generated/variables.mak
+include $(MISOC_DIRECTORY)/software/common.mak
OBJECTS=exception.o libc.o errno.o crc16.o crc32.o console.o system.o id.o uart.o time.o qsort.o strtod.o spiflash.o
libbase-nofloat.a: $(OBJECTS) vsnprintf-nofloat.o
$(AR) crs libbase-nofloat.a $(OBJECTS) vsnprintf-nofloat.o
-vsnprintf-nofloat.o: vsnprintf.c
+vsnprintf-nofloat.o: $(LIBBASE_DIRECTORY)/vsnprintf.c
$(call compile-dep,-DNO_FLOAT)
-%.o: %.c
+%.o: $(LIBBASE_DIRECTORY)/%.c
$(compile-dep)
-%.o: %.S
+%.o: $(LIBBASE_DIRECTORY)/%.S
$(assemble)
.PHONY: clean
char sysid[3];
get_sysid_formatted(sysid);
- printf("Running on MiSoC rev. %08x (sysid:%s) at %dMHz\n", identifier_revision_read(), sysid, identifier_frequency_read()/1000000);
+ printf("Running on MiSoC (sysid:%s) at %dMHz\n", sysid, identifier_frequency_read()/1000000);
}
+++ /dev/null
-MSCDIR=../..
-include $(MSCDIR)/software/common.mak
-
-CFLAGS+=-D_YUGA_LITTLE_ENDIAN=0 -D_YUGA_BIG_ENDIAN=1 -Wno-missing-prototypes
-
-OBJECTS=divsi3.o modsi3.o comparedf2.o negsf2.o negdf2.o addsf3.o subsf3.o mulsf3.o divsf3.o lshrdi3.o muldi3.o divdi3.o ashldi3.o ashrdi3.o udivmoddi4.o \
- floatsisf.o floatunsisf.o fixsfsi.o fixdfdi.o fixunssfsi.o adddf3.o subdf3.o muldf3.o divdf3.o floatsidf.o floatunsidf.o floatdidf.o fixdfsi.o fixunsdfsi.o \
- clzsi2.o ctzsi2.o udivdi3.o umoddi3.o moddi3.o ucmpdi2.o
-
-all: libcompiler-rt.a
-
-# pull in dependency info for *existing* .o files
--include $(OBJECTS:.o=.d)
-
-libcompiler-rt.a: $(OBJECTS)
- $(AR) crs libcompiler-rt.a $(OBJECTS)
-
-%.o: $(MSCDIR)/software/compiler-rt/lib/builtins/%.c
- $(compile-dep)
-
-.PHONY: clean
-
-clean:
- $(RM) $(OBJECTS) $(OBJECTS:.o=.ts) $(OBJECTS:.o=.d) libcompiler-rt.a .*~ *~
--- /dev/null
+include ../include/generated/variables.mak
+include $(MISOC_DIRECTORY)/software/common.mak
+
+CFLAGS+=-D_YUGA_LITTLE_ENDIAN=0 -D_YUGA_BIG_ENDIAN=1 -Wno-missing-prototypes
+
+OBJECTS=divsi3.o modsi3.o comparedf2.o negsf2.o negdf2.o addsf3.o subsf3.o mulsf3.o divsf3.o lshrdi3.o muldi3.o divdi3.o ashldi3.o ashrdi3.o udivmoddi4.o \
+ floatsisf.o floatunsisf.o fixsfsi.o fixdfdi.o fixunssfsi.o adddf3.o subdf3.o muldf3.o divdf3.o floatsidf.o floatunsidf.o floatdidf.o fixdfsi.o fixunsdfsi.o \
+ clzsi2.o ctzsi2.o udivdi3.o umoddi3.o moddi3.o ucmpdi2.o
+
+all: libcompiler_rt.a
+
+# pull in dependency info for *existing* .o files
+-include $(OBJECTS:.o=.d)
+
+libcompiler_rt.a: $(OBJECTS)
+ $(AR) crs libcompiler_rt.a $(OBJECTS)
+
+%.o: $(MISOC_DIRECTORY)/software/compiler_rt/lib/builtins/%.c
+ $(compile-dep)
+
+.PHONY: clean
+
+clean:
+ $(RM) $(OBJECTS) $(OBJECTS:.o=.ts) $(OBJECTS:.o=.d) libcompiler_rt.a .*~ *~
-MSCDIR=../..
-include $(MSCDIR)/software/common.mak
+include ../include/generated/variables.mak
+include $(MISOC_DIRECTORY)/software/common.mak
-COMMONFLAGS += -I$(MSCDIR)/software/include/dyld
+COMMONFLAGS += -I$(MISOC_DIRECTORY)/software/include/dyld
OBJECTS=dyld.o
libdyld.a: $(OBJECTS)
$(AR) crs libdyld.a $(OBJECTS)
+%.o: $(LIBDYLD_DIRECTORY)/%.c
+ $(compile-dep)
+
.PHONY: clean
clean:
-MSCDIR=../..
-include $(MSCDIR)/software/common.mak
+include ../include/generated/variables.mak
+include $(MISOC_DIRECTORY)/software/common.mak
OBJECTS=microudp.o tftp.o
libnet.a: $(OBJECTS)
$(AR) crs libnet.a $(OBJECTS)
-%.o: %.c
+%.o: $(LIBNET_DIRECTORY)/%.c
$(compile-dep)
%.o: %.S
-MSCDIR=../..
-include $(MSCDIR)/software/common.mak
+include ../include/generated/variables.mak
+include $(MISOC_DIRECTORY)/software/common.mak
COMMONFLAGS+=-integrated-as \
- -I. -I$(MSCDIR)/software/include/dyld/ -I$(MSCDIR)/software/unwinder/include/ \
+ -I. -I$(MISOC_DIRECTORY)/software/include/dyld/ -I$(MISOC_DIRECTORY)/software/unwinder/include/ \
+ -I$(LIBUNWIND_DIRECTORY) \
-D__ELF__ -D__linux__ -D_LIBUNWIND_NO_HEAP -DNDEBUG
OBJECTS=UnwindRegistersSave.o UnwindRegistersRestore.o UnwindLevel1.o libunwind.o
libunwind.a: $(OBJECTS)
$(AR) crs libunwind.a $(OBJECTS)
-%.o: $(MSCDIR)/software/unwinder/src/%.cpp
+%.o: $(MISOC_DIRECTORY)/software/unwinder/src/%.cpp
$(compilexx-dep)
-%.o: $(MSCDIR)/software/unwinder/src/%.c
+%.o: $(MISOC_DIRECTORY)/software/unwinder/src/%.c
$(compile-dep)
-%.o: $(MSCDIR)/software/unwinder/src/%.S
+%.o: $(MISOC_DIRECTORY)/software/unwinder/src/%.S
$(assemble)
.PHONY: clean
clean:
- $(RM) $(OBJECTS) $(OBJECTS:.o=.ts) $(OBJECTS:.o=.d) libuwind.a .*~ *~
+ $(RM) $(OBJECTS) $(OBJECTS:.o=.ts) $(OBJECTS:.o=.d) libunwind.a .*~ *~
--- /dev/null
+from migen import *
+
+from misoc.cores.sdram_settings import IS42S16160
+from misoc.cores.sdram_phy import GENSDRPHY
+from misoc.cores.lasmicon.core import LASMIconSettings
+from misoc.integration.soc_sdram import SoCSDRAM
+
+
+class _PLL(Module):
+ def __init__(self, period_in, name, phase_shift, operation_mode):
+ self.clk_in = Signal()
+ self.clk_out = Signal()
+
+ self.specials += Instance("ALTPLL",
+ p_bandwidth_type = "AUTO",
+ p_clk0_divide_by = 1,
+ p_clk0_duty_cycle = 50,
+ p_clk0_multiply_by = 2,
+ p_clk0_phase_shift = "{}".format(str(phase_shift)),
+ p_compensate_clock = "CLK0",
+ p_inclk0_input_frequency = int(period_in*1000),
+ p_intended_device_family = "Cyclone IV E",
+ p_lpm_hint = "CBX_MODULE_PREFIX={}_pll".format(name),
+ p_lpm_type = "altpll",
+ p_operation_mode = operation_mode,
+ i_inclk=self.clk_in,
+ o_clk=self.clk_out,
+ i_areset=0,
+ i_clkena=0x3f,
+ i_clkswitch=0,
+ i_configupdate=0,
+ i_extclkena=0xf,
+ i_fbin=1,
+ i_pfdena=1,
+ i_phasecounterselect=0xf,
+ i_phasestep=1,
+ i_phaseupdown=1,
+ i_pllena=1,
+ i_scanaclr=0,
+ i_scanclk=0,
+ i_scanclkena=1,
+ i_scandata=0,
+ i_scanread=0,
+ i_scanwrite=0
+ )
+
+
+class _CRG(Module):
+ def __init__(self, platform):
+ self.clock_domains.cd_sys = ClockDomain()
+ self.clock_domains.cd_sys_ps = ClockDomain()
+ self.clock_domains.cd_por = ClockDomain(reset_less=True)
+
+ clk50 = platform.request("clk50")
+
+ sys_pll = _PLL(20, "sys", 0, "NORMAL")
+ self.submodules += sys_pll
+ self.comb += [
+ sys_pll.clk_in.eq(clk50),
+ self.cd_sys.clk.eq(sys_pll.clk_out)
+ ]
+
+ sdram_pll = _PLL(20, "sdram", -3000, "ZERO_DELAY_BUFFER")
+ self.submodules += sdram_pll
+ self.comb += [
+ sdram_pll.clk_in.eq(clk50),
+ self.cd_sys_ps.clk.eq(sdram_pll.clk_out)
+ ]
+
+ # Power on Reset (vendor agnostic)
+ rst_n = Signal()
+ self.sync.por += rst_n.eq(1)
+ self.comb += [
+ self.cd_por.clk.eq(self.cd_sys.clk),
+ self.cd_sys.rst.eq(~rst_n),
+ self.cd_sys_ps.rst.eq(~rst_n)
+ ]
+
+ self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
+
+
+class BaseSoC(SoCSDRAM):
+ default_platform = "de0nano"
+
+ def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
+ SoCSDRAM.__init__(self, platform,
+ clk_freq=100*1000000,
+ integrated_rom_size=0x8000,
+ sdram_controller_settings=sdram_controller_settings,
+ **kwargs)
+
+ self.submodules.crg = _CRG(platform)
+
+ if not self.integrated_main_ram_size:
+ self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),
+ IS42S16160(self.clk_freq))
+ self.register_sdram_phy(self.sdrphy)
+
+default_subtarget = BaseSoC
--- /dev/null
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from misoc.cores.sdram_settings import MT8JTF12864
+from misoc.cores.sdram_phy import k7ddrphy
+from misoc.cores.lasmicon.core import LASMIconSettings
+from misoc.cores import spi_flash
+from misoc.cores.liteeth_mini.phy import LiteEthPHY
+from misoc.cores.liteeth_mini.mac import LiteEthMAC
+from misoc.integration.soc_core import mem_decoder
+from misoc.integration.soc_sdram import SoCSDRAM
+
+
+class _CRG(Module):
+ def __init__(self, platform):
+ self.clock_domains.cd_sys = ClockDomain()
+ self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
+ self.clock_domains.cd_clk200 = ClockDomain()
+
+ clk200 = platform.request("clk200")
+ clk200_se = Signal()
+ self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)
+
+ rst = platform.request("cpu_reset")
+
+ pll_locked = Signal()
+ pll_fb = Signal()
+ self.pll_sys = Signal()
+ pll_sys4x = Signal()
+ pll_clk200 = Signal()
+ self.specials += [
+ Instance("PLLE2_BASE",
+ p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
+
+ # VCO @ 1GHz
+ p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
+ p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
+ i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
+
+ # 125MHz
+ p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=self.pll_sys,
+
+ # 500MHz
+ p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_sys4x,
+
+ # 200MHz
+ p_CLKOUT2_DIVIDE=5, p_CLKOUT2_PHASE=0.0, o_CLKOUT2=pll_clk200,
+
+ p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
+
+ p_CLKOUT4_DIVIDE=4, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
+ ),
+ Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk),
+ Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
+ Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
+ AsyncResetSynchronizer(self.cd_sys, ~pll_locked | rst),
+ AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | rst),
+ ]
+
+ reset_counter = Signal(4, reset=15)
+ ic_reset = Signal(reset=1)
+ self.sync.clk200 += \
+ If(reset_counter != 0,
+ reset_counter.eq(reset_counter - 1)
+ ).Else(
+ ic_reset.eq(0)
+ )
+ self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
+
+
+class BaseSoC(SoCSDRAM):
+ default_platform = "kc705"
+
+ csr_map = {
+ "spiflash": 16,
+ "ddrphy": 17,
+ }
+ csr_map.update(SoCSDRAM.csr_map)
+
+ def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
+ SoCSDRAM.__init__(self, platform,
+ clk_freq=125*1000000, cpu_reset_address=0xaf0000,
+ sdram_controller_settings=sdram_controller_settings,
+ **kwargs)
+
+ self.submodules.crg = _CRG(platform)
+
+ if not self.integrated_main_ram_size:
+ self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"),
+ MT8JTF12864(self.clk_freq))
+ self.register_sdram_phy(self.ddrphy)
+
+ if not self.integrated_rom_size:
+ spiflash_pads = platform.request("spiflash")
+ spiflash_pads.clk = Signal()
+ self.specials += Instance("STARTUPE2",
+ i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
+ i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
+ self.submodules.spiflash = spi_flash.SpiFlash(spiflash_pads, dummy=11, div=2)
+ self.add_constant("SPIFLASH_PAGE_SIZE", 256)
+ self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
+ self.flash_boot_address = 0xb00000
+ self.register_rom(self.spiflash.bus)
+
+
+class MiniSoC(BaseSoC):
+ csr_map = {
+ "ethphy": 18,
+ "ethmac": 19,
+ }
+ csr_map.update(BaseSoC.csr_map)
+
+ interrupt_map = {
+ "ethmac": 2,
+ }
+ interrupt_map.update(BaseSoC.interrupt_map)
+
+ mem_map = {
+ "ethmac": 0x30000000, # (shadow @0xb0000000)
+ }
+ mem_map.update(BaseSoC.mem_map)
+
+ def __init__(self, platform, **kwargs):
+ BaseSoC.__init__(self, platform, **kwargs)
+
+ self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"), clk_freq=self.clk_freq)
+ self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
+ self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
+ self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
+
+default_subtarget = BaseSoC
--- /dev/null
+from fractions import Fraction
+
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from misoc.cores.sdram_settings import AS4C16M16
+from misoc.cores.sdram_phy import GENSDRPHY
+from misoc.cores.lasmicon.core import LASMIconSettings
+from misoc.integration.soc_sdram import SoCSDRAM
+
+
+class _CRG(Module):
+ def __init__(self, platform, clk_freq):
+ self.clock_domains.cd_sys = ClockDomain()
+ self.clock_domains.cd_sys_ps = ClockDomain()
+
+ f0 = 32*1000000
+ clk32 = platform.request("clk32")
+ clk32a = Signal()
+ self.specials += Instance("IBUFG", i_I=clk32, o_O=clk32a)
+ clk32b = Signal()
+ self.specials += Instance("BUFIO2", p_DIVIDE=1,
+ p_DIVIDE_BYPASS="TRUE", p_I_INVERT="FALSE",
+ i_I=clk32a, o_DIVCLK=clk32b)
+ f = Fraction(int(clk_freq), int(f0))
+ n, m, p = f.denominator, f.numerator, 8
+ assert f0/n*m == clk_freq
+ pll_lckd = Signal()
+ pll_fb = Signal()
+ pll = Signal(6)
+ self.specials.pll = Instance("PLL_ADV", p_SIM_DEVICE="SPARTAN6",
+ p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
+ p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
+ i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
+ p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
+ i_CLKIN1=clk32b, i_CLKIN2=0, i_CLKINSEL=1,
+ p_CLKIN1_PERIOD=1000000000/f0, p_CLKIN2_PERIOD=0.,
+ i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
+ o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
+ o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
+ o_CLKOUT2=pll[2], p_CLKOUT2_DUTY_CYCLE=.5,
+ o_CLKOUT3=pll[3], p_CLKOUT3_DUTY_CYCLE=.5,
+ o_CLKOUT4=pll[4], p_CLKOUT4_DUTY_CYCLE=.5,
+ o_CLKOUT5=pll[5], p_CLKOUT5_DUTY_CYCLE=.5,
+ p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//1,
+ p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//1,
+ p_CLKOUT2_PHASE=0., p_CLKOUT2_DIVIDE=p//1,
+ p_CLKOUT3_PHASE=0., p_CLKOUT3_DIVIDE=p//1,
+ p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1, # sys
+ p_CLKOUT5_PHASE=270., p_CLKOUT5_DIVIDE=p//1, # sys_ps
+ )
+ self.specials += Instance("BUFG", i_I=pll[4], o_O=self.cd_sys.clk)
+ self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys_ps.clk)
+ self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd)
+
+ self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
+ p_INIT=0, p_SRTYPE="SYNC",
+ i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
+ i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk,
+ o_Q=platform.request("sdram_clock"))
+
+
+class BaseSoC(SoCSDRAM):
+ default_platform = "minispartan6"
+
+ def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
+ clk_freq = 80*1000000
+ SoCSDRAM.__init__(self, platform, clk_freq,
+ integrated_rom_size=0x8000,
+ sdram_controller_settings=sdram_controller_settings,
+ **kwargs)
+
+ self.submodules.crg = _CRG(platform, clk_freq)
+
+ if not self.integrated_main_ram_size:
+ self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),
+ AS4C16M16(clk_freq))
+ self.register_sdram_phy(self.sdrphy)
+
+default_subtarget = BaseSoC
--- /dev/null
+import os
+from fractions import Fraction
+from math import ceil
+
+from migen import *
+from migen.build.generic_platform import ConstraintError
+
+from misoc.cores.sdram_settings import MT46V32M16
+from misoc.cores.sdram_phy import S6HalfRateDDRPHY
+from misoc.cores.lasmicon.core import LASMIconSettings
+from misoc.cores import nor_flash_16
+from misoc.cores import framebuffer
+from misoc.cores import gpio
+from misoc.cores.liteeth_mini.phy import LiteEthPHY
+from misoc.cores.liteeth_mini.mac import LiteEthMAC
+from misoc.integration.soc_core import mem_decoder
+from misoc.integration.soc_sdram import SoCSDRAM
+
+
+class _MXCRG(Module):
+ def __init__(self, pads, outfreq1x):
+ self.clock_domains.cd_sys = ClockDomain()
+ self.clock_domains.cd_sdram_half = ClockDomain()
+ self.clock_domains.cd_sdram_full_wr = ClockDomain()
+ self.clock_domains.cd_sdram_full_rd = ClockDomain()
+ self.clock_domains.cd_base50 = ClockDomain(reset_less=True)
+
+ self.clk4x_wr_strb = Signal()
+ self.clk4x_rd_strb = Signal()
+
+ ###
+
+ infreq = 50*1000000
+ ratio = Fraction(outfreq1x)/Fraction(infreq)
+ in_period = float(Fraction(1000000000)/Fraction(infreq))
+
+ self.specials += Instance("mxcrg",
+ Instance.Parameter("in_period", in_period),
+ Instance.Parameter("f_mult", ratio.numerator),
+ Instance.Parameter("f_div", ratio.denominator),
+ Instance.Input("clk50_pad", pads.clk50),
+ Instance.Input("trigger_reset", pads.trigger_reset),
+
+ Instance.Output("sys_clk", self.cd_sys.clk),
+ Instance.Output("sys_rst", self.cd_sys.rst),
+ Instance.Output("clk2x_270", self.cd_sdram_half.clk),
+ Instance.Output("clk4x_wr", self.cd_sdram_full_wr.clk),
+ Instance.Output("clk4x_rd", self.cd_sdram_full_rd.clk),
+ Instance.Output("base50_clk", self.cd_base50.clk),
+
+ Instance.Output("clk4x_wr_strb", self.clk4x_wr_strb),
+ Instance.Output("clk4x_rd_strb", self.clk4x_rd_strb),
+ Instance.Output("norflash_rst_n", pads.norflash_rst_n),
+ Instance.Output("ddr_clk_pad_p", pads.ddr_clk_p),
+ Instance.Output("ddr_clk_pad_n", pads.ddr_clk_n))
+
+
+class _MXClockPads:
+ def __init__(self, platform):
+ self.clk50 = platform.request("clk50")
+ self.trigger_reset = 0
+ try:
+ self.trigger_reset = platform.request("user_btn", 1)
+ except ConstraintError:
+ pass
+ self.norflash_rst_n = platform.request("norflash_rst_n")
+ ddram_clock = platform.request("ddram_clock")
+ self.ddr_clk_p = ddram_clock.p
+ self.ddr_clk_n = ddram_clock.n
+
+
+class BaseSoC(SoCSDRAM):
+ default_platform = "mixxeo" # also supports m1
+
+ def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
+ SoCSDRAM.__init__(self, platform,
+ clk_freq=(83 + Fraction(1, 3))*1000000,
+ cpu_reset_address=0x00180000,
+ sdram_controller_settings=sdram_controller_settings,
+ **kwargs)
+
+ self.submodules.crg = _MXCRG(_MXClockPads(platform), self.clk_freq)
+
+ if not self.integrated_main_ram_size:
+ self.submodules.ddrphy = S6HalfRateDDRPHY(platform.request("ddram"),
+ MT46V32M16(self.clk_freq),
+ rd_bitslip=0,
+ wr_bitslip=3,
+ dqs_ddr_alignment="C1")
+ self.register_sdram_phy(self.ddrphy)
+ self.comb += [
+ self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
+ self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
+ ]
+
+ if not self.integrated_rom_size:
+ clk_period_ns = 1000000000/self.clk_freq
+ self.submodules.norflash = nor_flash_16.NorFlash16(
+ platform.request("norflash"),
+ ceil(110/clk_period_ns), ceil(50/clk_period_ns))
+ self.flash_boot_address = 0x001a0000
+ self.register_rom(self.norflash.bus)
+
+ platform.add_platform_command("""
+INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
+INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";
+""")
+ platform.add_source(os.path.join("misoc", "mxcrg.v"))
+
+
+class MiniSoC(BaseSoC):
+ csr_map = {
+ "ethphy": 16,
+ "ethmac": 17,
+ }
+ csr_map.update(BaseSoC.csr_map)
+
+ interrupt_map = {
+ "ethmac": 2,
+ }
+ interrupt_map.update(BaseSoC.interrupt_map)
+
+ mem_map = {
+ "ethmac": 0x30000000, # (shadow @0xb0000000)
+ }
+ mem_map.update(BaseSoC.mem_map)
+
+ def __init__(self, platform, **kwargs):
+ BaseSoC.__init__(self, platform, **kwargs)
+
+ if platform.name == "mixxeo":
+ self.submodules.leds = gpio.GPIOOut(platform.request("user_led"))
+ if platform.name == "m1":
+ self.submodules.buttons = gpio.GPIOIn(Cat(platform.request("user_btn", 0),
+ platform.request("user_btn", 2)))
+ self.submodules.leds = gpio.GPIOOut(Cat(platform.request("user_led", i) for i in range(2)))
+
+ self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),
+ platform.request("eth"))
+ self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
+ self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
+ self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
+
+
+def get_vga_dvi(platform):
+ try:
+ pads_vga = platform.request("vga_out")
+ except ConstraintError:
+ pads_vga = None
+ try:
+ pads_dvi = platform.request("dvi_out")
+ except ConstraintError:
+ pads_dvi = None
+ else:
+ platform.add_platform_command("""
+PIN "dviout_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;
+""")
+ return pads_vga, pads_dvi
+
+
+def add_vga_tig(platform, fb):
+ platform.add_platform_command("""
+NET "{vga_clk}" TNM_NET = "GRPvga_clk";
+NET "sys_clk" TNM_NET = "GRPsys_clk";
+TIMESPEC "TSise_sucks1" = FROM "GRPvga_clk" TO "GRPsys_clk" TIG;
+TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
+""", vga_clk=fb.driver.clocking.cd_pix.clk)
+
+
+class FramebufferSoC(MiniSoC):
+ csr_map = {
+ "fb": 18,
+ }
+ csr_map.update(MiniSoC.csr_map)
+
+ def __init__(self, platform, **kwargs):
+ MiniSoC.__init__(self, platform, **kwargs)
+ pads_vga, pads_dvi = get_vga_dvi(platform)
+ self.submodules.fb = framebuffer.Framebuffer(pads_vga, pads_dvi,
+ self.sdram.crossbar.get_master())
+ add_vga_tig(platform, self.fb)
+
+default_subtarget = FramebufferSoC
--- /dev/null
+#!/usr/bin/env python3
+
+from fractions import Fraction
+
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+from migen.build.platforms import papilio_pro
+
+from misoc.cores.sdram_settings import MT48LC4M16
+from misoc.cores.sdram_phy import GENSDRPHY
+from misoc.cores.lasmicon.core import LASMIconSettings
+from misoc.cores import spi_flash
+from misoc.integration.soc_sdram import SoCSDRAM
+from misoc.integration.builder import Builder
+
+
+class _CRG(Module):
+ def __init__(self, platform, clk_freq):
+ self.clock_domains.cd_sys = ClockDomain()
+ self.clock_domains.cd_sys_ps = ClockDomain()
+
+ f0 = 32*1000000
+ clk32 = platform.request("clk32")
+ clk32a = Signal()
+ self.specials += Instance("IBUFG", i_I=clk32, o_O=clk32a)
+ clk32b = Signal()
+ self.specials += Instance("BUFIO2", p_DIVIDE=1,
+ p_DIVIDE_BYPASS="TRUE", p_I_INVERT="FALSE",
+ i_I=clk32a, o_DIVCLK=clk32b)
+ f = Fraction(int(clk_freq), int(f0))
+ n, m, p = f.denominator, f.numerator, 8
+ assert f0/n*m == clk_freq
+ pll_lckd = Signal()
+ pll_fb = Signal()
+ pll = Signal(6)
+ self.specials.pll = Instance("PLL_ADV", p_SIM_DEVICE="SPARTAN6",
+ p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
+ p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
+ i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
+ p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
+ i_CLKIN1=clk32b, i_CLKIN2=0, i_CLKINSEL=1,
+ p_CLKIN1_PERIOD=1000000000/f0, p_CLKIN2_PERIOD=0.,
+ i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
+ o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
+ o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
+ o_CLKOUT2=pll[2], p_CLKOUT2_DUTY_CYCLE=.5,
+ o_CLKOUT3=pll[3], p_CLKOUT3_DUTY_CYCLE=.5,
+ o_CLKOUT4=pll[4], p_CLKOUT4_DUTY_CYCLE=.5,
+ o_CLKOUT5=pll[5], p_CLKOUT5_DUTY_CYCLE=.5,
+ p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//1,
+ p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//1,
+ p_CLKOUT2_PHASE=0., p_CLKOUT2_DIVIDE=p//1,
+ p_CLKOUT3_PHASE=0., p_CLKOUT3_DIVIDE=p//1,
+ p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1, # sys
+ p_CLKOUT5_PHASE=270., p_CLKOUT5_DIVIDE=p//1, # sys_ps
+ )
+ self.specials += Instance("BUFG", i_I=pll[4], o_O=self.cd_sys.clk)
+ self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys_ps.clk)
+ self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd)
+
+ self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
+ p_INIT=0, p_SRTYPE="SYNC",
+ i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
+ i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk,
+ o_Q=platform.request("sdram_clock"))
+
+
+class BaseSoC(SoCSDRAM):
+ csr_map = {
+ "spiflash": 16,
+ }
+ csr_map.update(SoCSDRAM.csr_map)
+
+ def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
+ clk_freq = 80*1000000
+ SoCSDRAM.__init__(self, platform, clk_freq,
+ cpu_reset_address=0x60000,
+ sdram_controller_settings=sdram_controller_settings,
+ **kwargs)
+
+ self.submodules.crg = _CRG(platform, clk_freq)
+
+ if not self.integrated_main_ram_size:
+ self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),
+ MT48LC4M16(clk_freq))
+ self.register_sdram_phy(self.sdrphy)
+
+ if not self.integrated_rom_size:
+ self.submodules.spiflash = spi_flash.SpiFlash(platform.request("spiflash2x"),
+ dummy=4, div=6)
+ self.flash_boot_address = 0x70000
+ self.register_rom(self.spiflash.bus)
+
+
+def main():
+ soc = BaseSoC(papilio_pro.Platform(), cpu_type="or1k")
+ builder = Builder(soc, "misoc_build")
+ builder.build()
+
+
+if __name__ == "__main__":
+ main()
--- /dev/null
+from fractions import Fraction
+
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from misoc.cores.sdram_settings import MT46H32M16
+from misoc.cores.sdram_phy import S6HalfRateDDRPHY
+from misoc.cores.lasmicon.core import LASMIconSettings
+from misoc.cores import spi_flash
+from misoc.integration.soc_sdram import SoCSDRAM
+
+
+class _CRG(Module):
+ def __init__(self, platform, clk_freq):
+ self.clock_domains.cd_sys = ClockDomain()
+ self.clock_domains.cd_sdram_half = ClockDomain()
+ self.clock_domains.cd_sdram_full_wr = ClockDomain()
+ self.clock_domains.cd_sdram_full_rd = ClockDomain()
+
+ self.clk4x_wr_strb = Signal()
+ self.clk4x_rd_strb = Signal()
+
+ f0 = Fraction(50, 1)*1000000
+ p = 12
+ f = Fraction(clk_freq*p, f0)
+ n, d = f.numerator, f.denominator
+ assert 19e6 <= f0/d <= 500e6 # pfd
+ assert 400e6 <= f0*n/d <= 1080e6 # vco
+
+ clk50 = platform.request("clk50")
+ clk50a = Signal()
+ self.specials += Instance("IBUFG", i_I=clk50, o_O=clk50a)
+ clk50b = Signal()
+ self.specials += Instance("BUFIO2", p_DIVIDE=1,
+ p_DIVIDE_BYPASS="TRUE", p_I_INVERT="FALSE",
+ i_I=clk50a, o_DIVCLK=clk50b)
+ pll_lckd = Signal()
+ pll_fb = Signal()
+ pll = Signal(6)
+ self.specials.pll = Instance("PLL_ADV", p_SIM_DEVICE="SPARTAN6",
+ p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
+ p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
+ i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
+ p_DIVCLK_DIVIDE=d, p_CLKFBOUT_MULT=n, p_CLKFBOUT_PHASE=0.,
+ i_CLKIN1=clk50b, i_CLKIN2=0, i_CLKINSEL=1,
+ p_CLKIN1_PERIOD=1e9/f0, p_CLKIN2_PERIOD=0.,
+ i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
+ o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
+ o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
+ o_CLKOUT2=pll[2], p_CLKOUT2_DUTY_CYCLE=.5,
+ o_CLKOUT3=pll[3], p_CLKOUT3_DUTY_CYCLE=.5,
+ o_CLKOUT4=pll[4], p_CLKOUT4_DUTY_CYCLE=.5,
+ o_CLKOUT5=pll[5], p_CLKOUT5_DUTY_CYCLE=.5,
+ p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//4, # sdram wr rd
+ p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//4,
+ p_CLKOUT2_PHASE=270., p_CLKOUT2_DIVIDE=p//2, # sdram dqs adr ctrl
+ p_CLKOUT3_PHASE=250., p_CLKOUT3_DIVIDE=p//2, # off-chip ddr
+ p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1,
+ p_CLKOUT5_PHASE=0., p_CLKOUT5_DIVIDE=p//1, # sys
+ )
+ self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys.clk)
+ reset = platform.request("user_btn")
+ self.clock_domains.cd_por = ClockDomain()
+ por = Signal(max=1 << 11, reset=(1 << 11) - 1)
+ self.sync.por += If(por != 0, por.eq(por - 1))
+ self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
+ self.specials += AsyncResetSynchronizer(self.cd_por, reset)
+ self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd | (por > 0))
+ self.specials += Instance("BUFG", i_I=pll[2], o_O=self.cd_sdram_half.clk)
+ self.specials += Instance("BUFPLL", p_DIVIDE=4,
+ i_PLLIN=pll[0], i_GCLK=self.cd_sys.clk,
+ i_LOCKED=pll_lckd, o_IOCLK=self.cd_sdram_full_wr.clk,
+ o_SERDESSTROBE=self.clk4x_wr_strb)
+ self.comb += [
+ self.cd_sdram_full_rd.clk.eq(self.cd_sdram_full_wr.clk),
+ self.clk4x_rd_strb.eq(self.clk4x_wr_strb),
+ ]
+ clk_sdram_half_shifted = Signal()
+ self.specials += Instance("BUFG", i_I=pll[3], o_O=clk_sdram_half_shifted)
+ clk = platform.request("ddram_clock")
+ self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
+ p_INIT=0, p_SRTYPE="SYNC",
+ i_D0=1, i_D1=0, i_S=0, i_R=0, i_CE=1,
+ i_C0=clk_sdram_half_shifted, i_C1=~clk_sdram_half_shifted,
+ o_Q=clk.p)
+ self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
+ p_INIT=0, p_SRTYPE="SYNC",
+ i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
+ i_C0=clk_sdram_half_shifted, i_C1=~clk_sdram_half_shifted,
+ o_Q=clk.n)
+
+
+class BaseSoC(SoCSDRAM):
+ default_platform = "pipistrello"
+
+ csr_map = {
+ "spiflash": 16,
+ }
+ csr_map.update(SoCSDRAM.csr_map)
+
+ def __init__(self, platform, sdram_controller_settings=LASMIconSettings(),
+ clk_freq=(83 + Fraction(1, 3))*1000*1000, **kwargs):
+ SoCSDRAM.__init__(self, platform, clk_freq,
+ cpu_reset_address=0x170000, # 1.5 MB
+ sdram_controller_settings=sdram_controller_settings,
+ **kwargs)
+
+ self.submodules.crg = _CRG(platform, clk_freq)
+
+ if not self.integrated_main_ram_size:
+ self.submodules.ddrphy = S6HalfRateDDRPHY(platform.request("ddram"),
+ MT46H32M16(self.clk_freq),
+ rd_bitslip=1,
+ wr_bitslip=3,
+ dqs_ddr_alignment="C1")
+ self.comb += [
+ self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
+ self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
+ ]
+ self.register_sdram_phy(self.ddrphy)
+
+ if not self.integrated_rom_size:
+ self.submodules.spiflash = spi_flash.SpiFlash(platform.request("spiflash4x"),
+ dummy=10, div=4)
+ self.add_constant("SPIFLASH_PAGE_SIZE", 256)
+ self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
+ self.flash_boot_address = 0x180000
+ self.register_rom(self.spiflash.bus, 0x1000000)
+
+default_subtarget = BaseSoC
--- /dev/null
+from migen import *
+from migen.genlib.io import CRG
+
+from misoc.cores.liteeth_mini.phy import LiteEthPHY
+from misoc.cores.liteeth_mini.mac import LiteEthMAC
+from misoc.integration.soc_core import SoCCore, mem_decoder
+
+
+class BaseSoC(SoCCore):
+ def __init__(self, platform, **kwargs):
+ SoCCore.__init__(self, platform,
+ clk_freq=int((1/(platform.default_clk_period))*1000000000),
+ integrated_rom_size=0x8000,
+ integrated_main_ram_size=16*1024,
+ **kwargs)
+ self.submodules.crg = CRG(platform.request(platform.default_clk_name))
+
+
+class MiniSoC(BaseSoC):
+ csr_map = {
+ "ethphy": 20,
+ "ethmac": 21
+ }
+ csr_map.update(BaseSoC.csr_map)
+
+ interrupt_map = {
+ "ethmac": 2,
+ }
+ interrupt_map.update(BaseSoC.interrupt_map)
+
+ mem_map = {
+ "ethmac": 0x30000000, # (shadow @0xb0000000)
+ }
+ mem_map.update(BaseSoC.mem_map)
+
+ def __init__(self, platform, **kwargs):
+ BaseSoC.__init__(self, platform, **kwargs)
+
+ self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),
+ platform.request("eth"))
+ self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
+ interface="wishbone",
+ with_preamble_crc=False)
+ self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
+ self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
+
+default_subtarget = BaseSoC
--- /dev/null
+from migen import *
+from migen.genlib.io import CRG
+
+from misoc.integration.soc_core import SoCCore
+
+
+class BaseSoC(SoCCore):
+ default_platform = "versa"
+ def __init__(self, platform, **kwargs):
+ SoCCore.__init__(self, platform,
+ clk_freq=100*1000000,
+ integrated_rom_size=0x8000,
+ **kwargs)
+ self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("rst_n"))
+ self.comb += platform.request("user_led", 0).eq(ResetSignal())
+
+default_subtarget = BaseSoC
--- /dev/null
+#!/usr/bin/env python3
+
+import sys
+import os
+import time
+import serial
+import threading
+import argparse
+
+from serial.tools.miniterm import console, character, LF
+
+sfl_magic_len = 14
+sfl_magic_req = "sL5DdSMmkekro\n"
+sfl_magic_ack = "z6IHG7cYDID6o\n"
+
+# General commands
+sfl_cmd_abort = 0x00
+sfl_cmd_load = 0x01
+sfl_cmd_jump = 0x02
+
+
+# Replies
+sfl_ack_success = 'K'
+sfl_ack_crcerror = 'C'
+sfl_ack_unknown = 'U'
+sfl_ack_error = 'E'
+
+
+crc16_table = [
+ 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50A5, 0x60C6, 0x70E7,
+ 0x8108, 0x9129, 0xA14A, 0xB16B, 0xC18C, 0xD1AD, 0xE1CE, 0xF1EF,
+ 0x1231, 0x0210, 0x3273, 0x2252, 0x52B5, 0x4294, 0x72F7, 0x62D6,
+ 0x9339, 0x8318, 0xB37B, 0xA35A, 0xD3BD, 0xC39C, 0xF3FF, 0xE3DE,
+ 0x2462, 0x3443, 0x0420, 0x1401, 0x64E6, 0x74C7, 0x44A4, 0x5485,
+ 0xA56A, 0xB54B, 0x8528, 0x9509, 0xE5EE, 0xF5CF, 0xC5AC, 0xD58D,
+ 0x3653, 0x2672, 0x1611, 0x0630, 0x76D7, 0x66F6, 0x5695, 0x46B4,
+ 0xB75B, 0xA77A, 0x9719, 0x8738, 0xF7DF, 0xE7FE, 0xD79D, 0xC7BC,
+ 0x48C4, 0x58E5, 0x6886, 0x78A7, 0x0840, 0x1861, 0x2802, 0x3823,
+ 0xC9CC, 0xD9ED, 0xE98E, 0xF9AF, 0x8948, 0x9969, 0xA90A, 0xB92B,
+ 0x5AF5, 0x4AD4, 0x7AB7, 0x6A96, 0x1A71, 0x0A50, 0x3A33, 0x2A12,
+ 0xDBFD, 0xCBDC, 0xFBBF, 0xEB9E, 0x9B79, 0x8B58, 0xBB3B, 0xAB1A,
+ 0x6CA6, 0x7C87, 0x4CE4, 0x5CC5, 0x2C22, 0x3C03, 0x0C60, 0x1C41,
+ 0xEDAE, 0xFD8F, 0xCDEC, 0xDDCD, 0xAD2A, 0xBD0B, 0x8D68, 0x9D49,
+ 0x7E97, 0x6EB6, 0x5ED5, 0x4EF4, 0x3E13, 0x2E32, 0x1E51, 0x0E70,
+ 0xFF9F, 0xEFBE, 0xDFDD, 0xCFFC, 0xBF1B, 0xAF3A, 0x9F59, 0x8F78,
+ 0x9188, 0x81A9, 0xB1CA, 0xA1EB, 0xD10C, 0xC12D, 0xF14E, 0xE16F,
+ 0x1080, 0x00A1, 0x30C2, 0x20E3, 0x5004, 0x4025, 0x7046, 0x6067,
+ 0x83B9, 0x9398, 0xA3FB, 0xB3DA, 0xC33D, 0xD31C, 0xE37F, 0xF35E,
+ 0x02B1, 0x1290, 0x22F3, 0x32D2, 0x4235, 0x5214, 0x6277, 0x7256,
+ 0xB5EA, 0xA5CB, 0x95A8, 0x8589, 0xF56E, 0xE54F, 0xD52C, 0xC50D,
+ 0x34E2, 0x24C3, 0x14A0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
+ 0xA7DB, 0xB7FA, 0x8799, 0x97B8, 0xE75F, 0xF77E, 0xC71D, 0xD73C,
+ 0x26D3, 0x36F2, 0x0691, 0x16B0, 0x6657, 0x7676, 0x4615, 0x5634,
+ 0xD94C, 0xC96D, 0xF90E, 0xE92F, 0x99C8, 0x89E9, 0xB98A, 0xA9AB,
+ 0x5844, 0x4865, 0x7806, 0x6827, 0x18C0, 0x08E1, 0x3882, 0x28A3,
+ 0xCB7D, 0xDB5C, 0xEB3F, 0xFB1E, 0x8BF9, 0x9BD8, 0xABBB, 0xBB9A,
+ 0x4A75, 0x5A54, 0x6A37, 0x7A16, 0x0AF1, 0x1AD0, 0x2AB3, 0x3A92,
+ 0xFD2E, 0xED0F, 0xDD6C, 0xCD4D, 0xBDAA, 0xAD8B, 0x9DE8, 0x8DC9,
+ 0x7C26, 0x6C07, 0x5C64, 0x4C45, 0x3CA2, 0x2C83, 0x1CE0, 0x0CC1,
+ 0xEF1F, 0xFF3E, 0xCF5D, 0xDF7C, 0xAF9B, 0xBFBA, 0x8FD9, 0x9FF8,
+ 0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0
+]
+
+
+def crc16(l):
+ crc = 0
+ for d in l:
+ crc = crc16_table[((crc >> 8) ^ d) & 0xff] ^ (crc << 8)
+ return crc & 0xffff
+
+
+class SFLFrame:
+ def __init__(self):
+ self.length = None
+ self.cmd = None
+ self.payload = []
+ self.crc = None
+ self.raw = []
+
+ def compute_crc(self):
+ crc_data = []
+ crc_data.append(self.cmd)
+ for d in self.payload:
+ crc_data.append(d)
+ self.crc = crc16(crc_data)
+ return self.crc
+
+ def encode(self):
+ self.raw = []
+ self.raw.append(self.length)
+ self.compute_crc()
+ for d in self.crc.to_bytes(2, "big"):
+ self.raw.append(d)
+ self.raw.append(self.cmd)
+ for d in self.payload:
+ self.raw.append(d)
+
+
+def get_file_data(filename):
+ with open(filename, "rb") as f:
+ data = []
+ while True:
+ w = f.read(1)
+ if not w:
+ break
+ data.append(int.from_bytes(w, "big"))
+ return data
+
+
+class Flterm:
+ def __init__(self, kernel_image, kernel_address):
+ self.kernel_image = kernel_image
+ self.kernel_address = kernel_address
+
+ self.reader_alive = False
+ self.writer_alive = False
+
+ self.detect_magic_str = " "*len(sfl_magic_req)
+
+ def open(self, port, speed):
+ port = port if not port.isdigit() else int(port)
+ self.serial = serial.serial_for_url(
+ port,
+ baudrate=speed,
+ bytesize=8,
+ parity="N",
+ stopbits=1,
+ xonxoff=0,
+ timeout=0.25)
+ self.serial.flushOutput()
+ self.serial.flushInput()
+ self.serial.close() # in case port was not correctly closed
+ self.serial.open()
+
+ def close(self):
+ self.serial.close()
+
+ def write_exact(self, data):
+ if isinstance(data, str):
+ self.serial.write(bytes(data, "utf-8"))
+ else:
+ self.serial.write(serial.to_bytes(data))
+
+ def send_frame(self, frame):
+ frame.encode()
+ retry = 1
+ while retry:
+ self.write_exact(frame.raw)
+ # Get the reply from the device
+ reply = character(self.serial.read())
+ if reply == sfl_ack_success:
+ retry = 0
+ elif reply == sfl_ack_crcerror:
+ retry = 1
+ else:
+ print("[FLTERM] Got unknown reply '{}' from the device, aborting.".format(reply))
+ return 0
+ return 1
+
+ def upload(self, filename, address):
+ data = get_file_data(filename)
+ print("[FLTERM] Uploading {} ({} bytes)...".format(filename, len(data)))
+ current_address = address
+ position = 0
+ length = len(data)
+ start = time.time()
+ while len(data) != 0:
+ print("{}%\r".format(100*position//length), end="")
+ frame = SFLFrame()
+ frame_data = data[:251]
+ frame.length = len(frame_data) + 4
+ frame.cmd = sfl_cmd_load
+ for d in current_address.to_bytes(4, "big"):
+ frame.payload.append(d)
+ for d in frame_data:
+ frame.payload.append(d)
+ if self.send_frame(frame) == 0:
+ return
+ current_address += len(frame_data)
+ position += len(frame_data)
+ try:
+ data = data[251:]
+ except:
+ data = []
+ end = time.time()
+ elapsed = end - start
+ print("[FLTERM] Upload complete ({0:.1f}KB/s).".format(length/(elapsed*1024)))
+ return length
+
+ def boot(self):
+ print("[FLTERM] Booting the device.")
+ frame = SFLFrame()
+ frame.length = 4
+ frame.cmd = sfl_cmd_jump
+ for d in self.kernel_address.to_bytes(4, "big"):
+ frame.payload.append(d)
+ self.send_frame(frame)
+
+ def detect_magic(self, data):
+ if data is not "":
+ self.detect_magic_str = self.detect_magic_str[1:] + data
+ return self.detect_magic_str == sfl_magic_req
+ else:
+ return False
+
+ def answer_magic(self):
+ print("[FLTERM] Received firmware download request from the device.")
+ if os.path.exists(self.kernel_image):
+ self.write_exact(sfl_magic_ack)
+ self.upload(self.kernel_image, self.kernel_address)
+ self.boot()
+ print("[FLTERM] Done.");
+
+ def reader(self):
+ try:
+ while self.reader_alive:
+ c = character(self.serial.read())
+ if c == '\r':
+ sys.stdout.write('\n')
+ else:
+ sys.stdout.write(c)
+ sys.stdout.flush()
+
+ if self.kernel_image is not None:
+ if self.detect_magic(c):
+ self.answer_magic()
+
+ except serial.SerialException:
+ self.reader_alive = False
+ raise
+
+ def start_reader(self):
+ self.reader_alive = True
+ self.reader_thread = threading.Thread(target=self.reader)
+ self.reader_thread.setDaemon(True)
+ self.reader_thread.start()
+
+ def stop_reader(self):
+ self.reader_alive = False
+ self.reader_thread.join()
+
+ def writer(self):
+ try:
+ while self.writer_alive:
+ try:
+ b = console.getkey()
+ except KeyboardInterrupt:
+ b = serial.to_bytes([3])
+ c = character(b)
+ if c == chr(0x03):
+ self.stop()
+ elif c == '\n':
+ self.serial.write(LF)
+ else:
+ self.serial.write(b)
+ except:
+ self.writer_alive = False
+ raise
+
+ def start_writer(self):
+ self.writer_alive = True
+ self.writer_thread = threading.Thread(target=self.writer)
+ self.writer_thread.setDaemon(True)
+ self.writer_thread.start()
+
+ def stop_writer(self):
+ self.writer_alive = False
+ self.writer_thread.join()
+
+ def start(self):
+ print("[FLTERM] Starting....")
+ self.start_reader()
+ self.start_writer()
+
+ def stop(self):
+ self.reader_alive = False
+ self.writer_alive = False
+
+ def join(self, writer_only=False):
+ self.writer_thread.join()
+ if not writer_only:
+ self.reader_thread.join()
+
+
+def _get_args():
+ parser = argparse.ArgumentParser()
+ parser.add_argument("--port", default="2", help="serial port")
+ parser.add_argument("--speed", default=115200, help="serial baudrate")
+ parser.add_argument("--kernel", default=None, help="kernel image")
+ parser.add_argument("--kernel-adr", type=lambda a: int(a, 0), default=0x40000000, help="kernel address")
+ return parser.parse_args()
+
+if __name__ == "__main__":
+ args = _get_args()
+ flterm = Flterm(args.kernel, args.kernel_adr)
+ flterm.open(args.port, args.speed)
+ flterm.start()
+ try:
+ flterm.join(True)
+ except KeyboardInterrupt:
+ pass
+ flterm.join()
--- /dev/null
+#!/usr/bin/env python3
+
+import argparse
+import binascii
+
+
+def insert_crc(i_filename, fbi_mode=False, o_filename=None):
+ if o_filename is None:
+ o_filename = i_filename
+
+ with open(i_filename, "rb") as f:
+ fdata = f.read()
+ fcrc = binascii.crc32(fdata).to_bytes(4, byteorder="big")
+ flength = len(fdata).to_bytes(4, byteorder="big")
+
+ with open(o_filename, "wb") as f:
+ if fbi_mode:
+ f.write(flength)
+ f.write(fcrc)
+ f.write(fdata)
+ else:
+ f.write(fdata)
+ f.write(fcrc)
+
+
+def main():
+ parser = argparse.ArgumentParser(description="CRC32 computation tool and MiSoC image file writer.")
+ parser.add_argument("input", help="input file")
+ parser.add_argument("-o", "--output", default=None, help="output file (if not specified, use input file)")
+ parser.add_argument("-f", "--fbi", default=False, action="store_true", help="build flash boot image (FBI) file")
+ args = parser.parse_args()
+ insert_crc(args.input, args.fbi, args.output)
+
+
+if __name__ == "__main__":
+ main()
+++ /dev/null
-import sys
-import importlib
-
-
-def misoc_import(default, external, name):
- if external:
- try:
- del sys.modules[name] # force external path search
- except KeyError:
- pass
- loader = importlib.find_loader(name, [external])
- if loader is None:
- # try internal import
- return importlib.import_module(default + "." + name)
- return loader.load_module()
- else:
- return importlib.import_module(default + "." + name)
+++ /dev/null
-#!/usr/bin/env python3
-
-import argparse
-import crc
-
-if __name__ == "__main__":
- parser = argparse.ArgumentParser(description="CRC32 computation tool and MiSoC image file writer.")
- parser.add_argument("input", help="input file")
- parser.add_argument("-o", "--output", default=None, help="output file (if not specified, use input file)")
- parser.add_argument("-f", "--fbi", default=False, action="store_true", help="build flash boot image (FBI) file")
- args = parser.parse_args()
- crc.insert_crc(args.input, args.fbi, args.output)
+++ /dev/null
-from migen import *
-
-from misoc.cores.sdram_settings import IS42S16160
-from misoc.cores.sdram_phy import GENSDRPHY
-from misoc.cores.lasmicon.core import LASMIconSettings
-from misoc.integration.soc_sdram import SoCSDRAM
-
-
-class _PLL(Module):
- def __init__(self, period_in, name, phase_shift, operation_mode):
- self.clk_in = Signal()
- self.clk_out = Signal()
-
- self.specials += Instance("ALTPLL",
- p_bandwidth_type = "AUTO",
- p_clk0_divide_by = 1,
- p_clk0_duty_cycle = 50,
- p_clk0_multiply_by = 2,
- p_clk0_phase_shift = "{}".format(str(phase_shift)),
- p_compensate_clock = "CLK0",
- p_inclk0_input_frequency = int(period_in*1000),
- p_intended_device_family = "Cyclone IV E",
- p_lpm_hint = "CBX_MODULE_PREFIX={}_pll".format(name),
- p_lpm_type = "altpll",
- p_operation_mode = operation_mode,
- i_inclk=self.clk_in,
- o_clk=self.clk_out,
- i_areset=0,
- i_clkena=0x3f,
- i_clkswitch=0,
- i_configupdate=0,
- i_extclkena=0xf,
- i_fbin=1,
- i_pfdena=1,
- i_phasecounterselect=0xf,
- i_phasestep=1,
- i_phaseupdown=1,
- i_pllena=1,
- i_scanaclr=0,
- i_scanclk=0,
- i_scanclkena=1,
- i_scandata=0,
- i_scanread=0,
- i_scanwrite=0
- )
-
-
-class _CRG(Module):
- def __init__(self, platform):
- self.clock_domains.cd_sys = ClockDomain()
- self.clock_domains.cd_sys_ps = ClockDomain()
- self.clock_domains.cd_por = ClockDomain(reset_less=True)
-
- clk50 = platform.request("clk50")
-
- sys_pll = _PLL(20, "sys", 0, "NORMAL")
- self.submodules += sys_pll
- self.comb += [
- sys_pll.clk_in.eq(clk50),
- self.cd_sys.clk.eq(sys_pll.clk_out)
- ]
-
- sdram_pll = _PLL(20, "sdram", -3000, "ZERO_DELAY_BUFFER")
- self.submodules += sdram_pll
- self.comb += [
- sdram_pll.clk_in.eq(clk50),
- self.cd_sys_ps.clk.eq(sdram_pll.clk_out)
- ]
-
- # Power on Reset (vendor agnostic)
- rst_n = Signal()
- self.sync.por += rst_n.eq(1)
- self.comb += [
- self.cd_por.clk.eq(self.cd_sys.clk),
- self.cd_sys.rst.eq(~rst_n),
- self.cd_sys_ps.rst.eq(~rst_n)
- ]
-
- self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)
-
-
-class BaseSoC(SoCSDRAM):
- default_platform = "de0nano"
-
- def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
- SoCSDRAM.__init__(self, platform,
- clk_freq=100*1000000,
- integrated_rom_size=0x8000,
- sdram_controller_settings=sdram_controller_settings,
- **kwargs)
-
- self.submodules.crg = _CRG(platform)
-
- if not self.integrated_main_ram_size:
- self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),
- IS42S16160(self.clk_freq))
- self.register_sdram_phy(self.sdrphy)
-
-default_subtarget = BaseSoC
+++ /dev/null
-from migen import *
-from migen.genlib.resetsync import AsyncResetSynchronizer
-
-from misoc.cores.sdram_settings import MT8JTF12864
-from misoc.cores.sdram_phy import k7ddrphy
-from misoc.cores.lasmicon.core import LASMIconSettings
-from misoc.cores import spi_flash
-from misoc.cores.liteeth_mini.phy import LiteEthPHY
-from misoc.cores.liteeth_mini.mac import LiteEthMAC
-from misoc.integration.soc_core import mem_decoder
-from misoc.integration.soc_sdram import SoCSDRAM
-
-
-class _CRG(Module):
- def __init__(self, platform):
- self.clock_domains.cd_sys = ClockDomain()
- self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
- self.clock_domains.cd_clk200 = ClockDomain()
-
- clk200 = platform.request("clk200")
- clk200_se = Signal()
- self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)
-
- rst = platform.request("cpu_reset")
-
- pll_locked = Signal()
- pll_fb = Signal()
- self.pll_sys = Signal()
- pll_sys4x = Signal()
- pll_clk200 = Signal()
- self.specials += [
- Instance("PLLE2_BASE",
- p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
-
- # VCO @ 1GHz
- p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=5.0,
- p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
- i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
-
- # 125MHz
- p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=self.pll_sys,
-
- # 500MHz
- p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_sys4x,
-
- # 200MHz
- p_CLKOUT2_DIVIDE=5, p_CLKOUT2_PHASE=0.0, o_CLKOUT2=pll_clk200,
-
- p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=0.0, #o_CLKOUT3=,
-
- p_CLKOUT4_DIVIDE=4, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
- ),
- Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk),
- Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
- Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
- AsyncResetSynchronizer(self.cd_sys, ~pll_locked | rst),
- AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | rst),
- ]
-
- reset_counter = Signal(4, reset=15)
- ic_reset = Signal(reset=1)
- self.sync.clk200 += \
- If(reset_counter != 0,
- reset_counter.eq(reset_counter - 1)
- ).Else(
- ic_reset.eq(0)
- )
- self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
-
-
-class BaseSoC(SoCSDRAM):
- default_platform = "kc705"
-
- csr_map = {
- "spiflash": 16,
- "ddrphy": 17,
- }
- csr_map.update(SoCSDRAM.csr_map)
-
- def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
- SoCSDRAM.__init__(self, platform,
- clk_freq=125*1000000, cpu_reset_address=0xaf0000,
- sdram_controller_settings=sdram_controller_settings,
- **kwargs)
-
- self.submodules.crg = _CRG(platform)
-
- if not self.integrated_main_ram_size:
- self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"),
- MT8JTF12864(self.clk_freq))
- self.register_sdram_phy(self.ddrphy)
-
- if not self.integrated_rom_size:
- spiflash_pads = platform.request("spiflash")
- spiflash_pads.clk = Signal()
- self.specials += Instance("STARTUPE2",
- i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
- i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
- self.submodules.spiflash = spi_flash.SpiFlash(spiflash_pads, dummy=11, div=2)
- self.add_constant("SPIFLASH_PAGE_SIZE", 256)
- self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
- self.flash_boot_address = 0xb00000
- self.register_rom(self.spiflash.bus)
-
-
-class MiniSoC(BaseSoC):
- csr_map = {
- "ethphy": 18,
- "ethmac": 19,
- }
- csr_map.update(BaseSoC.csr_map)
-
- interrupt_map = {
- "ethmac": 2,
- }
- interrupt_map.update(BaseSoC.interrupt_map)
-
- mem_map = {
- "ethmac": 0x30000000, # (shadow @0xb0000000)
- }
- mem_map.update(BaseSoC.mem_map)
-
- def __init__(self, platform, **kwargs):
- BaseSoC.__init__(self, platform, **kwargs)
-
- self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"), clk_freq=self.clk_freq)
- self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
- self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
- self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
-
-default_subtarget = BaseSoC
+++ /dev/null
-from fractions import Fraction
-
-from migen import *
-from migen.genlib.resetsync import AsyncResetSynchronizer
-
-from misoc.cores.sdram_settings import AS4C16M16
-from misoc.cores.sdram_phy import GENSDRPHY
-from misoc.cores.lasmicon.core import LASMIconSettings
-from misoc.integration.soc_sdram import SoCSDRAM
-
-
-class _CRG(Module):
- def __init__(self, platform, clk_freq):
- self.clock_domains.cd_sys = ClockDomain()
- self.clock_domains.cd_sys_ps = ClockDomain()
-
- f0 = 32*1000000
- clk32 = platform.request("clk32")
- clk32a = Signal()
- self.specials += Instance("IBUFG", i_I=clk32, o_O=clk32a)
- clk32b = Signal()
- self.specials += Instance("BUFIO2", p_DIVIDE=1,
- p_DIVIDE_BYPASS="TRUE", p_I_INVERT="FALSE",
- i_I=clk32a, o_DIVCLK=clk32b)
- f = Fraction(int(clk_freq), int(f0))
- n, m, p = f.denominator, f.numerator, 8
- assert f0/n*m == clk_freq
- pll_lckd = Signal()
- pll_fb = Signal()
- pll = Signal(6)
- self.specials.pll = Instance("PLL_ADV", p_SIM_DEVICE="SPARTAN6",
- p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
- p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
- i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
- p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
- i_CLKIN1=clk32b, i_CLKIN2=0, i_CLKINSEL=1,
- p_CLKIN1_PERIOD=1000000000/f0, p_CLKIN2_PERIOD=0.,
- i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
- o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
- o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
- o_CLKOUT2=pll[2], p_CLKOUT2_DUTY_CYCLE=.5,
- o_CLKOUT3=pll[3], p_CLKOUT3_DUTY_CYCLE=.5,
- o_CLKOUT4=pll[4], p_CLKOUT4_DUTY_CYCLE=.5,
- o_CLKOUT5=pll[5], p_CLKOUT5_DUTY_CYCLE=.5,
- p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//1,
- p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//1,
- p_CLKOUT2_PHASE=0., p_CLKOUT2_DIVIDE=p//1,
- p_CLKOUT3_PHASE=0., p_CLKOUT3_DIVIDE=p//1,
- p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1, # sys
- p_CLKOUT5_PHASE=270., p_CLKOUT5_DIVIDE=p//1, # sys_ps
- )
- self.specials += Instance("BUFG", i_I=pll[4], o_O=self.cd_sys.clk)
- self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys_ps.clk)
- self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd)
-
- self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
- p_INIT=0, p_SRTYPE="SYNC",
- i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
- i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk,
- o_Q=platform.request("sdram_clock"))
-
-
-class BaseSoC(SoCSDRAM):
- default_platform = "minispartan6"
-
- def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
- clk_freq = 80*1000000
- SoCSDRAM.__init__(self, platform, clk_freq,
- integrated_rom_size=0x8000,
- sdram_controller_settings=sdram_controller_settings,
- **kwargs)
-
- self.submodules.crg = _CRG(platform, clk_freq)
-
- if not self.integrated_main_ram_size:
- self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),
- AS4C16M16(clk_freq))
- self.register_sdram_phy(self.sdrphy)
-
-default_subtarget = BaseSoC
+++ /dev/null
-import os
-from fractions import Fraction
-from math import ceil
-
-from migen import *
-from migen.build.generic_platform import ConstraintError
-
-from misoc.cores.sdram_settings import MT46V32M16
-from misoc.cores.sdram_phy import S6HalfRateDDRPHY
-from misoc.cores.lasmicon.core import LASMIconSettings
-from misoc.cores import nor_flash_16
-from misoc.cores import framebuffer
-from misoc.cores import gpio
-from misoc.cores.liteeth_mini.phy import LiteEthPHY
-from misoc.cores.liteeth_mini.mac import LiteEthMAC
-from misoc.integration.soc_core import mem_decoder
-from misoc.integration.soc_sdram import SoCSDRAM
-
-
-class _MXCRG(Module):
- def __init__(self, pads, outfreq1x):
- self.clock_domains.cd_sys = ClockDomain()
- self.clock_domains.cd_sdram_half = ClockDomain()
- self.clock_domains.cd_sdram_full_wr = ClockDomain()
- self.clock_domains.cd_sdram_full_rd = ClockDomain()
- self.clock_domains.cd_base50 = ClockDomain(reset_less=True)
-
- self.clk4x_wr_strb = Signal()
- self.clk4x_rd_strb = Signal()
-
- ###
-
- infreq = 50*1000000
- ratio = Fraction(outfreq1x)/Fraction(infreq)
- in_period = float(Fraction(1000000000)/Fraction(infreq))
-
- self.specials += Instance("mxcrg",
- Instance.Parameter("in_period", in_period),
- Instance.Parameter("f_mult", ratio.numerator),
- Instance.Parameter("f_div", ratio.denominator),
- Instance.Input("clk50_pad", pads.clk50),
- Instance.Input("trigger_reset", pads.trigger_reset),
-
- Instance.Output("sys_clk", self.cd_sys.clk),
- Instance.Output("sys_rst", self.cd_sys.rst),
- Instance.Output("clk2x_270", self.cd_sdram_half.clk),
- Instance.Output("clk4x_wr", self.cd_sdram_full_wr.clk),
- Instance.Output("clk4x_rd", self.cd_sdram_full_rd.clk),
- Instance.Output("base50_clk", self.cd_base50.clk),
-
- Instance.Output("clk4x_wr_strb", self.clk4x_wr_strb),
- Instance.Output("clk4x_rd_strb", self.clk4x_rd_strb),
- Instance.Output("norflash_rst_n", pads.norflash_rst_n),
- Instance.Output("ddr_clk_pad_p", pads.ddr_clk_p),
- Instance.Output("ddr_clk_pad_n", pads.ddr_clk_n))
-
-
-class _MXClockPads:
- def __init__(self, platform):
- self.clk50 = platform.request("clk50")
- self.trigger_reset = 0
- try:
- self.trigger_reset = platform.request("user_btn", 1)
- except ConstraintError:
- pass
- self.norflash_rst_n = platform.request("norflash_rst_n")
- ddram_clock = platform.request("ddram_clock")
- self.ddr_clk_p = ddram_clock.p
- self.ddr_clk_n = ddram_clock.n
-
-
-class BaseSoC(SoCSDRAM):
- default_platform = "mixxeo" # also supports m1
-
- def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
- SoCSDRAM.__init__(self, platform,
- clk_freq=(83 + Fraction(1, 3))*1000000,
- cpu_reset_address=0x00180000,
- sdram_controller_settings=sdram_controller_settings,
- **kwargs)
-
- self.submodules.crg = _MXCRG(_MXClockPads(platform), self.clk_freq)
-
- if not self.integrated_main_ram_size:
- self.submodules.ddrphy = S6HalfRateDDRPHY(platform.request("ddram"),
- MT46V32M16(self.clk_freq),
- rd_bitslip=0,
- wr_bitslip=3,
- dqs_ddr_alignment="C1")
- self.register_sdram_phy(self.ddrphy)
- self.comb += [
- self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
- self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
- ]
-
- if not self.integrated_rom_size:
- clk_period_ns = 1000000000/self.clk_freq
- self.submodules.norflash = nor_flash_16.NorFlash16(
- platform.request("norflash"),
- ceil(110/clk_period_ns), ceil(50/clk_period_ns))
- self.flash_boot_address = 0x001a0000
- self.register_rom(self.norflash.bus)
-
- platform.add_platform_command("""
-INST "mxcrg/wr_bufpll" LOC = "BUFPLL_X0Y2";
-INST "mxcrg/rd_bufpll" LOC = "BUFPLL_X0Y3";
-""")
- platform.add_source(os.path.join("misoc", "mxcrg.v"))
-
-
-class MiniSoC(BaseSoC):
- csr_map = {
- "ethphy": 16,
- "ethmac": 17,
- }
- csr_map.update(BaseSoC.csr_map)
-
- interrupt_map = {
- "ethmac": 2,
- }
- interrupt_map.update(BaseSoC.interrupt_map)
-
- mem_map = {
- "ethmac": 0x30000000, # (shadow @0xb0000000)
- }
- mem_map.update(BaseSoC.mem_map)
-
- def __init__(self, platform, **kwargs):
- BaseSoC.__init__(self, platform, **kwargs)
-
- if platform.name == "mixxeo":
- self.submodules.leds = gpio.GPIOOut(platform.request("user_led"))
- if platform.name == "m1":
- self.submodules.buttons = gpio.GPIOIn(Cat(platform.request("user_btn", 0),
- platform.request("user_btn", 2)))
- self.submodules.leds = gpio.GPIOOut(Cat(platform.request("user_led", i) for i in range(2)))
-
- self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),
- platform.request("eth"))
- self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
- self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
- self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
-
-
-def get_vga_dvi(platform):
- try:
- pads_vga = platform.request("vga_out")
- except ConstraintError:
- pads_vga = None
- try:
- pads_dvi = platform.request("dvi_out")
- except ConstraintError:
- pads_dvi = None
- else:
- platform.add_platform_command("""
-PIN "dviout_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;
-""")
- return pads_vga, pads_dvi
-
-
-def add_vga_tig(platform, fb):
- platform.add_platform_command("""
-NET "{vga_clk}" TNM_NET = "GRPvga_clk";
-NET "sys_clk" TNM_NET = "GRPsys_clk";
-TIMESPEC "TSise_sucks1" = FROM "GRPvga_clk" TO "GRPsys_clk" TIG;
-TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
-""", vga_clk=fb.driver.clocking.cd_pix.clk)
-
-
-class FramebufferSoC(MiniSoC):
- csr_map = {
- "fb": 18,
- }
- csr_map.update(MiniSoC.csr_map)
-
- def __init__(self, platform, **kwargs):
- MiniSoC.__init__(self, platform, **kwargs)
- pads_vga, pads_dvi = get_vga_dvi(platform)
- self.submodules.fb = framebuffer.Framebuffer(pads_vga, pads_dvi,
- self.sdram.crossbar.get_master())
- add_vga_tig(platform, self.fb)
-
-default_subtarget = FramebufferSoC
+++ /dev/null
-from fractions import Fraction
-
-from migen import *
-from migen.genlib.resetsync import AsyncResetSynchronizer
-
-from misoc.cores.sdram_settings import MT46H32M16
-from misoc.cores.sdram_phy import S6HalfRateDDRPHY
-from misoc.cores.lasmicon.core import LASMIconSettings
-from misoc.cores import spi_flash
-from misoc.integration.soc_sdram import SoCSDRAM
-
-
-class _CRG(Module):
- def __init__(self, platform, clk_freq):
- self.clock_domains.cd_sys = ClockDomain()
- self.clock_domains.cd_sdram_half = ClockDomain()
- self.clock_domains.cd_sdram_full_wr = ClockDomain()
- self.clock_domains.cd_sdram_full_rd = ClockDomain()
-
- self.clk4x_wr_strb = Signal()
- self.clk4x_rd_strb = Signal()
-
- f0 = Fraction(50, 1)*1000000
- p = 12
- f = Fraction(clk_freq*p, f0)
- n, d = f.numerator, f.denominator
- assert 19e6 <= f0/d <= 500e6 # pfd
- assert 400e6 <= f0*n/d <= 1080e6 # vco
-
- clk50 = platform.request("clk50")
- clk50a = Signal()
- self.specials += Instance("IBUFG", i_I=clk50, o_O=clk50a)
- clk50b = Signal()
- self.specials += Instance("BUFIO2", p_DIVIDE=1,
- p_DIVIDE_BYPASS="TRUE", p_I_INVERT="FALSE",
- i_I=clk50a, o_DIVCLK=clk50b)
- pll_lckd = Signal()
- pll_fb = Signal()
- pll = Signal(6)
- self.specials.pll = Instance("PLL_ADV", p_SIM_DEVICE="SPARTAN6",
- p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
- p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
- i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
- p_DIVCLK_DIVIDE=d, p_CLKFBOUT_MULT=n, p_CLKFBOUT_PHASE=0.,
- i_CLKIN1=clk50b, i_CLKIN2=0, i_CLKINSEL=1,
- p_CLKIN1_PERIOD=1e9/f0, p_CLKIN2_PERIOD=0.,
- i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
- o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
- o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
- o_CLKOUT2=pll[2], p_CLKOUT2_DUTY_CYCLE=.5,
- o_CLKOUT3=pll[3], p_CLKOUT3_DUTY_CYCLE=.5,
- o_CLKOUT4=pll[4], p_CLKOUT4_DUTY_CYCLE=.5,
- o_CLKOUT5=pll[5], p_CLKOUT5_DUTY_CYCLE=.5,
- p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//4, # sdram wr rd
- p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//4,
- p_CLKOUT2_PHASE=270., p_CLKOUT2_DIVIDE=p//2, # sdram dqs adr ctrl
- p_CLKOUT3_PHASE=250., p_CLKOUT3_DIVIDE=p//2, # off-chip ddr
- p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1,
- p_CLKOUT5_PHASE=0., p_CLKOUT5_DIVIDE=p//1, # sys
- )
- self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys.clk)
- reset = platform.request("user_btn")
- self.clock_domains.cd_por = ClockDomain()
- por = Signal(max=1 << 11, reset=(1 << 11) - 1)
- self.sync.por += If(por != 0, por.eq(por - 1))
- self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
- self.specials += AsyncResetSynchronizer(self.cd_por, reset)
- self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd | (por > 0))
- self.specials += Instance("BUFG", i_I=pll[2], o_O=self.cd_sdram_half.clk)
- self.specials += Instance("BUFPLL", p_DIVIDE=4,
- i_PLLIN=pll[0], i_GCLK=self.cd_sys.clk,
- i_LOCKED=pll_lckd, o_IOCLK=self.cd_sdram_full_wr.clk,
- o_SERDESSTROBE=self.clk4x_wr_strb)
- self.comb += [
- self.cd_sdram_full_rd.clk.eq(self.cd_sdram_full_wr.clk),
- self.clk4x_rd_strb.eq(self.clk4x_wr_strb),
- ]
- clk_sdram_half_shifted = Signal()
- self.specials += Instance("BUFG", i_I=pll[3], o_O=clk_sdram_half_shifted)
- clk = platform.request("ddram_clock")
- self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
- p_INIT=0, p_SRTYPE="SYNC",
- i_D0=1, i_D1=0, i_S=0, i_R=0, i_CE=1,
- i_C0=clk_sdram_half_shifted, i_C1=~clk_sdram_half_shifted,
- o_Q=clk.p)
- self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
- p_INIT=0, p_SRTYPE="SYNC",
- i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
- i_C0=clk_sdram_half_shifted, i_C1=~clk_sdram_half_shifted,
- o_Q=clk.n)
-
-
-class BaseSoC(SoCSDRAM):
- default_platform = "pipistrello"
-
- csr_map = {
- "spiflash": 16,
- }
- csr_map.update(SoCSDRAM.csr_map)
-
- def __init__(self, platform, sdram_controller_settings=LASMIconSettings(),
- clk_freq=(83 + Fraction(1, 3))*1000*1000, **kwargs):
- SoCSDRAM.__init__(self, platform, clk_freq,
- cpu_reset_address=0x170000, # 1.5 MB
- sdram_controller_settings=sdram_controller_settings,
- **kwargs)
-
- self.submodules.crg = _CRG(platform, clk_freq)
-
- if not self.integrated_main_ram_size:
- self.submodules.ddrphy = S6HalfRateDDRPHY(platform.request("ddram"),
- MT46H32M16(self.clk_freq),
- rd_bitslip=1,
- wr_bitslip=3,
- dqs_ddr_alignment="C1")
- self.comb += [
- self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
- self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb),
- ]
- self.register_sdram_phy(self.ddrphy)
-
- if not self.integrated_rom_size:
- self.submodules.spiflash = spi_flash.SpiFlash(platform.request("spiflash4x"),
- dummy=10, div=4)
- self.add_constant("SPIFLASH_PAGE_SIZE", 256)
- self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
- self.flash_boot_address = 0x180000
- self.register_rom(self.spiflash.bus, 0x1000000)
-
-default_subtarget = BaseSoC
+++ /dev/null
-from fractions import Fraction
-
-from migen import *
-from migen.genlib.resetsync import AsyncResetSynchronizer
-
-from misoc.cores.sdram_settings import MT48LC4M16
-from misoc.cores.sdram_phy import GENSDRPHY
-from misoc.cores.lasmicon.core import LASMIconSettings
-from misoc.cores import spi_flash
-from misoc.integration.soc_sdram import SoCSDRAM
-
-
-class _CRG(Module):
- def __init__(self, platform, clk_freq):
- self.clock_domains.cd_sys = ClockDomain()
- self.clock_domains.cd_sys_ps = ClockDomain()
-
- f0 = 32*1000000
- clk32 = platform.request("clk32")
- clk32a = Signal()
- self.specials += Instance("IBUFG", i_I=clk32, o_O=clk32a)
- clk32b = Signal()
- self.specials += Instance("BUFIO2", p_DIVIDE=1,
- p_DIVIDE_BYPASS="TRUE", p_I_INVERT="FALSE",
- i_I=clk32a, o_DIVCLK=clk32b)
- f = Fraction(int(clk_freq), int(f0))
- n, m, p = f.denominator, f.numerator, 8
- assert f0/n*m == clk_freq
- pll_lckd = Signal()
- pll_fb = Signal()
- pll = Signal(6)
- self.specials.pll = Instance("PLL_ADV", p_SIM_DEVICE="SPARTAN6",
- p_BANDWIDTH="OPTIMIZED", p_COMPENSATION="INTERNAL",
- p_REF_JITTER=.01, p_CLK_FEEDBACK="CLKFBOUT",
- i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0,
- p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0.,
- i_CLKIN1=clk32b, i_CLKIN2=0, i_CLKINSEL=1,
- p_CLKIN1_PERIOD=1000000000/f0, p_CLKIN2_PERIOD=0.,
- i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd,
- o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5,
- o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5,
- o_CLKOUT2=pll[2], p_CLKOUT2_DUTY_CYCLE=.5,
- o_CLKOUT3=pll[3], p_CLKOUT3_DUTY_CYCLE=.5,
- o_CLKOUT4=pll[4], p_CLKOUT4_DUTY_CYCLE=.5,
- o_CLKOUT5=pll[5], p_CLKOUT5_DUTY_CYCLE=.5,
- p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//1,
- p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//1,
- p_CLKOUT2_PHASE=0., p_CLKOUT2_DIVIDE=p//1,
- p_CLKOUT3_PHASE=0., p_CLKOUT3_DIVIDE=p//1,
- p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//1, # sys
- p_CLKOUT5_PHASE=270., p_CLKOUT5_DIVIDE=p//1, # sys_ps
- )
- self.specials += Instance("BUFG", i_I=pll[4], o_O=self.cd_sys.clk)
- self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys_ps.clk)
- self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd)
-
- self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
- p_INIT=0, p_SRTYPE="SYNC",
- i_D0=0, i_D1=1, i_S=0, i_R=0, i_CE=1,
- i_C0=self.cd_sys.clk, i_C1=~self.cd_sys.clk,
- o_Q=platform.request("sdram_clock"))
-
-
-class BaseSoC(SoCSDRAM):
- default_platform = "papilio_pro"
-
- csr_map = {
- "spiflash": 16,
- }
- csr_map.update(SoCSDRAM.csr_map)
-
- def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
- clk_freq = 80*1000000
- SoCSDRAM.__init__(self, platform, clk_freq,
- cpu_reset_address=0x60000,
- sdram_controller_settings=sdram_controller_settings,
- **kwargs)
-
- self.submodules.crg = _CRG(platform, clk_freq)
-
- if not self.integrated_main_ram_size:
- self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"),
- MT48LC4M16(clk_freq))
- self.register_sdram_phy(self.sdrphy)
-
- if not self.integrated_rom_size:
- self.submodules.spiflash = spi_flash.SpiFlash(platform.request("spiflash2x"),
- dummy=4, div=6)
- self.flash_boot_address = 0x70000
- self.register_rom(self.spiflash.bus)
-
-default_subtarget = BaseSoC
+++ /dev/null
-from migen import *
-from migen.genlib.io import CRG
-
-from misoc.cores.liteeth_mini.phy import LiteEthPHY
-from misoc.cores.liteeth_mini.mac import LiteEthMAC
-from misoc.integration.soc_core import SoCCore, mem_decoder
-
-
-class BaseSoC(SoCCore):
- def __init__(self, platform, **kwargs):
- SoCCore.__init__(self, platform,
- clk_freq=int((1/(platform.default_clk_period))*1000000000),
- integrated_rom_size=0x8000,
- integrated_main_ram_size=16*1024,
- **kwargs)
- self.submodules.crg = CRG(platform.request(platform.default_clk_name))
-
-
-class MiniSoC(BaseSoC):
- csr_map = {
- "ethphy": 20,
- "ethmac": 21
- }
- csr_map.update(BaseSoC.csr_map)
-
- interrupt_map = {
- "ethmac": 2,
- }
- interrupt_map.update(BaseSoC.interrupt_map)
-
- mem_map = {
- "ethmac": 0x30000000, # (shadow @0xb0000000)
- }
- mem_map.update(BaseSoC.mem_map)
-
- def __init__(self, platform, **kwargs):
- BaseSoC.__init__(self, platform, **kwargs)
-
- self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),
- platform.request("eth"))
- self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
- interface="wishbone",
- with_preamble_crc=False)
- self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
- self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
-
-default_subtarget = BaseSoC
+++ /dev/null
-from migen import *
-from migen.genlib.io import CRG
-
-from misoc.integration.soc_core import SoCCore
-
-
-class BaseSoC(SoCCore):
- default_platform = "versa"
- def __init__(self, platform, **kwargs):
- SoCCore.__init__(self, platform,
- clk_freq=100*1000000,
- integrated_rom_size=0x8000,
- **kwargs)
- self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("rst_n"))
- self.comb += platform.request("user_led", 0).eq(ResetSignal())
-
-default_subtarget = BaseSoC
+++ /dev/null
-TARGETS=byteswap
-CC=gcc
-RM ?= rm -f
-
-all: $(TARGETS)
-
-%: %.c
- $(CC) -O2 -Wall -I../common -s -o $@ $<
-
-.PHONY: all clean
-
-clean:
- $(RM) $(TARGETS)
+++ /dev/null
-/*
- * MiSoC
- * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <stdlib.h>
-#include <string.h>
-#include <stdio.h>
-
-int main(int argc, char *argv[])
-{
- FILE *fdi, *fdo;
- unsigned short wi;
- unsigned short wo;
- int i;
-
- if(argc != 3) {
- fprintf(stderr, "Usage: byteswap <infile> <outfile>\n");
- return 1;
- }
- fdi = fopen(argv[1], "rb");
- if(!fdi) {
- perror("Unable to open input file");
- return 1;
- }
- fdo = fopen(argv[2], "w");
- if(!fdo) {
- perror("Unable to open output file");
- fclose(fdi);
- return 1;
- }
- while(1) {
- if(fread(&wi, 2, 1, fdi) <= 0) break;
- wo = 0;
- for(i=0;i<16;i++)
- if(wi & (1 << i))
- wo |= (0x8000 >> i);
- /* comment out the next line on big endian machines! */
- wo = ((wo & 0x00ff) << 8) | ((wo & 0xff00) >> 8);
- fwrite(&wo, 2, 1, fdo);
- }
- fclose(fdi);
- if(fclose(fdo) != 0) {
- perror("Unable to close output file");
- return 1;
- }
- return 0;
-}
+++ /dev/null
-#!/usr/bin/env python3
-import sys
-import os
-import time
-import serial
-import threading
-import argparse
-
-from serial.tools.miniterm import console, character, LF
-
-sfl_magic_len = 14
-sfl_magic_req = "sL5DdSMmkekro\n"
-sfl_magic_ack = "z6IHG7cYDID6o\n"
-
-# General commands
-sfl_cmd_abort = 0x00
-sfl_cmd_load = 0x01
-sfl_cmd_jump = 0x02
-
-
-# Replies
-sfl_ack_success = 'K'
-sfl_ack_crcerror = 'C'
-sfl_ack_unknown = 'U'
-sfl_ack_error = 'E'
-
-
-crc16_table = [
- 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50A5, 0x60C6, 0x70E7,
- 0x8108, 0x9129, 0xA14A, 0xB16B, 0xC18C, 0xD1AD, 0xE1CE, 0xF1EF,
- 0x1231, 0x0210, 0x3273, 0x2252, 0x52B5, 0x4294, 0x72F7, 0x62D6,
- 0x9339, 0x8318, 0xB37B, 0xA35A, 0xD3BD, 0xC39C, 0xF3FF, 0xE3DE,
- 0x2462, 0x3443, 0x0420, 0x1401, 0x64E6, 0x74C7, 0x44A4, 0x5485,
- 0xA56A, 0xB54B, 0x8528, 0x9509, 0xE5EE, 0xF5CF, 0xC5AC, 0xD58D,
- 0x3653, 0x2672, 0x1611, 0x0630, 0x76D7, 0x66F6, 0x5695, 0x46B4,
- 0xB75B, 0xA77A, 0x9719, 0x8738, 0xF7DF, 0xE7FE, 0xD79D, 0xC7BC,
- 0x48C4, 0x58E5, 0x6886, 0x78A7, 0x0840, 0x1861, 0x2802, 0x3823,
- 0xC9CC, 0xD9ED, 0xE98E, 0xF9AF, 0x8948, 0x9969, 0xA90A, 0xB92B,
- 0x5AF5, 0x4AD4, 0x7AB7, 0x6A96, 0x1A71, 0x0A50, 0x3A33, 0x2A12,
- 0xDBFD, 0xCBDC, 0xFBBF, 0xEB9E, 0x9B79, 0x8B58, 0xBB3B, 0xAB1A,
- 0x6CA6, 0x7C87, 0x4CE4, 0x5CC5, 0x2C22, 0x3C03, 0x0C60, 0x1C41,
- 0xEDAE, 0xFD8F, 0xCDEC, 0xDDCD, 0xAD2A, 0xBD0B, 0x8D68, 0x9D49,
- 0x7E97, 0x6EB6, 0x5ED5, 0x4EF4, 0x3E13, 0x2E32, 0x1E51, 0x0E70,
- 0xFF9F, 0xEFBE, 0xDFDD, 0xCFFC, 0xBF1B, 0xAF3A, 0x9F59, 0x8F78,
- 0x9188, 0x81A9, 0xB1CA, 0xA1EB, 0xD10C, 0xC12D, 0xF14E, 0xE16F,
- 0x1080, 0x00A1, 0x30C2, 0x20E3, 0x5004, 0x4025, 0x7046, 0x6067,
- 0x83B9, 0x9398, 0xA3FB, 0xB3DA, 0xC33D, 0xD31C, 0xE37F, 0xF35E,
- 0x02B1, 0x1290, 0x22F3, 0x32D2, 0x4235, 0x5214, 0x6277, 0x7256,
- 0xB5EA, 0xA5CB, 0x95A8, 0x8589, 0xF56E, 0xE54F, 0xD52C, 0xC50D,
- 0x34E2, 0x24C3, 0x14A0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
- 0xA7DB, 0xB7FA, 0x8799, 0x97B8, 0xE75F, 0xF77E, 0xC71D, 0xD73C,
- 0x26D3, 0x36F2, 0x0691, 0x16B0, 0x6657, 0x7676, 0x4615, 0x5634,
- 0xD94C, 0xC96D, 0xF90E, 0xE92F, 0x99C8, 0x89E9, 0xB98A, 0xA9AB,
- 0x5844, 0x4865, 0x7806, 0x6827, 0x18C0, 0x08E1, 0x3882, 0x28A3,
- 0xCB7D, 0xDB5C, 0xEB3F, 0xFB1E, 0x8BF9, 0x9BD8, 0xABBB, 0xBB9A,
- 0x4A75, 0x5A54, 0x6A37, 0x7A16, 0x0AF1, 0x1AD0, 0x2AB3, 0x3A92,
- 0xFD2E, 0xED0F, 0xDD6C, 0xCD4D, 0xBDAA, 0xAD8B, 0x9DE8, 0x8DC9,
- 0x7C26, 0x6C07, 0x5C64, 0x4C45, 0x3CA2, 0x2C83, 0x1CE0, 0x0CC1,
- 0xEF1F, 0xFF3E, 0xCF5D, 0xDF7C, 0xAF9B, 0xBFBA, 0x8FD9, 0x9FF8,
- 0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0
-]
-
-
-def crc16(l):
- crc = 0
- for d in l:
- crc = crc16_table[((crc >> 8) ^ d) & 0xff] ^ (crc << 8)
- return crc & 0xffff
-
-
-class SFLFrame:
- def __init__(self):
- self.length = None
- self.cmd = None
- self.payload = []
- self.crc = None
- self.raw = []
-
- def compute_crc(self):
- crc_data = []
- crc_data.append(self.cmd)
- for d in self.payload:
- crc_data.append(d)
- self.crc = crc16(crc_data)
- return self.crc
-
- def encode(self):
- self.raw = []
- self.raw.append(self.length)
- self.compute_crc()
- for d in self.crc.to_bytes(2, "big"):
- self.raw.append(d)
- self.raw.append(self.cmd)
- for d in self.payload:
- self.raw.append(d)
-
-
-def get_file_data(filename):
- with open(filename, "rb") as f:
- data = []
- while True:
- w = f.read(1)
- if not w:
- break
- data.append(int.from_bytes(w, "big"))
- return data
-
-
-class Flterm:
- def __init__(self, kernel_image, kernel_address):
- self.kernel_image = kernel_image
- self.kernel_address = kernel_address
-
- self.reader_alive = False
- self.writer_alive = False
-
- self.detect_magic_str = " "*len(sfl_magic_req)
-
- def open(self, port, speed):
- port = port if not port.isdigit() else int(port)
- self.serial = serial.serial_for_url(
- port,
- baudrate=speed,
- bytesize=8,
- parity="N",
- stopbits=1,
- xonxoff=0,
- timeout=0.25)
- self.serial.flushOutput()
- self.serial.flushInput()
- self.serial.close() # in case port was not correctly closed
- self.serial.open()
-
- def close(self):
- self.serial.close()
-
- def write_exact(self, data):
- if isinstance(data, str):
- self.serial.write(bytes(data, "utf-8"))
- else:
- self.serial.write(serial.to_bytes(data))
-
- def send_frame(self, frame):
- frame.encode()
- retry = 1
- while retry:
- self.write_exact(frame.raw)
- # Get the reply from the device
- reply = character(self.serial.read())
- if reply == sfl_ack_success:
- retry = 0
- elif reply == sfl_ack_crcerror:
- retry = 1
- else:
- print("[FLTERM] Got unknown reply '{}' from the device, aborting.".format(reply))
- return 0
- return 1
-
- def upload(self, filename, address):
- data = get_file_data(filename)
- print("[FLTERM] Uploading {} ({} bytes)...".format(filename, len(data)))
- current_address = address
- position = 0
- length = len(data)
- start = time.time()
- while len(data) != 0:
- print("{}%\r".format(100*position//length), end="")
- frame = SFLFrame()
- frame_data = data[:251]
- frame.length = len(frame_data) + 4
- frame.cmd = sfl_cmd_load
- for d in current_address.to_bytes(4, "big"):
- frame.payload.append(d)
- for d in frame_data:
- frame.payload.append(d)
- if self.send_frame(frame) == 0:
- return
- current_address += len(frame_data)
- position += len(frame_data)
- try:
- data = data[251:]
- except:
- data = []
- end = time.time()
- elapsed = end - start
- print("[FLTERM] Upload complete ({0:.1f}KB/s).".format(length/(elapsed*1024)))
- return length
-
- def boot(self):
- print("[FLTERM] Booting the device.")
- frame = SFLFrame()
- frame.length = 4
- frame.cmd = sfl_cmd_jump
- for d in self.kernel_address.to_bytes(4, "big"):
- frame.payload.append(d)
- self.send_frame(frame)
-
- def detect_magic(self, data):
- if data is not "":
- self.detect_magic_str = self.detect_magic_str[1:] + data
- return self.detect_magic_str == sfl_magic_req
- else:
- return False
-
- def answer_magic(self):
- print("[FLTERM] Received firmware download request from the device.")
- if os.path.exists(self.kernel_image):
- self.write_exact(sfl_magic_ack)
- self.upload(self.kernel_image, self.kernel_address)
- self.boot()
- print("[FLTERM] Done.");
-
- def reader(self):
- try:
- while self.reader_alive:
- c = character(self.serial.read())
- if c == '\r':
- sys.stdout.write('\n')
- else:
- sys.stdout.write(c)
- sys.stdout.flush()
-
- if self.kernel_image is not None:
- if self.detect_magic(c):
- self.answer_magic()
-
- except serial.SerialException:
- self.reader_alive = False
- raise
-
- def start_reader(self):
- self.reader_alive = True
- self.reader_thread = threading.Thread(target=self.reader)
- self.reader_thread.setDaemon(True)
- self.reader_thread.start()
-
- def stop_reader(self):
- self.reader_alive = False
- self.reader_thread.join()
-
- def writer(self):
- try:
- while self.writer_alive:
- try:
- b = console.getkey()
- except KeyboardInterrupt:
- b = serial.to_bytes([3])
- c = character(b)
- if c == chr(0x03):
- self.stop()
- elif c == '\n':
- self.serial.write(LF)
- else:
- self.serial.write(b)
- except:
- self.writer_alive = False
- raise
-
- def start_writer(self):
- self.writer_alive = True
- self.writer_thread = threading.Thread(target=self.writer)
- self.writer_thread.setDaemon(True)
- self.writer_thread.start()
-
- def stop_writer(self):
- self.writer_alive = False
- self.writer_thread.join()
-
- def start(self):
- print("[FLTERM] Starting....")
- self.start_reader()
- self.start_writer()
-
- def stop(self):
- self.reader_alive = False
- self.writer_alive = False
-
- def join(self, writer_only=False):
- self.writer_thread.join()
- if not writer_only:
- self.reader_thread.join()
-
-
-def _get_args():
- parser = argparse.ArgumentParser()
- parser.add_argument("--port", default="2", help="serial port")
- parser.add_argument("--speed", default=115200, help="serial baudrate")
- parser.add_argument("--kernel", default=None, help="kernel image")
- parser.add_argument("--kernel-adr", type=lambda a: int(a, 0), default=0x40000000, help="kernel address")
- return parser.parse_args()
-
-if __name__ == "__main__":
- args = _get_args()
- flterm = Flterm(args.kernel, args.kernel_adr)
- flterm.open(args.port, args.speed)
- flterm.start()
- try:
- flterm.join(True)
- except KeyboardInterrupt:
- pass
- flterm.join()
projects / litex.git / commitdiff