arm-protos.h (arm_arch_thumb1): Declare.

2016-05-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    * config/arm/arm-protos.h (arm_arch_thumb1): Declare.
    * config/arm/arm.c (arm_arch_thumb1): Define.
    (arm_option_override): Initialize arm_arch_thumb1.
    * config/arm/arm.h (arm_arch_thumb1): Declare.
    (TARGET_ARM_ARCH_ISA_THUMB): Use arm_arch_thumb to determine if target
    support Thumb-1 ISA.

    gcc/testsuite/
    * gcc.target/arm/armv5_thumb_isa.c: New test.

From-SVN: r236913

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 587afe0b1f16f5468c2a30b213f5840380337516..b4f8c5650c205e311700eda8045757248008e1e0 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,12 @@
+2016-05-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+       * config/arm/arm-protos.h (arm_arch_thumb1): Declare.
+       * config/arm/arm.c (arm_arch_thumb1): Define.
+       (arm_option_override): Initialize arm_arch_thumb1.
+       * config/arm/arm.h (arm_arch_thumb1): Declare.
+       (TARGET_ARM_ARCH_ISA_THUMB): Use arm_arch_thumb to determine if target
+       support Thumb-1 ISA.
+
 2016-05-31  Kirill Yukhin  <kirill.yukhin@intel.com>
 
        PR target/71346

diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index d8179c441bb53dced94d2ebf497aad093e4ac600..34fd06a92d99cfcb7ece4da7f1a2957e0225e4fb 100644 (file)
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -603,6 +603,9 @@ extern int arm_tune_cortex_a9;
    interworking clean.  */
 extern int arm_cpp_interwork;
 
+/* Nonzero if chip supports Thumb 1.  */
+extern int arm_arch_thumb1;
+
 /* Nonzero if chip supports Thumb 2.  */
 extern int arm_arch_thumb2;
 

diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 4e453fd710112adc0cf581ea817bf17df63ac9c4..16499ce647bba0adc2fdb4b8f7d665b169deb4e7 100644 (file)
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -847,6 +847,9 @@ int arm_tune_cortex_a9 = 0;
    interworking clean.  */
 int arm_cpp_interwork = 0;
 
+/* Nonzero if chip supports Thumb 1.  */
+int arm_arch_thumb1;
+
 /* Nonzero if chip supports Thumb 2.  */
 int arm_arch_thumb2;
 
@@ -3165,6 +3168,7 @@ arm_option_override (void)
   arm_arch7em = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH7EM);
   arm_arch8 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH8);
   arm_arch8_1 = ARM_FSET_HAS_CPU2 (insn_flags, FL2_ARCH8_1);
+  arm_arch_thumb1 = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB);
   arm_arch_thumb2 = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB2);
   arm_arch_xscale = ARM_FSET_HAS_CPU1 (insn_flags, FL_XSCALE);
 

diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 1e817a88e8f17dd07a0b293c2cc6689115710dae..065e7da4bfac2dc99d9ace023247a605790a4789 100644 (file)
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -479,6 +479,9 @@ extern int arm_tune_cortex_a9;
    interworking clean.  */
 extern int arm_cpp_interwork;
 
+/* Nonzero if chip supports Thumb 1.  */
+extern int arm_arch_thumb1;
+
 /* Nonzero if chip supports Thumb 2.  */
 extern int arm_arch_thumb2;
 
@@ -2189,9 +2192,8 @@ extern int making_const_table;
   (arm_base_arch)      \
 
 /* The highest Thumb instruction set version supported by the chip.  */
-#define TARGET_ARM_ARCH_ISA_THUMB              \
-  (arm_arch_thumb2 ? 2                         \
-                  : ((TARGET_ARM_ARCH >= 5 || arm_arch4t) ? 1 : 0))
+#define TARGET_ARM_ARCH_ISA_THUMB              \
+  (arm_arch_thumb2 ? 2 : (arm_arch_thumb1 ? 1 : 0))
 
 /* Expands to an upper-case char of the target's architectural
    profile.  */

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 05eb1e8d0847c698b17555784b8c6e52fb2aa5cc..563d5e5885ca25777805c72bb108e8b958db603f 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2016-05-31  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+       * gcc.target/arm/armv5_thumb_isa.c: New test.
+
 2016-05-31  Kirill Yukhin  <kirill.yukhin@intel.com>
 
        PR target/71346

diff --git a/gcc/testsuite/gcc.target/arm/armv5_thumb_isa.c b/gcc/testsuite/gcc.target/arm/armv5_thumb_isa.c
new file mode 100644 (file)
index 0000000..80a00ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/armv5_thumb_isa.c
@@ -0,0 +1,8 @@
+/* { dg-require-effective-target arm_arch_v5_ok } */
+/* { dg-add-options arm_arch_v5 } */
+
+#if __ARM_ARCH_ISA_THUMB
+#error "__ARM_ARCH_ISA_THUMB defined for ARMv5"
+#endif
+
+int foo;