Revert "Fix TODOs"

This reverts commit 8674a6c68d563908014d16671567459499c6dc99.

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 3523db3a470c9030d843ef5ede29b045d5b05c46..8a2c2caf53fdd799d0622b87b764d971732f0c31 100644 (file)
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -103,6 +103,11 @@ code sigA sigB sigC sigD sigM clock
        }
        else
                sigM = P;
+       // TODO: Check if necessary
+       // This sigM could have no users if downstream $add
+       //   is narrower than $mul result, for example
+       if (sigM.empty())
+               reject;
 
        clock = port(dsp, \CLK, SigBit());
 endcode
@@ -154,6 +159,16 @@ match preAdd
        optional
 endmatch
 
+code sigA sigD
+       // TODO: Check if this is necessary?
+       if (preAdd) {
+               sigA = port(preAdd, \A);
+               sigD = port(preAdd, \B);
+               if (GetSize(sigA) < GetSize(sigD))
+                       std::swap(sigA, sigD);
+       }
+endcode
+
 // (4) If pre-adder was present, find match 'A' input for A2REG
 //     If pre-adder was not present, move ADREG to A2REG
 //     Then match 'A' input for A1REG

diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg
index 3d911b4783c00518b9eac0c0db675db6ac73c426..b87a686a15906f67d063d85e3d8db0ebe7de4172 100644 (file)
--- a/passes/pmgen/xilinx_dsp_CREG.pmg
+++ b/passes/pmgen/xilinx_dsp_CREG.pmg
@@ -79,6 +79,11 @@ endcode
 //     (attached to at most two $mux cells that implement clock-enable or
 //      reset functionality, using the in_dffe subpattern)
 code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock
+       // TODO: Any downside to allowing this?
+       // If this DSP implements an accumulator, do not attempt to match
+       if (sigC == sigP)
+               reject;
+
        argQ = sigC;
        subpattern(in_dffe);
        if (dff) {