+2017-06-23 Will Schmidt <will_schmidt@vnet.ibm.com>
+
+ * config/rs6000/rs6000.c: Add include of ssa-propagate.h for
+ update_call_from_tree(). (rs6000_gimple_fold_builtin): Add
+ handling for early expansion of vector shifts (sl,sr,sra,rl).
+ (builtin_function_type): Add vector shift right instructions
+ to the unsigned argument list.
+
2017-06-23 Bernd Edlinger <bernd.edlinger@hotmail.de>
rtl-optimizatoin/79286
#endif
#include "case-cfn-macros.h"
#include "ppc-auxv.h"
+#include "tree-ssa-propagate.h"
/* This file should be included last. */
#include "target-def.h"
gsi_replace (gsi, g, true);
return true;
}
+ /* Flavors of vec_rotate_left. */
+ case ALTIVEC_BUILTIN_VRLB:
+ case ALTIVEC_BUILTIN_VRLH:
+ case ALTIVEC_BUILTIN_VRLW:
+ case P8V_BUILTIN_VRLD:
+ {
+ arg0 = gimple_call_arg (stmt, 0);
+ arg1 = gimple_call_arg (stmt, 1);
+ lhs = gimple_call_lhs (stmt);
+ gimple *g = gimple_build_assign (lhs, LROTATE_EXPR, arg0, arg1);
+ gimple_set_location (g, gimple_location (stmt));
+ gsi_replace (gsi, g, true);
+ return true;
+ }
+ /* Flavors of vector shift right algebraic.
+ vec_sra{b,h,w} -> vsra{b,h,w}. */
+ case ALTIVEC_BUILTIN_VSRAB:
+ case ALTIVEC_BUILTIN_VSRAH:
+ case ALTIVEC_BUILTIN_VSRAW:
+ case P8V_BUILTIN_VSRAD:
+ {
+ arg0 = gimple_call_arg (stmt, 0);
+ arg1 = gimple_call_arg (stmt, 1);
+ lhs = gimple_call_lhs (stmt);
+ gimple *g = gimple_build_assign (lhs, RSHIFT_EXPR, arg0, arg1);
+ gimple_set_location (g, gimple_location (stmt));
+ gsi_replace (gsi, g, true);
+ return true;
+ }
+ /* Flavors of vector shift left.
+ builtin_altivec_vsl{b,h,w} -> vsl{b,h,w}. */
+ case ALTIVEC_BUILTIN_VSLB:
+ case ALTIVEC_BUILTIN_VSLH:
+ case ALTIVEC_BUILTIN_VSLW:
+ case P8V_BUILTIN_VSLD:
+ {
+ arg0 = gimple_call_arg (stmt, 0);
+ if (INTEGRAL_TYPE_P (TREE_TYPE (TREE_TYPE (arg0)))
+ && !TYPE_OVERFLOW_WRAPS (TREE_TYPE (TREE_TYPE (arg0))))
+ return false;
+ arg1 = gimple_call_arg (stmt, 1);
+ lhs = gimple_call_lhs (stmt);
+ gimple *g = gimple_build_assign (lhs, LSHIFT_EXPR, arg0, arg1);
+ gimple_set_location (g, gimple_location (stmt));
+ gsi_replace (gsi, g, true);
+ return true;
+ }
+ /* Flavors of vector shift right. */
+ case ALTIVEC_BUILTIN_VSRB:
+ case ALTIVEC_BUILTIN_VSRH:
+ case ALTIVEC_BUILTIN_VSRW:
+ case P8V_BUILTIN_VSRD:
+ {
+ arg0 = gimple_call_arg (stmt, 0);
+ arg1 = gimple_call_arg (stmt, 1);
+ lhs = gimple_call_lhs (stmt);
+ gimple_seq stmts = NULL;
+ /* Convert arg0 to unsigned. */
+ tree arg0_unsigned
+ = gimple_build (&stmts, VIEW_CONVERT_EXPR,
+ unsigned_type_for (TREE_TYPE (arg0)), arg0);
+ tree res
+ = gimple_build (&stmts, RSHIFT_EXPR,
+ TREE_TYPE (arg0_unsigned), arg0_unsigned, arg1);
+ /* Convert result back to the lhs type. */
+ res = gimple_build (&stmts, VIEW_CONVERT_EXPR, TREE_TYPE (lhs), res);
+ gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
+ update_call_from_tree (gsi, res);
+ return true;
+ }
default:
break;
}
h.uns_p[2] = 1;
break;
+ /* unsigned second arguments (vector shift right). */
+ case ALTIVEC_BUILTIN_VSRB:
+ case ALTIVEC_BUILTIN_VSRH:
+ case ALTIVEC_BUILTIN_VSRW:
+ case P8V_BUILTIN_VSRD:
+ h.uns_p[2] = 1;
+ break;
+
default:
break;
}
+2017-06-23 Will Schmidt <will_schmidt@vnet.ibm.com>
+
+ * gcc.target/powerpc/fold-vec-shift-char.c: New.
+ * gcc.target/powerpc/fold-vec-shift-int.c: New.
+ * gcc.target/powerpc/fold-vec-shift-longlong.c: New.
+ * gcc.target/powerpc/fold-vec-shift-short.c: New.
+ * gcc.target/powerpc/fold-vec-shift-left.c: New.
+ * gcc.target/powerpc/fold-vec-shift-left-fwrapv.c: New.
+ * gcc.target/powerpc/fold-vec-shift-left-longlong-fwrapv.c: New.
+ * gcc.target/powerpc/fold-vec-shift-left-longlong.c: New.
+
2017-06-23 James Cowgill <James.Cowgill@imgtec.com>
* go.test/go-test.exp (go-set-goarch): Update MIPS architecture
--- /dev/null
+/* Verify that overloaded built-ins for vec_sl with char
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+//# vec_sl - shift left
+//# vec_sr - shift right
+//# vec_sra - shift right algebraic
+//# vec_rl - rotate left
+
+vector signed char
+testsl_signed (vector signed char x, vector unsigned char y)
+{
+ return vec_sl (x, y);
+}
+
+vector unsigned char
+testsl_unsigned (vector unsigned char x, vector unsigned char y)
+{
+ return vec_sl (x, y);
+}
+
+vector signed char
+testsr_signed (vector signed char x, vector unsigned char y)
+{
+ return vec_sr (x, y);
+}
+
+vector unsigned char
+testsr_unsigned (vector unsigned char x, vector unsigned char y)
+{
+ return vec_sr (x, y);
+}
+
+vector signed char
+testsra_signed (vector signed char x, vector unsigned char y)
+{
+ return vec_sra (x, y);
+}
+
+vector unsigned char
+testsra_unsigned (vector unsigned char x, vector unsigned char y)
+{
+ return vec_sra (x, y);
+}
+
+vector signed char
+testrl_signed (vector signed char x, vector unsigned char y)
+{
+ return vec_rl (x, y);
+}
+
+vector unsigned char
+testrl_unsigned (vector unsigned char x, vector unsigned char y)
+{
+ return vec_rl (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vslb" 2 } } */
+/* { dg-final { scan-assembler-times "vsrb" 2 } } */
+/* { dg-final { scan-assembler-times "vsrab" 2 } } */
+/* { dg-final { scan-assembler-times "vrlb" 2 } } */
--- /dev/null
+/* Verify that overloaded built-ins for vec_sl with int
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector signed int
+testsl_signed (vector signed int x, vector unsigned int y)
+{
+ return vec_sl (x, y);
+}
+
+vector unsigned int
+testsl_unsigned (vector unsigned int x, vector unsigned int y)
+{
+ return vec_sl (x, y);
+}
+
+vector signed int
+testsr_signed (vector signed int x, vector unsigned int y)
+{
+ return vec_sr (x, y);
+}
+
+vector unsigned int
+testsr_unsigned (vector unsigned int x, vector unsigned int y)
+{
+ return vec_sr (x, y);
+}
+
+vector signed int
+testsra_signed (vector signed int x, vector unsigned int y)
+{
+ return vec_sra (x, y);
+}
+
+vector unsigned int
+testsra_unsigned (vector unsigned int x, vector unsigned int y)
+{
+ return vec_sra (x, y);
+}
+
+vector signed int
+testrl_signed (vector signed int x, vector unsigned int y)
+{
+ return vec_rl (x, y);
+}
+
+vector unsigned int
+testrl_unsigned (vector unsigned int x, vector unsigned int y)
+{
+ return vec_rl (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vslw" 2 } } */
+/* { dg-final { scan-assembler-times "vsrw" 2 } } */
+/* { dg-final { scan-assembler-times "vsraw" 2 } } */
+/* { dg-final { scan-assembler-times "vrlw" 2 } } */
--- /dev/null
+/* Verify that overloaded built-ins for vec_sl produce the right results. */
+/* This test covers the shift left tests with the -fwrapv option. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -fwrapv" } */
+
+#include <altivec.h>
+
+vector signed char
+testsl_signed_char (vector signed char x, vector unsigned char y)
+{
+ return vec_sl (x, y);
+}
+
+vector unsigned char
+testsl_unsigned_char (vector unsigned char x, vector unsigned char y)
+{
+ return vec_sl (x, y);
+}
+
+vector signed short
+testsl_signed_short (vector signed short x, vector unsigned short y)
+{
+ return vec_sl (x, y);
+}
+
+vector unsigned short
+testsl_unsigned_short (vector unsigned short x, vector unsigned short y)
+{
+ return vec_sl (x, y);
+}
+
+vector signed int
+testsl_signed_int (vector signed int x, vector unsigned int y)
+{
+ return vec_sl (x, y);
+}
+
+vector unsigned int
+testsl_unsigned_int (vector unsigned int x, vector unsigned int y)
+{
+ return vec_sl (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vslb" 2 } } */
+/* { dg-final { scan-assembler-times "vslh" 2 } } */
+/* { dg-final { scan-assembler-times "vslw" 2 } } */
--- /dev/null
+/* Verify that overloaded built-ins for vec_sl produce the right results. */
+/* This test covers the shift left tests with the -fwrapv option. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2 -mpower8-vector -fwrapv" } */
+
+#include <altivec.h>
+
+vector signed long long
+testsl_signed_longlong (vector signed long long x, vector unsigned long long y)
+{
+ return vec_sl (x, y);
+}
+
+vector unsigned long long
+testsl_unsigned_longlong (vector unsigned long long x, vector unsigned long long y)
+{
+ return vec_sl (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vsld" 2 } } */
--- /dev/null
+/* cross section of shift tests specific for shift-left.
+ * This is a counterpart to the fold-vec-shift-left-frwapv test. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -mpower8-vector -O2" } */
+
+#include <altivec.h>
+
+vector signed long long
+testsl_signed_longlong (vector signed long long x, vector unsigned long long y)
+{
+ return vec_sl (x, y);
+}
+
+vector unsigned long long
+testsl_unsigned_longlong (vector unsigned long long x, vector unsigned long long y)
+{
+ return vec_sl (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vsld" 2 } } */
--- /dev/null
+/* cross section of shift tests specific for shift-left.
+ * This is a counterpart to the fold-vec-shift-left-frwapv test. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector signed char
+testsl_signed_char (vector signed char x, vector unsigned char y)
+{
+ return vec_sl (x, y);
+}
+
+vector unsigned char
+testsl_unsigned_char (vector unsigned char x, vector unsigned char y)
+{
+ return vec_sl (x, y);
+}
+
+vector signed short
+testsl_signed_short (vector signed short x, vector unsigned short y)
+{
+ return vec_sl (x, y);
+}
+
+vector unsigned short
+testsl_unsigned_short (vector unsigned short x, vector unsigned short y)
+{
+ return vec_sl (x, y);
+}
+
+vector signed int
+testsl_signed_int (vector signed int x, vector unsigned int y)
+{
+ return vec_sl (x, y);
+}
+
+vector unsigned int
+testsl_unsigned_int (vector unsigned int x, vector unsigned int y)
+{
+ return vec_sl (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vslb" 2 } } */
+/* { dg-final { scan-assembler-times "vslh" 2 } } */
+/* { dg-final { scan-assembler-times "vslw" 2 } } */
--- /dev/null
+/* Verify that overloaded built-ins for vec_sl with long long
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mpower8-vector -O2" } */
+
+#include <altivec.h>
+
+vector signed long long
+testsl_signed (vector signed long long x, vector unsigned long long y)
+{
+ return vec_sl (x, y);
+}
+
+vector unsigned long long
+testsl_unsigned (vector unsigned long long x, vector unsigned long long y)
+{
+ return vec_sl (x, y);
+}
+
+vector signed long long
+testsr_signed (vector signed long long x, vector unsigned long long y)
+{
+ return vec_sr (x, y);
+}
+
+vector unsigned long long
+testsr_unsigned (vector unsigned long long x, vector unsigned long long y)
+{
+ return vec_sr (x, y);
+}
+
+vector signed long long
+testsra_signed (vector signed long long x, vector unsigned long long y)
+{
+ return vec_sra (x, y);
+}
+
+/* watch for PR 79544 here (vsrd / vsrad issue) */
+vector unsigned long long
+testsra_unsigned (vector unsigned long long x, vector unsigned long long y)
+{
+ return vec_sra (x, y);
+}
+
+vector signed long long
+testrl_signed (vector signed long long x, vector unsigned long long y)
+{
+ return vec_rl (x, y);
+}
+
+vector unsigned long long
+testrl_unsigned (vector unsigned long long x, vector unsigned long long y)
+{
+ return vec_rl (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vsld" 2 } } */
+/* { dg-final { scan-assembler-times "vsrd" 2 } } */
+/* { dg-final { scan-assembler-times "vsrad" 2 } } */
+/* { dg-final { scan-assembler-times "vrld" 2 } } */
+
--- /dev/null
+/* Verify that overloaded built-ins for vec_sl with short
+ inputs produce the right results. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector signed short
+testsl_signed (vector signed short x, vector unsigned short y)
+{
+ return vec_sl (x, y);
+}
+
+vector unsigned short
+testsl_unsigned (vector unsigned short x, vector unsigned short y)
+{
+ return vec_sl (x, y);
+}
+
+vector signed short
+testsr_signed (vector signed short x, vector unsigned short y)
+{
+ return vec_sr (x, y);
+}
+
+vector unsigned short
+testsr_unsigned (vector unsigned short x, vector unsigned short y)
+{
+ return vec_sr (x, y);
+}
+
+vector signed short
+testsra_signed (vector signed short x, vector unsigned short y)
+{
+ return vec_sra (x, y);
+}
+
+vector unsigned short
+testsra_unsigned (vector unsigned short x, vector unsigned short y)
+{
+ return vec_sra (x, y);
+}
+
+vector signed short
+testrl_signed (vector signed short x, vector unsigned short y)
+{
+ return vec_rl (x, y);
+}
+
+vector unsigned short
+testrl_unsigned (vector unsigned short x, vector unsigned short y)
+{
+ return vec_rl (x, y);
+}
+
+/* { dg-final { scan-assembler-times "vslh" 2 } } */
+/* { dg-final { scan-assembler-times "vsrh" 2 } } */
+/* { dg-final { scan-assembler-times "vsrah" 2 } } */
+/* { dg-final { scan-assembler-times "vrlh" 2 } } */
projects / gcc.git / commitdiff