(match_dup 4)))])
(define_insn ""
- [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
+ [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
(plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
- (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))
- (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
+ (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
"! TARGET_POWERPC64"
"@
- xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
- {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3
- {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
- {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
- {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
+ xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
+ {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
+ {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
+ {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
+ {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
[(set_attr "length" "12,8,12,12,12")])
(define_insn ""