[AArch64, ILP32] 3/6 Change tests to be ILP32-friendly.

gcc/testsuite/

	* gcc.dg/20020219-1.c: Skip the test on aarch64*-*-* in ilp32.
	* gcc.target/aarch64/aapcs64/test_18.c (struct y): Change the field
	type from long to long long.
	* gcc.target/aarch64/atomic-op-long.c: Update dg-final directives
	to have effective-target keywords of lp64 and ilp32.
	* gcc.target/aarch64/fcvt_double_int.c: Likewise.
	* gcc.target/aarch64/fcvt_double_long.c: Likewise.
	* gcc.target/aarch64/fcvt_double_uint.c: Likewise.
	* gcc.target/aarch64/fcvt_double_ulong.c: Likewise.
	* gcc.target/aarch64/fcvt_float_int.c: Likewise.
	* gcc.target/aarch64/fcvt_float_long.c: Likewise.
	* gcc.target/aarch64/fcvt_float_uint.c: Likewise.
	* gcc.target/aarch64/fcvt_float_ulong.c: Likewise.
	* gcc.target/aarch64/vect_smlal_1.c: Replace 'long' with 'long long'.

From-SVN: r201166

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 4cd3d0f62b259ab9f3d0fdba8056334adadddff5..e715ca564fdf28450c0b997e52b940947588ae85 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,20 @@
+2013-07-23  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+       * gcc.dg/20020219-1.c: Skip the test on aarch64*-*-* in ilp32.
+       * gcc.target/aarch64/aapcs64/test_18.c (struct y): Change the field
+       type from long to long long.
+       * gcc.target/aarch64/atomic-op-long.c: Update dg-final directives
+       to have effective-target keywords of lp64 and ilp32.
+       * gcc.target/aarch64/fcvt_double_int.c: Likewise.
+       * gcc.target/aarch64/fcvt_double_long.c: Likewise.
+       * gcc.target/aarch64/fcvt_double_uint.c: Likewise.
+       * gcc.target/aarch64/fcvt_double_ulong.c: Likewise.
+       * gcc.target/aarch64/fcvt_float_int.c: Likewise.
+       * gcc.target/aarch64/fcvt_float_long.c: Likewise.
+       * gcc.target/aarch64/fcvt_float_uint.c: Likewise.
+       * gcc.target/aarch64/fcvt_float_ulong.c: Likewise.
+       * gcc.target/aarch64/vect_smlal_1.c: Replace 'long' with 'long long'.
+
 2013-07-23  Tom Tromey  <tromey@redhat.com>
            Joseph Myers  <joseph@codesourcery.com>
 

diff --git a/gcc/testsuite/gcc.dg/20020219-1.c b/gcc/testsuite/gcc.dg/20020219-1.c
index ffdf19a43c1fdd437ef6c95f85d8e0a2790f86a8..d2ba755f50ffe489dacfac0b0e1cd3f35298a21f 100644 (file)
--- a/gcc/testsuite/gcc.dg/20020219-1.c
+++ b/gcc/testsuite/gcc.dg/20020219-1.c
@@ -13,6 +13,7 @@
 /* { dg-do run } */
 /* { dg-options "-O2" } */
 /* { dg-options "-O2 -mdisable-indexing" { target hppa*-*-hpux* } } */
+/* { dg-skip-if "" { aarch64*-*-* && ilp32 } { "*" } { "" } } */
 /* { dg-skip-if "" { "ia64-*-hpux*" } "*" "-mlp64" } */
 /* { dg-skip-if "" { { i?86-*-* x86_64-*-* } && x32 } { "*" } { "" } } */
 

diff --git a/gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c b/gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c
index b611e9b27faf7295fdcf0f9c7104d0d4ac6c17cb..2ebecee63e5c5ee978c9e185a730d86ee32e3e1e 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c
+++ b/gcc/testsuite/gcc.target/aarch64/aapcs64/test_18.c
@@ -9,10 +9,10 @@
 
 struct y
 {
-  long p;
-  long q;
-  long r;
-  long s;
+  long long p;
+  long long q;
+  long long r;
+  long long s;
 } v = { 1, 2, 3, 4 };
 
 struct z

diff --git a/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c
index 9468ef445248e396b18beba4dc4a8375977e1ce9..0672d48b66a86627a5c9347fd5efbe882efba71f 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c
@@ -39,5 +39,7 @@ atomic_fetch_or_RELAXED (long a)
   return __atomic_fetch_or (&v, a, __ATOMIC_RELAXED);
 }
 
-/* { dg-final { scan-assembler-times "ldxr\tx\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
-/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, x\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "ldxr\tx\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target lp64} } } */
+/* { dg-final { scan-assembler-times "ldxr\tw\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, x\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target lp64} } } */
+/* { dg-final { scan-assembler-times "stxr\tw\[0-9\]+, w\[0-9\]+, \\\[x\[0-9\]+\\\]" 6 {target ilp32} } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_double_int.c b/gcc/testsuite/gcc.target/aarch64/fcvt_double_int.c
index 697aab1c478534dc4f860eeddd71e054248d0c93..e5399099b71d17c55fff36ae84508656e24bc297 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/fcvt_double_int.c
+++ b/gcc/testsuite/gcc.target/aarch64/fcvt_double_int.c
@@ -8,8 +8,10 @@
 #include "fcvt.x"
 
 /* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *d\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
 /* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *d\[0-9\]" 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c b/gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c
index edf640bda4bd60a258941f7ba2e57b35772f6831..5eb36ff6dddbca85ee9c78661319e7f2e6653a02 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c
+++ b/gcc/testsuite/gcc.target/aarch64/fcvt_double_long.c
@@ -7,7 +7,11 @@
 
 #include "fcvt.x"
 
-/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *d\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 3 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 3 } } */
-/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *d\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 3 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 3 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_double_uint.c b/gcc/testsuite/gcc.target/aarch64/fcvt_double_uint.c
index a1fae764fdb4eac25892e1f11d1032542a53327c..59be47512cf73884700c1fb5de69ace7558e8ae3 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/fcvt_double_uint.c
+++ b/gcc/testsuite/gcc.target/aarch64/fcvt_double_uint.c
@@ -8,8 +8,10 @@
 #include "fcvt.x"
 
 /* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *d\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */
 /* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *d\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */
 /* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *d\[0-9\]" 2 } } */
 /* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *d\[0-9\]" 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c b/gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c
index f95fe55c6742884e3303c19ae566a745249da9b7..55723cf90635c1960bfe43d31fbda8c2d4441e92 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c
+++ b/gcc/testsuite/gcc.target/aarch64/fcvt_double_ulong.c
@@ -7,9 +7,15 @@
 
 #include "fcvt.x"
 
-/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *d\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *d\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *d\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *d\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *d\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *d\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *d\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *d\[0-9\]" 2 {target ilp32} } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c b/gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c
index ac1509857c4b84564303eeaae3fda888aad938a6..2e10e2dec9d82cd8e6ce3d5e6a432ca9071842cb 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c
+++ b/gcc/testsuite/gcc.target/aarch64/fcvt_float_int.c
@@ -8,8 +8,10 @@
 #include "fcvt.x"
 
 /* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *s\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */
 /* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *s\[0-9\]" 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c b/gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c
index 928ac52f7bccef2360127d1f50035fea0583f049..1debf710f5629b29f5b13393b33ce09b1587880b 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c
+++ b/gcc/testsuite/gcc.target/aarch64/fcvt_float_long.c
@@ -7,7 +7,11 @@
 
 #include "fcvt.x"
 
-/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *s\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 3 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 3 } } */
-/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *s\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtzs\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 3 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 3 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 3 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtas\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtas\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c b/gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c
index a7d1868ba7393fae95bdc875588ed02ed97a27fa..c0b0c693a2b27f672eb5d87e8030251a7b3305d9 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c
+++ b/gcc/testsuite/gcc.target/aarch64/fcvt_float_uint.c
@@ -8,8 +8,10 @@
 #include "fcvt.x"
 
 /* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *s\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */
 /* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *s\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */
 /* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *s\[0-9\]" 2 } } */
 /* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *s\[0-9\]" 2 } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c b/gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c
index ab6f46e7134b00d4b14d725d02a7b471843982a5..07309e2c884bc22c11ec56aa9f105db5a21ef734 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c
+++ b/gcc/testsuite/gcc.target/aarch64/fcvt_float_ulong.c
@@ -7,9 +7,15 @@
 
 #include "fcvt.x"
 
-/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *s\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *s\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 } } */
-/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *s\[0-9\]" 2 } } */
-/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *s\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-times "fcvtzu\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtzu\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtps\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtpu\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtpu\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tx\[0-9\]+, *s\[0-9\]" 1 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtms\tw\[0-9\]+, *s\[0-9\]" 1 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtmu\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtmu\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */
+/* { dg-final { scan-assembler-times "fcvtau\tx\[0-9\]+, *s\[0-9\]" 2 {target lp64} } } */
+/* { dg-final { scan-assembler-times "fcvtau\tw\[0-9\]+, *s\[0-9\]" 2 {target ilp32} } } */

diff --git a/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c b/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c
index 1f86eaeeb6e8cc2cb1fa4be4ea1ab0ef33a14b74..f8cfeccf3347883a0c3c657c26c2a24ed8a8a33c 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/vect_smlal_1.c
@@ -4,11 +4,11 @@
 typedef signed char S8_t;
 typedef signed short S16_t;
 typedef signed int S32_t;
-typedef signed long S64_t;
+typedef signed long long S64_t;
 typedef signed char *__restrict__ pS8_t;
 typedef signed short *__restrict__ pS16_t;
 typedef signed int *__restrict__ pS32_t;
-typedef signed long *__restrict__ pS64_t;
+typedef signed long long *__restrict__ pS64_t;
 typedef unsigned char U8_t;
 typedef unsigned short U16_t;
 typedef unsigned int U32_t;
@@ -16,7 +16,7 @@ typedef unsigned long U64_t;
 typedef unsigned char *__restrict__ pU8_t;
 typedef unsigned short *__restrict__ pU16_t;
 typedef unsigned int *__restrict__ pU32_t;
-typedef unsigned long *__restrict__ pU64_t;
+typedef unsigned long long *__restrict__ pU64_t;
 
 extern void abort ();