arm.md (*addsi3_carryin_compare0_<optab>): New pattern.

	* config/arm/arm.md (*addsi3_carryin_compare0_<optab>): New pattern.
	(peephole2 for conditional move): Generate 16 bit instructions.

	* gcc.target/arm/pr46975.c: New testcase.

From-SVN: r174854

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 76053c9eed7b76693e1ee52f82f58b3013a206bd..29dcf554fc79af7b1f11a8c4f506882715e63928 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2011-06-09  Wei Guozhi  <carrot@google.com>
+
+       PR target/46975
+       * config/arm/arm.md (*addsi3_carryin_compare0_<optab>): New pattern.
+       (peephole2 for conditional move): Generate 16 bit instructions.
+
 2011-06-09  Uros Bizjak  <ubizjak@gmail.com>
 
        * config/i386/i386.md (*movdi_internal_rex64): Merge

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 4e84826dd35bb01006c7d2b175d648126d808d57..70f703c3e7bd660b720e0724338f9c77814f73f5 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -985,6 +985,17 @@
                      (const_string "alu_shift_reg")))]
 )
 
+(define_insn "*addsi3_carryin_clobercc_<optab>"
+  [(set (match_operand:SI 0 "s_register_operand" "=r")
+       (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r")
+                         (match_operand:SI 2 "arm_rhs_operand" "rI"))
+                (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))
+   (clobber (reg:CC CC_REGNUM))]
+   "TARGET_32BIT"
+   "adc%.\\t%0, %1, %2"
+   [(set_attr "conds" "set")]
+)
+
 (define_expand "incscc"
   [(set (match_operand:SI 0 "s_register_operand" "=r,r")
         (plus:SI (match_operator:SI 2 "arm_comparison_operator"
@@ -8873,14 +8884,19 @@
              (set (match_dup 0) (const_int 1)))
    (match_scratch:SI 3 "r")]
   "TARGET_32BIT"
-  [(set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
+  [(parallel
+    [(set (reg:CC CC_REGNUM)
+         (compare:CC (match_dup 1) (match_dup 2)))
+     (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))])
    (parallel
     [(set (reg:CC CC_REGNUM)
          (compare:CC (const_int 0) (match_dup 3)))
      (set (match_dup 0) (minus:SI (const_int 0) (match_dup 3)))])
-   (set (match_dup 0)
-       (plus:SI (plus:SI (match_dup 0) (match_dup 3))
-                (geu:SI (reg:CC CC_REGNUM) (const_int 0))))])
+   (parallel
+    [(set (match_dup 0)
+         (plus:SI (plus:SI (match_dup 0) (match_dup 3))
+                  (geu:SI (reg:CC CC_REGNUM) (const_int 0))))
+     (clobber (reg:CC CC_REGNUM))])])
 
 (define_insn "*cond_move"
   [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 12f41f641ab784b99aee8abd02c1d2330881396c..f84baa1221ae0dc265aaf94d12f77e25984ed65c 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2011-06-09  Wei Guozhi  <carrot@google.com>
+
+       PR target/46975
+       * gcc.target/arm/pr46975.c: New testcase.
+
 2011-06-09  Nicola Pero  <nicola.pero@meta-innovation.com>
 
        * objc-obj-c++-shared/objc-test-suite-next-encode-assist.h

diff --git a/gcc/testsuite/gcc.target/arm/pr46975.c b/gcc/testsuite/gcc.target/arm/pr46975.c
new file mode 100644 (file)
index 0000000..60d773b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr46975.c
@@ -0,0 +1,9 @@
+/* { dg-options "-mthumb -Os" } */
+/* { dg-require-effective-target arm_thumb2_ok } */
+/* { dg-final { scan-assembler "subs" } } */
+/* { dg-final { scan-assembler "adcs" } } */
+
+int foo (int s)
+{
+      return s == 1;
+}