blorp/blorp_priv.h
COMMON_FILES = \
- common/brw_device_info.c \
- common/brw_device_info.h
+ common/gen_device_info.c \
+ common/gen_device_info.h
GENXML_GENERATED_FILES = \
genxml/gen4_pack.h \
brw_blorp_build_nir_shader(struct blorp_context *blorp,
const struct brw_blorp_blit_prog_key *key)
{
- const struct brw_device_info *devinfo = blorp->isl_dev->info;
+ const struct gen_device_info *devinfo = blorp->isl_dev->info;
nir_ssa_def *src_pos, *dst_pos, *color;
/* Sanity checks */
float dst_x1, float dst_y1,
GLenum filter, bool mirror_x, bool mirror_y)
{
- const struct brw_device_info *devinfo = batch->blorp->isl_dev->info;
+ const struct gen_device_info *devinfo = batch->blorp->isl_dev->info;
struct blorp_params params;
blorp_params_init(¶ms);
*/
#include "blorp_priv.h"
-#include "common/brw_device_info.h"
+#include "common/gen_device_info.h"
#include "intel_aub.h"
/**
+++ /dev/null
-/*
- * Copyright © 2013 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include "brw_device_info.h"
-
-static const struct brw_device_info brw_device_info_i965 = {
- .gen = 4,
- .has_negative_rhw_bug = true,
- .num_slices = 1,
- .max_vs_threads = 16,
- .max_gs_threads = 2,
- .max_wm_threads = 8 * 4,
- .urb = {
- .size = 256,
- },
-};
-
-static const struct brw_device_info brw_device_info_g4x = {
- .gen = 4,
- .has_pln = true,
- .has_compr4 = true,
- .has_surface_tile_offset = true,
- .is_g4x = true,
- .num_slices = 1,
- .max_vs_threads = 32,
- .max_gs_threads = 2,
- .max_wm_threads = 10 * 5,
- .urb = {
- .size = 384,
- },
-};
-
-static const struct brw_device_info brw_device_info_ilk = {
- .gen = 5,
- .has_pln = true,
- .has_compr4 = true,
- .has_surface_tile_offset = true,
- .num_slices = 1,
- .max_vs_threads = 72,
- .max_gs_threads = 32,
- .max_wm_threads = 12 * 6,
- .urb = {
- .size = 1024,
- },
-};
-
-static const struct brw_device_info brw_device_info_snb_gt1 = {
- .gen = 6,
- .gt = 1,
- .has_hiz_and_separate_stencil = true,
- .has_llc = true,
- .has_pln = true,
- .has_surface_tile_offset = true,
- .needs_unlit_centroid_workaround = true,
- .num_slices = 1,
- .max_vs_threads = 24,
- .max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
- .max_wm_threads = 40,
- .urb = {
- .size = 32,
- .min_vs_entries = 24,
- .max_vs_entries = 256,
- .max_gs_entries = 256,
- },
-};
-
-static const struct brw_device_info brw_device_info_snb_gt2 = {
- .gen = 6,
- .gt = 2,
- .has_hiz_and_separate_stencil = true,
- .has_llc = true,
- .has_pln = true,
- .has_surface_tile_offset = true,
- .needs_unlit_centroid_workaround = true,
- .num_slices = 1,
- .max_vs_threads = 60,
- .max_gs_threads = 60,
- .max_wm_threads = 80,
- .urb = {
- .size = 64,
- .min_vs_entries = 24,
- .max_vs_entries = 256,
- .max_gs_entries = 256,
- },
-};
-
-#define GEN7_FEATURES \
- .gen = 7, \
- .has_hiz_and_separate_stencil = true, \
- .must_use_separate_stencil = true, \
- .has_llc = true, \
- .has_pln = true, \
- .has_surface_tile_offset = true
-
-static const struct brw_device_info brw_device_info_ivb_gt1 = {
- GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
- .num_slices = 1,
- .max_vs_threads = 36,
- .max_hs_threads = 36,
- .max_ds_threads = 36,
- .max_gs_threads = 36,
- .max_wm_threads = 48,
- .max_cs_threads = 36,
- .urb = {
- .size = 128,
- .min_vs_entries = 32,
- .max_vs_entries = 512,
- .max_hs_entries = 32,
- .min_ds_entries = 10,
- .max_ds_entries = 288,
- .max_gs_entries = 192,
- },
-};
-
-static const struct brw_device_info brw_device_info_ivb_gt2 = {
- GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
- .num_slices = 1,
- .max_vs_threads = 128,
- .max_hs_threads = 128,
- .max_ds_threads = 128,
- .max_gs_threads = 128,
- .max_wm_threads = 172,
- .max_cs_threads = 64,
- .urb = {
- .size = 256,
- .min_vs_entries = 32,
- .max_vs_entries = 704,
- .max_hs_entries = 64,
- .min_ds_entries = 10,
- .max_ds_entries = 448,
- .max_gs_entries = 320,
- },
-};
-
-static const struct brw_device_info brw_device_info_byt = {
- GEN7_FEATURES, .is_baytrail = true, .gt = 1,
- .num_slices = 1,
- .has_llc = false,
- .max_vs_threads = 36,
- .max_hs_threads = 36,
- .max_ds_threads = 36,
- .max_gs_threads = 36,
- .max_wm_threads = 48,
- .max_cs_threads = 32,
- .urb = {
- .size = 128,
- .min_vs_entries = 32,
- .max_vs_entries = 512,
- .max_hs_entries = 32,
- .min_ds_entries = 10,
- .max_ds_entries = 288,
- .max_gs_entries = 192,
- },
-};
-
-#define HSW_FEATURES \
- GEN7_FEATURES, \
- .is_haswell = true, \
- .supports_simd16_3src = true, \
- .has_resource_streamer = true
-
-static const struct brw_device_info brw_device_info_hsw_gt1 = {
- HSW_FEATURES, .gt = 1,
- .num_slices = 1,
- .max_vs_threads = 70,
- .max_hs_threads = 70,
- .max_ds_threads = 70,
- .max_gs_threads = 70,
- .max_wm_threads = 102,
- .max_cs_threads = 70,
- .urb = {
- .size = 128,
- .min_vs_entries = 32,
- .max_vs_entries = 640,
- .max_hs_entries = 64,
- .min_ds_entries = 10,
- .max_ds_entries = 384,
- .max_gs_entries = 256,
- },
-};
-
-static const struct brw_device_info brw_device_info_hsw_gt2 = {
- HSW_FEATURES, .gt = 2,
- .num_slices = 1,
- .max_vs_threads = 280,
- .max_hs_threads = 256,
- .max_ds_threads = 280,
- .max_gs_threads = 256,
- .max_wm_threads = 204,
- .max_cs_threads = 70,
- .urb = {
- .size = 256,
- .min_vs_entries = 64,
- .max_vs_entries = 1664,
- .max_hs_entries = 128,
- .min_ds_entries = 10,
- .max_ds_entries = 960,
- .max_gs_entries = 640,
- },
-};
-
-static const struct brw_device_info brw_device_info_hsw_gt3 = {
- HSW_FEATURES, .gt = 3,
- .num_slices = 2,
- .max_vs_threads = 280,
- .max_hs_threads = 256,
- .max_ds_threads = 280,
- .max_gs_threads = 256,
- .max_wm_threads = 408,
- .max_cs_threads = 70,
- .urb = {
- .size = 512,
- .min_vs_entries = 64,
- .max_vs_entries = 1664,
- .max_hs_entries = 128,
- .min_ds_entries = 10,
- .max_ds_entries = 960,
- .max_gs_entries = 640,
- },
-};
-
-#define GEN8_FEATURES \
- .gen = 8, \
- .has_hiz_and_separate_stencil = true, \
- .has_resource_streamer = true, \
- .must_use_separate_stencil = true, \
- .has_llc = true, \
- .has_pln = true, \
- .supports_simd16_3src = true, \
- .has_surface_tile_offset = true, \
- .max_vs_threads = 504, \
- .max_hs_threads = 504, \
- .max_ds_threads = 504, \
- .max_gs_threads = 504, \
- .max_wm_threads = 384
-
-static const struct brw_device_info brw_device_info_bdw_gt1 = {
- GEN8_FEATURES, .gt = 1,
- .num_slices = 1,
- .max_cs_threads = 42,
- .urb = {
- .size = 192,
- .min_vs_entries = 64,
- .max_vs_entries = 2560,
- .max_hs_entries = 504,
- .min_ds_entries = 34,
- .max_ds_entries = 1536,
- .max_gs_entries = 960,
- }
-};
-
-static const struct brw_device_info brw_device_info_bdw_gt2 = {
- GEN8_FEATURES, .gt = 2,
- .num_slices = 1,
- .max_cs_threads = 56,
- .urb = {
- .size = 384,
- .min_vs_entries = 64,
- .max_vs_entries = 2560,
- .max_hs_entries = 504,
- .min_ds_entries = 34,
- .max_ds_entries = 1536,
- .max_gs_entries = 960,
- }
-};
-
-static const struct brw_device_info brw_device_info_bdw_gt3 = {
- GEN8_FEATURES, .gt = 3,
- .num_slices = 2,
- .max_cs_threads = 56,
- .urb = {
- .size = 384,
- .min_vs_entries = 64,
- .max_vs_entries = 2560,
- .max_hs_entries = 504,
- .min_ds_entries = 34,
- .max_ds_entries = 1536,
- .max_gs_entries = 960,
- }
-};
-
-static const struct brw_device_info brw_device_info_chv = {
- GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
- .has_llc = false,
- .num_slices = 1,
- .max_vs_threads = 80,
- .max_hs_threads = 80,
- .max_ds_threads = 80,
- .max_gs_threads = 80,
- .max_wm_threads = 128,
- .max_cs_threads = 6 * 7,
- .urb = {
- .size = 192,
- .min_vs_entries = 34,
- .max_vs_entries = 640,
- .max_hs_entries = 80,
- .min_ds_entries = 34,
- .max_ds_entries = 384,
- .max_gs_entries = 256,
- }
-};
-
-#define GEN9_FEATURES \
- .gen = 9, \
- .has_hiz_and_separate_stencil = true, \
- .has_resource_streamer = true, \
- .must_use_separate_stencil = true, \
- .has_llc = true, \
- .has_pln = true, \
- .supports_simd16_3src = true, \
- .has_surface_tile_offset = true, \
- .max_vs_threads = 336, \
- .max_gs_threads = 336, \
- .max_hs_threads = 336, \
- .max_ds_threads = 336, \
- .max_wm_threads = 64 * 9, \
- .max_cs_threads = 56, \
- .urb = { \
- .size = 384, \
- .min_vs_entries = 64, \
- .max_vs_entries = 1856, \
- .max_hs_entries = 672, \
- .min_ds_entries = 34, \
- .max_ds_entries = 1120, \
- .max_gs_entries = 640, \
- }
-
-static const struct brw_device_info brw_device_info_skl_gt1 = {
- GEN9_FEATURES, .gt = 1,
- .num_slices = 1,
- .urb.size = 192,
-};
-
-static const struct brw_device_info brw_device_info_skl_gt2 = {
- GEN9_FEATURES, .gt = 2,
- .num_slices = 1,
-};
-
-static const struct brw_device_info brw_device_info_skl_gt3 = {
- GEN9_FEATURES, .gt = 3,
- .num_slices = 2,
-};
-
-static const struct brw_device_info brw_device_info_skl_gt4 = {
- GEN9_FEATURES, .gt = 4,
- .num_slices = 3,
- /* From the "L3 Allocation and Programming" documentation:
- *
- * "URB is limited to 1008KB due to programming restrictions. This is not a
- * restriction of the L3 implementation, but of the FF and other clients.
- * Therefore, in a GT4 implementation it is possible for the programmed
- * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
- * only 1008KB of this will be used."
- */
- .urb.size = 1008 / 3,
-};
-
-static const struct brw_device_info brw_device_info_bxt = {
- GEN9_FEATURES,
- .is_broxton = 1,
- .gt = 1,
- .has_llc = false,
-
- .num_slices = 1,
- .max_vs_threads = 112,
- .max_hs_threads = 112,
- .max_ds_threads = 112,
- .max_gs_threads = 112,
- .max_wm_threads = 64 * 3,
- .max_cs_threads = 6 * 6,
- .urb = {
- .size = 192,
- .min_vs_entries = 34,
- .max_vs_entries = 704,
- .max_hs_entries = 256,
- .max_ds_entries = 416,
- .max_gs_entries = 256,
- }
-};
-
-static const struct brw_device_info brw_device_info_bxt_2x6 = {
- GEN9_FEATURES,
- .is_broxton = 1,
- .gt = 1,
- .has_llc = false,
-
- .num_slices = 1,
- .max_vs_threads = 56, /* XXX: guess */
- .max_hs_threads = 56, /* XXX: guess */
- .max_ds_threads = 56,
- .max_gs_threads = 56,
- .max_wm_threads = 64 * 2,
- .max_cs_threads = 6 * 6,
- .urb = {
- .size = 128,
- .min_vs_entries = 34,
- .max_vs_entries = 352,
- .max_hs_entries = 128,
- .max_ds_entries = 208,
- .max_gs_entries = 128,
- }
-};
-/*
- * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
- * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
- */
-
-/*
- * Both SKL and KBL support a maximum of 64 threads per
- * Pixel Shader Dispatch (PSD) unit.
- */
-#define KBL_MAX_THREADS_PER_PSD 64
-
-static const struct brw_device_info brw_device_info_kbl_gt1 = {
- GEN9_FEATURES,
- .gt = 1,
-
- .max_cs_threads = 7 * 6,
- .max_wm_threads = KBL_MAX_THREADS_PER_PSD * 2,
- .urb.size = 192,
- .num_slices = 1,
-};
-
-static const struct brw_device_info brw_device_info_kbl_gt1_5 = {
- GEN9_FEATURES,
- .gt = 1,
-
- .max_cs_threads = 7 * 6,
- .max_wm_threads = KBL_MAX_THREADS_PER_PSD * 3,
- .num_slices = 1,
-};
-
-static const struct brw_device_info brw_device_info_kbl_gt2 = {
- GEN9_FEATURES,
- .gt = 2,
-
- .max_wm_threads = KBL_MAX_THREADS_PER_PSD * 3,
- .num_slices = 1,
-};
-
-static const struct brw_device_info brw_device_info_kbl_gt3 = {
- GEN9_FEATURES,
- .gt = 3,
-
- .max_wm_threads = KBL_MAX_THREADS_PER_PSD * 6,
- .num_slices = 2,
-};
-
-static const struct brw_device_info brw_device_info_kbl_gt4 = {
- GEN9_FEATURES,
- .gt = 4,
-
- .max_wm_threads = KBL_MAX_THREADS_PER_PSD * 9,
- /*
- * From the "L3 Allocation and Programming" documentation:
- *
- * "URB is limited to 1008KB due to programming restrictions. This
- * is not a restriction of the L3 implementation, but of the FF and
- * other clients. Therefore, in a GT4 implementation it is
- * possible for the programmed allocation of the L3 data array to
- * provide 3*384KB=1152KB for URB, but only 1008KB of this
- * will be used."
- */
- .urb.size = 1008 / 3,
- .num_slices = 3,
-};
-
-const struct brw_device_info *
-brw_get_device_info(int devid)
-{
- const struct brw_device_info *devinfo;
- switch (devid) {
-#undef CHIPSET
-#define CHIPSET(id, family, name) \
- case id: devinfo = &brw_device_info_##family; break;
-#include "pci_ids/i965_pci_ids.h"
- default:
- fprintf(stderr, "i965_dri.so does not support the 0x%x PCI ID.\n", devid);
- return NULL;
- }
-
- return devinfo;
-}
-
-const char *
-brw_get_device_name(int devid)
-{
- switch (devid) {
-#undef CHIPSET
-#define CHIPSET(id, family, name) case id: return name;
-#include "pci_ids/i965_pci_ids.h"
- default:
- return NULL;
- }
-}
+++ /dev/null
- /*
- * Copyright © 2013 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- */
-
-#pragma once
-#include <stdbool.h>
-
-/**
- * Intel hardware information and quirks
- */
-struct brw_device_info
-{
- int gen; /**< Generation number: 4, 5, 6, 7, ... */
- int gt;
-
- bool is_g4x;
- bool is_ivybridge;
- bool is_baytrail;
- bool is_haswell;
- bool is_cherryview;
- bool is_broxton;
-
- bool has_hiz_and_separate_stencil;
- bool must_use_separate_stencil;
-
- bool has_llc;
-
- bool has_pln;
- bool has_compr4;
- bool has_surface_tile_offset;
- bool supports_simd16_3src;
- bool has_resource_streamer;
-
- /**
- * \name Intel hardware quirks
- * @{
- */
- bool has_negative_rhw_bug;
-
- /**
- * Some versions of Gen hardware don't do centroid interpolation correctly
- * on unlit pixels, causing incorrect values for derivatives near triangle
- * edges. Enabling this flag causes the fragment shader to use
- * non-centroid interpolation for unlit pixels, at the expense of two extra
- * fragment shader instructions.
- */
- bool needs_unlit_centroid_workaround;
- /** @} */
-
- /**
- * \name GPU hardware limits
- *
- * In general, you can find shader thread maximums by looking at the "Maximum
- * Number of Threads" field in the Intel PRM description of the 3DSTATE_VS,
- * 3DSTATE_GS, 3DSTATE_HS, 3DSTATE_DS, and 3DSTATE_PS commands. URB entry
- * limits come from the "Number of URB Entries" field in the
- * 3DSTATE_URB_VS command and friends.
- *
- * These fields are used to calculate the scratch space to allocate. The
- * amount of scratch space can be larger without being harmful on modern
- * GPUs, however, prior to Haswell, programming the maximum number of threads
- * to greater than the hardware maximum would cause GPU performance to tank.
- *
- * @{
- */
- /**
- * Total number of slices present on the device whether or not they've been
- * fused off.
- *
- * XXX: CS thread counts are limited by the inability to do cross subslice
- * communication. It is the effectively the number of logical threads which
- * can be executed in a subslice. Fuse configurations may cause this number
- * to change, so we program @max_cs_threads as the lower maximum.
- */
- unsigned num_slices;
- unsigned max_vs_threads; /**< Maximum Vertex Shader threads */
- unsigned max_hs_threads; /**< Maximum Hull Shader threads */
- unsigned max_ds_threads; /**< Maximum Domain Shader threads */
- unsigned max_gs_threads; /**< Maximum Geometry Shader threads. */
- /**
- * Theoretical maximum number of Pixel Shader threads.
- *
- * PSD means Pixel Shader Dispatcher. On modern Intel GPUs, hardware will
- * automatically scale pixel shader thread count, based on a single value
- * programmed into 3DSTATE_PS.
- *
- * To calculate the maximum number of threads for Gen8 beyond (which have
- * multiple Pixel Shader Dispatchers):
- *
- * - Look up 3DSTATE_PS and find "Maximum Number of Threads Per PSD"
- * - Usually there's only one PSD per subslice, so use the number of
- * subslices for number of PSDs.
- * - For max_wm_threads, the total should be PSD threads * #PSDs.
- */
- unsigned max_wm_threads;
-
- /**
- * Maximum Compute Shader threads.
- *
- * Thread count * number of EUs per subslice
- */
- unsigned max_cs_threads;
-
- struct {
- /**
- * Hardware default URB size.
- *
- * The units this is expressed in are somewhat inconsistent: 512b units
- * on Gen4-5, KB on Gen6-7, and KB times the slice count on Gen8+.
- *
- * Look up "URB Size" in the "Device Attributes" page, and take the
- * maximum. Look up the slice count for each GT SKU on the same page.
- * urb.size = URB Size (kbytes) / slice count
- */
- unsigned size;
- unsigned min_vs_entries;
- unsigned max_vs_entries;
- unsigned max_hs_entries;
- unsigned min_ds_entries;
- unsigned max_ds_entries;
- unsigned max_gs_entries;
- } urb;
- /** @} */
-};
-
-const struct brw_device_info *brw_get_device_info(int devid);
-const char *brw_get_device_name(int devid);
--- /dev/null
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "gen_device_info.h"
+
+static const struct gen_device_info gen_device_info_i965 = {
+ .gen = 4,
+ .has_negative_rhw_bug = true,
+ .num_slices = 1,
+ .max_vs_threads = 16,
+ .max_gs_threads = 2,
+ .max_wm_threads = 8 * 4,
+ .urb = {
+ .size = 256,
+ },
+};
+
+static const struct gen_device_info gen_device_info_g4x = {
+ .gen = 4,
+ .has_pln = true,
+ .has_compr4 = true,
+ .has_surface_tile_offset = true,
+ .is_g4x = true,
+ .num_slices = 1,
+ .max_vs_threads = 32,
+ .max_gs_threads = 2,
+ .max_wm_threads = 10 * 5,
+ .urb = {
+ .size = 384,
+ },
+};
+
+static const struct gen_device_info gen_device_info_ilk = {
+ .gen = 5,
+ .has_pln = true,
+ .has_compr4 = true,
+ .has_surface_tile_offset = true,
+ .num_slices = 1,
+ .max_vs_threads = 72,
+ .max_gs_threads = 32,
+ .max_wm_threads = 12 * 6,
+ .urb = {
+ .size = 1024,
+ },
+};
+
+static const struct gen_device_info gen_device_info_snb_gt1 = {
+ .gen = 6,
+ .gt = 1,
+ .has_hiz_and_separate_stencil = true,
+ .has_llc = true,
+ .has_pln = true,
+ .has_surface_tile_offset = true,
+ .needs_unlit_centroid_workaround = true,
+ .num_slices = 1,
+ .max_vs_threads = 24,
+ .max_gs_threads = 21, /* conservative; 24 if rendering disabled. */
+ .max_wm_threads = 40,
+ .urb = {
+ .size = 32,
+ .min_vs_entries = 24,
+ .max_vs_entries = 256,
+ .max_gs_entries = 256,
+ },
+};
+
+static const struct gen_device_info gen_device_info_snb_gt2 = {
+ .gen = 6,
+ .gt = 2,
+ .has_hiz_and_separate_stencil = true,
+ .has_llc = true,
+ .has_pln = true,
+ .has_surface_tile_offset = true,
+ .needs_unlit_centroid_workaround = true,
+ .num_slices = 1,
+ .max_vs_threads = 60,
+ .max_gs_threads = 60,
+ .max_wm_threads = 80,
+ .urb = {
+ .size = 64,
+ .min_vs_entries = 24,
+ .max_vs_entries = 256,
+ .max_gs_entries = 256,
+ },
+};
+
+#define GEN7_FEATURES \
+ .gen = 7, \
+ .has_hiz_and_separate_stencil = true, \
+ .must_use_separate_stencil = true, \
+ .has_llc = true, \
+ .has_pln = true, \
+ .has_surface_tile_offset = true
+
+static const struct gen_device_info gen_device_info_ivb_gt1 = {
+ GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
+ .num_slices = 1,
+ .max_vs_threads = 36,
+ .max_hs_threads = 36,
+ .max_ds_threads = 36,
+ .max_gs_threads = 36,
+ .max_wm_threads = 48,
+ .max_cs_threads = 36,
+ .urb = {
+ .size = 128,
+ .min_vs_entries = 32,
+ .max_vs_entries = 512,
+ .max_hs_entries = 32,
+ .min_ds_entries = 10,
+ .max_ds_entries = 288,
+ .max_gs_entries = 192,
+ },
+};
+
+static const struct gen_device_info gen_device_info_ivb_gt2 = {
+ GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
+ .num_slices = 1,
+ .max_vs_threads = 128,
+ .max_hs_threads = 128,
+ .max_ds_threads = 128,
+ .max_gs_threads = 128,
+ .max_wm_threads = 172,
+ .max_cs_threads = 64,
+ .urb = {
+ .size = 256,
+ .min_vs_entries = 32,
+ .max_vs_entries = 704,
+ .max_hs_entries = 64,
+ .min_ds_entries = 10,
+ .max_ds_entries = 448,
+ .max_gs_entries = 320,
+ },
+};
+
+static const struct gen_device_info gen_device_info_byt = {
+ GEN7_FEATURES, .is_baytrail = true, .gt = 1,
+ .num_slices = 1,
+ .has_llc = false,
+ .max_vs_threads = 36,
+ .max_hs_threads = 36,
+ .max_ds_threads = 36,
+ .max_gs_threads = 36,
+ .max_wm_threads = 48,
+ .max_cs_threads = 32,
+ .urb = {
+ .size = 128,
+ .min_vs_entries = 32,
+ .max_vs_entries = 512,
+ .max_hs_entries = 32,
+ .min_ds_entries = 10,
+ .max_ds_entries = 288,
+ .max_gs_entries = 192,
+ },
+};
+
+#define HSW_FEATURES \
+ GEN7_FEATURES, \
+ .is_haswell = true, \
+ .supports_simd16_3src = true, \
+ .has_resource_streamer = true
+
+static const struct gen_device_info gen_device_info_hsw_gt1 = {
+ HSW_FEATURES, .gt = 1,
+ .num_slices = 1,
+ .max_vs_threads = 70,
+ .max_hs_threads = 70,
+ .max_ds_threads = 70,
+ .max_gs_threads = 70,
+ .max_wm_threads = 102,
+ .max_cs_threads = 70,
+ .urb = {
+ .size = 128,
+ .min_vs_entries = 32,
+ .max_vs_entries = 640,
+ .max_hs_entries = 64,
+ .min_ds_entries = 10,
+ .max_ds_entries = 384,
+ .max_gs_entries = 256,
+ },
+};
+
+static const struct gen_device_info gen_device_info_hsw_gt2 = {
+ HSW_FEATURES, .gt = 2,
+ .num_slices = 1,
+ .max_vs_threads = 280,
+ .max_hs_threads = 256,
+ .max_ds_threads = 280,
+ .max_gs_threads = 256,
+ .max_wm_threads = 204,
+ .max_cs_threads = 70,
+ .urb = {
+ .size = 256,
+ .min_vs_entries = 64,
+ .max_vs_entries = 1664,
+ .max_hs_entries = 128,
+ .min_ds_entries = 10,
+ .max_ds_entries = 960,
+ .max_gs_entries = 640,
+ },
+};
+
+static const struct gen_device_info gen_device_info_hsw_gt3 = {
+ HSW_FEATURES, .gt = 3,
+ .num_slices = 2,
+ .max_vs_threads = 280,
+ .max_hs_threads = 256,
+ .max_ds_threads = 280,
+ .max_gs_threads = 256,
+ .max_wm_threads = 408,
+ .max_cs_threads = 70,
+ .urb = {
+ .size = 512,
+ .min_vs_entries = 64,
+ .max_vs_entries = 1664,
+ .max_hs_entries = 128,
+ .min_ds_entries = 10,
+ .max_ds_entries = 960,
+ .max_gs_entries = 640,
+ },
+};
+
+#define GEN8_FEATURES \
+ .gen = 8, \
+ .has_hiz_and_separate_stencil = true, \
+ .has_resource_streamer = true, \
+ .must_use_separate_stencil = true, \
+ .has_llc = true, \
+ .has_pln = true, \
+ .supports_simd16_3src = true, \
+ .has_surface_tile_offset = true, \
+ .max_vs_threads = 504, \
+ .max_hs_threads = 504, \
+ .max_ds_threads = 504, \
+ .max_gs_threads = 504, \
+ .max_wm_threads = 384
+
+static const struct gen_device_info gen_device_info_bdw_gt1 = {
+ GEN8_FEATURES, .gt = 1,
+ .num_slices = 1,
+ .max_cs_threads = 42,
+ .urb = {
+ .size = 192,
+ .min_vs_entries = 64,
+ .max_vs_entries = 2560,
+ .max_hs_entries = 504,
+ .min_ds_entries = 34,
+ .max_ds_entries = 1536,
+ .max_gs_entries = 960,
+ }
+};
+
+static const struct gen_device_info gen_device_info_bdw_gt2 = {
+ GEN8_FEATURES, .gt = 2,
+ .num_slices = 1,
+ .max_cs_threads = 56,
+ .urb = {
+ .size = 384,
+ .min_vs_entries = 64,
+ .max_vs_entries = 2560,
+ .max_hs_entries = 504,
+ .min_ds_entries = 34,
+ .max_ds_entries = 1536,
+ .max_gs_entries = 960,
+ }
+};
+
+static const struct gen_device_info gen_device_info_bdw_gt3 = {
+ GEN8_FEATURES, .gt = 3,
+ .num_slices = 2,
+ .max_cs_threads = 56,
+ .urb = {
+ .size = 384,
+ .min_vs_entries = 64,
+ .max_vs_entries = 2560,
+ .max_hs_entries = 504,
+ .min_ds_entries = 34,
+ .max_ds_entries = 1536,
+ .max_gs_entries = 960,
+ }
+};
+
+static const struct gen_device_info gen_device_info_chv = {
+ GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
+ .has_llc = false,
+ .num_slices = 1,
+ .max_vs_threads = 80,
+ .max_hs_threads = 80,
+ .max_ds_threads = 80,
+ .max_gs_threads = 80,
+ .max_wm_threads = 128,
+ .max_cs_threads = 6 * 7,
+ .urb = {
+ .size = 192,
+ .min_vs_entries = 34,
+ .max_vs_entries = 640,
+ .max_hs_entries = 80,
+ .min_ds_entries = 34,
+ .max_ds_entries = 384,
+ .max_gs_entries = 256,
+ }
+};
+
+#define GEN9_FEATURES \
+ .gen = 9, \
+ .has_hiz_and_separate_stencil = true, \
+ .has_resource_streamer = true, \
+ .must_use_separate_stencil = true, \
+ .has_llc = true, \
+ .has_pln = true, \
+ .supports_simd16_3src = true, \
+ .has_surface_tile_offset = true, \
+ .max_vs_threads = 336, \
+ .max_gs_threads = 336, \
+ .max_hs_threads = 336, \
+ .max_ds_threads = 336, \
+ .max_wm_threads = 64 * 9, \
+ .max_cs_threads = 56, \
+ .urb = { \
+ .size = 384, \
+ .min_vs_entries = 64, \
+ .max_vs_entries = 1856, \
+ .max_hs_entries = 672, \
+ .min_ds_entries = 34, \
+ .max_ds_entries = 1120, \
+ .max_gs_entries = 640, \
+ }
+
+static const struct gen_device_info gen_device_info_skl_gt1 = {
+ GEN9_FEATURES, .gt = 1,
+ .num_slices = 1,
+ .urb.size = 192,
+};
+
+static const struct gen_device_info gen_device_info_skl_gt2 = {
+ GEN9_FEATURES, .gt = 2,
+ .num_slices = 1,
+};
+
+static const struct gen_device_info gen_device_info_skl_gt3 = {
+ GEN9_FEATURES, .gt = 3,
+ .num_slices = 2,
+};
+
+static const struct gen_device_info gen_device_info_skl_gt4 = {
+ GEN9_FEATURES, .gt = 4,
+ .num_slices = 3,
+ /* From the "L3 Allocation and Programming" documentation:
+ *
+ * "URB is limited to 1008KB due to programming restrictions. This is not a
+ * restriction of the L3 implementation, but of the FF and other clients.
+ * Therefore, in a GT4 implementation it is possible for the programmed
+ * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
+ * only 1008KB of this will be used."
+ */
+ .urb.size = 1008 / 3,
+};
+
+static const struct gen_device_info gen_device_info_bxt = {
+ GEN9_FEATURES,
+ .is_broxton = 1,
+ .gt = 1,
+ .has_llc = false,
+
+ .num_slices = 1,
+ .max_vs_threads = 112,
+ .max_hs_threads = 112,
+ .max_ds_threads = 112,
+ .max_gs_threads = 112,
+ .max_wm_threads = 64 * 3,
+ .max_cs_threads = 6 * 6,
+ .urb = {
+ .size = 192,
+ .min_vs_entries = 34,
+ .max_vs_entries = 704,
+ .max_hs_entries = 256,
+ .max_ds_entries = 416,
+ .max_gs_entries = 256,
+ }
+};
+
+static const struct gen_device_info gen_device_info_bxt_2x6 = {
+ GEN9_FEATURES,
+ .is_broxton = 1,
+ .gt = 1,
+ .has_llc = false,
+
+ .num_slices = 1,
+ .max_vs_threads = 56, /* XXX: guess */
+ .max_hs_threads = 56, /* XXX: guess */
+ .max_ds_threads = 56,
+ .max_gs_threads = 56,
+ .max_wm_threads = 64 * 2,
+ .max_cs_threads = 6 * 6,
+ .urb = {
+ .size = 128,
+ .min_vs_entries = 34,
+ .max_vs_entries = 352,
+ .max_hs_entries = 128,
+ .max_ds_entries = 208,
+ .max_gs_entries = 128,
+ }
+};
+/*
+ * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
+ * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
+ */
+
+/*
+ * Both SKL and KBL support a maximum of 64 threads per
+ * Pixel Shader Dispatch (PSD) unit.
+ */
+#define KBL_MAX_THREADS_PER_PSD 64
+
+static const struct gen_device_info gen_device_info_kbl_gt1 = {
+ GEN9_FEATURES,
+ .gt = 1,
+
+ .max_cs_threads = 7 * 6,
+ .max_wm_threads = KBL_MAX_THREADS_PER_PSD * 2,
+ .urb.size = 192,
+ .num_slices = 1,
+};
+
+static const struct gen_device_info gen_device_info_kbl_gt1_5 = {
+ GEN9_FEATURES,
+ .gt = 1,
+
+ .max_cs_threads = 7 * 6,
+ .max_wm_threads = KBL_MAX_THREADS_PER_PSD * 3,
+ .num_slices = 1,
+};
+
+static const struct gen_device_info gen_device_info_kbl_gt2 = {
+ GEN9_FEATURES,
+ .gt = 2,
+
+ .max_wm_threads = KBL_MAX_THREADS_PER_PSD * 3,
+ .num_slices = 1,
+};
+
+static const struct gen_device_info gen_device_info_kbl_gt3 = {
+ GEN9_FEATURES,
+ .gt = 3,
+
+ .max_wm_threads = KBL_MAX_THREADS_PER_PSD * 6,
+ .num_slices = 2,
+};
+
+static const struct gen_device_info gen_device_info_kbl_gt4 = {
+ GEN9_FEATURES,
+ .gt = 4,
+
+ .max_wm_threads = KBL_MAX_THREADS_PER_PSD * 9,
+ /*
+ * From the "L3 Allocation and Programming" documentation:
+ *
+ * "URB is limited to 1008KB due to programming restrictions. This
+ * is not a restriction of the L3 implementation, but of the FF and
+ * other clients. Therefore, in a GT4 implementation it is
+ * possible for the programmed allocation of the L3 data array to
+ * provide 3*384KB=1152KB for URB, but only 1008KB of this
+ * will be used."
+ */
+ .urb.size = 1008 / 3,
+ .num_slices = 3,
+};
+
+const struct gen_device_info *
+brw_get_device_info(int devid)
+{
+ const struct gen_device_info *devinfo;
+ switch (devid) {
+#undef CHIPSET
+#define CHIPSET(id, family, name) \
+ case id: devinfo = &gen_device_info_##family; break;
+#include "pci_ids/i965_pci_ids.h"
+ default:
+ fprintf(stderr, "i965_dri.so does not support the 0x%x PCI ID.\n", devid);
+ return NULL;
+ }
+
+ return devinfo;
+}
+
+const char *
+brw_get_device_name(int devid)
+{
+ switch (devid) {
+#undef CHIPSET
+#define CHIPSET(id, family, name) case id: return name;
+#include "pci_ids/i965_pci_ids.h"
+ default:
+ return NULL;
+ }
+}
--- /dev/null
+ /*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#pragma once
+#include <stdbool.h>
+
+/**
+ * Intel hardware information and quirks
+ */
+struct gen_device_info
+{
+ int gen; /**< Generation number: 4, 5, 6, 7, ... */
+ int gt;
+
+ bool is_g4x;
+ bool is_ivybridge;
+ bool is_baytrail;
+ bool is_haswell;
+ bool is_cherryview;
+ bool is_broxton;
+
+ bool has_hiz_and_separate_stencil;
+ bool must_use_separate_stencil;
+
+ bool has_llc;
+
+ bool has_pln;
+ bool has_compr4;
+ bool has_surface_tile_offset;
+ bool supports_simd16_3src;
+ bool has_resource_streamer;
+
+ /**
+ * \name Intel hardware quirks
+ * @{
+ */
+ bool has_negative_rhw_bug;
+
+ /**
+ * Some versions of Gen hardware don't do centroid interpolation correctly
+ * on unlit pixels, causing incorrect values for derivatives near triangle
+ * edges. Enabling this flag causes the fragment shader to use
+ * non-centroid interpolation for unlit pixels, at the expense of two extra
+ * fragment shader instructions.
+ */
+ bool needs_unlit_centroid_workaround;
+ /** @} */
+
+ /**
+ * \name GPU hardware limits
+ *
+ * In general, you can find shader thread maximums by looking at the "Maximum
+ * Number of Threads" field in the Intel PRM description of the 3DSTATE_VS,
+ * 3DSTATE_GS, 3DSTATE_HS, 3DSTATE_DS, and 3DSTATE_PS commands. URB entry
+ * limits come from the "Number of URB Entries" field in the
+ * 3DSTATE_URB_VS command and friends.
+ *
+ * These fields are used to calculate the scratch space to allocate. The
+ * amount of scratch space can be larger without being harmful on modern
+ * GPUs, however, prior to Haswell, programming the maximum number of threads
+ * to greater than the hardware maximum would cause GPU performance to tank.
+ *
+ * @{
+ */
+ /**
+ * Total number of slices present on the device whether or not they've been
+ * fused off.
+ *
+ * XXX: CS thread counts are limited by the inability to do cross subslice
+ * communication. It is the effectively the number of logical threads which
+ * can be executed in a subslice. Fuse configurations may cause this number
+ * to change, so we program @max_cs_threads as the lower maximum.
+ */
+ unsigned num_slices;
+ unsigned max_vs_threads; /**< Maximum Vertex Shader threads */
+ unsigned max_hs_threads; /**< Maximum Hull Shader threads */
+ unsigned max_ds_threads; /**< Maximum Domain Shader threads */
+ unsigned max_gs_threads; /**< Maximum Geometry Shader threads. */
+ /**
+ * Theoretical maximum number of Pixel Shader threads.
+ *
+ * PSD means Pixel Shader Dispatcher. On modern Intel GPUs, hardware will
+ * automatically scale pixel shader thread count, based on a single value
+ * programmed into 3DSTATE_PS.
+ *
+ * To calculate the maximum number of threads for Gen8 beyond (which have
+ * multiple Pixel Shader Dispatchers):
+ *
+ * - Look up 3DSTATE_PS and find "Maximum Number of Threads Per PSD"
+ * - Usually there's only one PSD per subslice, so use the number of
+ * subslices for number of PSDs.
+ * - For max_wm_threads, the total should be PSD threads * #PSDs.
+ */
+ unsigned max_wm_threads;
+
+ /**
+ * Maximum Compute Shader threads.
+ *
+ * Thread count * number of EUs per subslice
+ */
+ unsigned max_cs_threads;
+
+ struct {
+ /**
+ * Hardware default URB size.
+ *
+ * The units this is expressed in are somewhat inconsistent: 512b units
+ * on Gen4-5, KB on Gen6-7, and KB times the slice count on Gen8+.
+ *
+ * Look up "URB Size" in the "Device Attributes" page, and take the
+ * maximum. Look up the slice count for each GT SKU on the same page.
+ * urb.size = URB Size (kbytes) / slice count
+ */
+ unsigned size;
+ unsigned min_vs_entries;
+ unsigned max_vs_entries;
+ unsigned max_hs_entries;
+ unsigned min_ds_entries;
+ unsigned max_ds_entries;
+ unsigned max_gs_entries;
+ } urb;
+ /** @} */
+};
+
+const struct gen_device_info *brw_get_device_info(int devid);
+const char *brw_get_device_name(int devid);
void
isl_device_init(struct isl_device *dev,
- const struct brw_device_info *info,
+ const struct gen_device_info *info,
bool has_bit6_swizzling)
{
dev->info = info;
extern "C" {
#endif
-struct brw_device_info;
+struct gen_device_info;
struct brw_image_param;
#ifndef ISL_DEV_GEN
struct isl_device {
- const struct brw_device_info *info;
+ const struct gen_device_info *info;
bool use_separate_stencil;
bool has_bit6_swizzling;
};
void
isl_device_init(struct isl_device *dev,
- const struct brw_device_info *info,
+ const struct gen_device_info *info,
bool has_bit6_swizzling);
isl_sample_count_mask_t ATTRIBUTE_CONST
return isl_format_layouts[fmt].name;
}
-bool isl_format_supports_rendering(const struct brw_device_info *devinfo,
+bool isl_format_supports_rendering(const struct gen_device_info *devinfo,
enum isl_format format);
-bool isl_format_supports_alpha_blending(const struct brw_device_info *devinfo,
+bool isl_format_supports_alpha_blending(const struct gen_device_info *devinfo,
enum isl_format format);
-bool isl_format_supports_sampling(const struct brw_device_info *devinfo,
+bool isl_format_supports_sampling(const struct gen_device_info *devinfo,
enum isl_format format);
-bool isl_format_supports_filtering(const struct brw_device_info *devinfo,
+bool isl_format_supports_filtering(const struct gen_device_info *devinfo,
enum isl_format format);
-bool isl_format_supports_vertex_fetch(const struct brw_device_info *devinfo,
+bool isl_format_supports_vertex_fetch(const struct gen_device_info *devinfo,
enum isl_format format);
-bool isl_format_supports_lossless_compression(const struct brw_device_info *devinfo,
+bool isl_format_supports_lossless_compression(const struct gen_device_info *devinfo,
enum isl_format format);
bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
bool isl_is_storage_image_format(enum isl_format fmt);
enum isl_format
-isl_lower_storage_image_format(const struct brw_device_info *devinfo,
+isl_lower_storage_image_format(const struct gen_device_info *devinfo,
enum isl_format fmt);
/* Returns true if this hardware supports typed load/store on a format with
* the same size as the given format.
*/
bool
-isl_has_matching_typed_storage_image_format(const struct brw_device_info *devinfo,
+isl_has_matching_typed_storage_image_format(const struct gen_device_info *devinfo,
enum isl_format fmt);
static inline bool
#include <assert.h>
#include "isl.h"
-#include "common/brw_device_info.h"
+#include "common/gen_device_info.h"
struct surface_format_info {
bool exists;
#undef Y
static unsigned
-format_gen(const struct brw_device_info *devinfo)
+format_gen(const struct gen_device_info *devinfo)
{
return devinfo->gen * 10 + (devinfo->is_g4x || devinfo->is_haswell) * 5;
}
bool
-isl_format_supports_rendering(const struct brw_device_info *devinfo,
+isl_format_supports_rendering(const struct gen_device_info *devinfo,
enum isl_format format)
{
if (!format_info[format].exists)
}
bool
-isl_format_supports_alpha_blending(const struct brw_device_info *devinfo,
+isl_format_supports_alpha_blending(const struct gen_device_info *devinfo,
enum isl_format format)
{
if (!format_info[format].exists)
}
bool
-isl_format_supports_sampling(const struct brw_device_info *devinfo,
+isl_format_supports_sampling(const struct gen_device_info *devinfo,
enum isl_format format)
{
if (!format_info[format].exists)
}
bool
-isl_format_supports_filtering(const struct brw_device_info *devinfo,
+isl_format_supports_filtering(const struct gen_device_info *devinfo,
enum isl_format format)
{
if (!format_info[format].exists)
}
bool
-isl_format_supports_vertex_fetch(const struct brw_device_info *devinfo,
+isl_format_supports_vertex_fetch(const struct gen_device_info *devinfo,
enum isl_format format)
{
if (!format_info[format].exists)
}
bool
-isl_format_supports_lossless_compression(const struct brw_device_info *devinfo,
+isl_format_supports_lossless_compression(const struct gen_device_info *devinfo,
enum isl_format format)
{
if (!format_info[format].exists)
#include <assert.h>
#include <strings.h>
-#include "common/brw_device_info.h"
+#include "common/gen_device_info.h"
#include "util/macros.h"
#include "isl.h"
}
enum isl_format
-isl_lower_storage_image_format(const struct brw_device_info *devinfo,
+isl_lower_storage_image_format(const struct gen_device_info *devinfo,
enum isl_format format)
{
switch (format) {
}
bool
-isl_has_matching_typed_storage_image_format(const struct brw_device_info *devinfo,
+isl_has_matching_typed_storage_image_format(const struct gen_device_info *devinfo,
enum isl_format fmt)
{
if (devinfo->gen >= 9) {
#include <stdio.h>
#include <stdlib.h>
-#include "common/brw_device_info.h"
+#include "common/gen_device_info.h"
#include "isl/isl.h"
#include "isl/isl_priv.h"
uint64_t INTEL_DEBUG;
struct gen_disasm {
- struct brw_device_info devinfo;
+ struct gen_device_info devinfo;
};
void
gen_disasm_disassemble(struct gen_disasm *disasm, void *assembly, int start,
int end, FILE *out)
{
- struct brw_device_info *devinfo = &disasm->devinfo;
+ struct gen_device_info *devinfo = &disasm->devinfo;
bool dump_hex = false;
for (int offset = start; offset < end;) {
gen_disasm_create(int pciid)
{
struct gen_disasm *gd;
- const struct brw_device_info *dev_info = NULL;
+ const struct gen_device_info *dev_info = NULL;
gd = malloc(sizeof *gd);
if (gd == NULL)
if (size == 0) {
/* We own the lock. Allocate a buffer */
- struct brw_device_info *devinfo = &device->info;
+ struct gen_device_info *devinfo = &device->info;
uint32_t max_threads[] = {
[MESA_SHADER_VERTEX] = devinfo->max_vs_threads,
[MESA_SHADER_TESS_CTRL] = devinfo->max_hs_threads,
VkPhysicalDeviceProperties* pProperties)
{
ANV_FROM_HANDLE(anv_physical_device, pdevice, physicalDevice);
- const struct brw_device_info *devinfo = pdevice->info;
+ const struct gen_device_info *devinfo = pdevice->info;
const float time_stamp_base = devinfo->gen >= 9 ? 83.333 : 80.0;
print " };\n"
print "};\n"
- print "void anv_set_dispatch_devinfo(const struct brw_device_info *info);\n"
+ print "void anv_set_dispatch_devinfo(const struct gen_device_info *info);\n"
for type, name, args, num, h in entrypoints:
print_guard_start(name)
print "};\n"
print """
-static const struct brw_device_info *dispatch_devinfo;
+static const struct gen_device_info *dispatch_devinfo;
void
-anv_set_dispatch_devinfo(const struct brw_device_info *devinfo)
+anv_set_dispatch_devinfo(const struct gen_device_info *devinfo)
{
dispatch_devinfo = devinfo;
}
* Exactly one bit must be set in \a aspect.
*/
struct anv_format
-anv_get_format(const struct brw_device_info *devinfo, VkFormat vk_format,
+anv_get_format(const struct gen_device_info *devinfo, VkFormat vk_format,
VkImageAspectFlags aspect, VkImageTiling tiling)
{
struct anv_format format = anv_formats[vk_format];
// Format capabilities
static VkFormatFeatureFlags
-get_image_format_properties(const struct brw_device_info *devinfo,
+get_image_format_properties(const struct gen_device_info *devinfo,
enum isl_format base, struct anv_format format)
{
if (format.isl_format == ISL_FORMAT_UNSUPPORTED)
}
static VkFormatFeatureFlags
-get_buffer_format_properties(const struct brw_device_info *devinfo,
+get_buffer_format_properties(const struct gen_device_info *devinfo,
enum isl_format format)
{
if (format == ISL_FORMAT_UNSUPPORTED)
};
static void
-populate_sampler_prog_key(const struct brw_device_info *devinfo,
+populate_sampler_prog_key(const struct gen_device_info *devinfo,
struct brw_sampler_prog_key_data *key)
{
/* XXX: Handle texture swizzle on HSW- */
}
static void
-populate_vs_prog_key(const struct brw_device_info *devinfo,
+populate_vs_prog_key(const struct gen_device_info *devinfo,
struct brw_vs_prog_key *key)
{
memset(key, 0, sizeof(*key));
}
static void
-populate_gs_prog_key(const struct brw_device_info *devinfo,
+populate_gs_prog_key(const struct gen_device_info *devinfo,
struct brw_gs_prog_key *key)
{
memset(key, 0, sizeof(*key));
}
static void
-populate_wm_prog_key(const struct brw_device_info *devinfo,
+populate_wm_prog_key(const struct gen_device_info *devinfo,
const VkGraphicsPipelineCreateInfo *info,
const struct anv_graphics_pipeline_create_info *extra,
struct brw_wm_prog_key *key)
}
static void
-populate_cs_prog_key(const struct brw_device_info *devinfo,
+populate_cs_prog_key(const struct gen_device_info *devinfo,
struct brw_cs_prog_key *key)
{
memset(key, 0, sizeof(*key));
void
anv_setup_pipeline_l3_config(struct anv_pipeline *pipeline)
{
- const struct brw_device_info *devinfo = &pipeline->device->info;
+ const struct gen_device_info *devinfo = &pipeline->device->info;
switch (devinfo->gen) {
case 7:
if (devinfo->is_haswell)
void
anv_compute_urb_partition(struct anv_pipeline *pipeline)
{
- const struct brw_device_info *devinfo = &pipeline->device->info;
+ const struct gen_device_info *devinfo = &pipeline->device->info;
bool vs_present = pipeline->active_stages & VK_SHADER_STAGE_VERTEX_BIT;
unsigned vs_size = vs_present ?
#define VG(x)
#endif
-#include "common/brw_device_info.h"
+#include "common/gen_device_info.h"
#include "brw_compiler.h"
#include "util/macros.h"
#include "util/list.h"
uint32_t chipset_id;
char path[20];
const char * name;
- const struct brw_device_info * info;
+ const struct gen_device_info * info;
uint64_t aperture_size;
struct brw_compiler * compiler;
struct isl_device isl_dev;
struct anv_instance * instance;
uint32_t chipset_id;
- struct brw_device_info info;
+ struct gen_device_info info;
struct isl_device isl_dev;
int context_id;
int fd;
};
struct anv_format
-anv_get_format(const struct brw_device_info *devinfo, VkFormat format,
+anv_get_format(const struct gen_device_info *devinfo, VkFormat format,
VkImageAspectFlags aspect, VkImageTiling tiling);
static inline enum isl_format
-anv_get_isl_format(const struct brw_device_info *devinfo, VkFormat vk_format,
+anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
VkImageAspectFlags aspect, VkImageTiling tiling)
{
return anv_get_format(devinfo, vk_format, aspect, tiling).isl_format;
* specified device.
*/
static inline const struct anv_l3_config *
-get_l3_configs(const struct brw_device_info *devinfo)
+get_l3_configs(const struct gen_device_info *devinfo)
{
assert(devinfo->gen == GEN_GEN);
#if GEN_IS_HASWELL
* Return the size of an L3 way in KB.
*/
static unsigned
-get_l3_way_size(const struct brw_device_info *devinfo)
+get_l3_way_size(const struct gen_device_info *devinfo)
{
if (devinfo->is_baytrail)
return 2;
* weight vector.
*/
static const struct anv_l3_config *
-get_l3_config(const struct brw_device_info *devinfo, struct anv_l3_weights w0)
+get_l3_config(const struct gen_device_info *devinfo, struct anv_l3_weights w0)
{
const struct anv_l3_config *const cfgs = get_l3_configs(devinfo);
const struct anv_l3_config *cfg_best = NULL;
* is intended to approximately resemble the hardware defaults.
*/
static struct anv_l3_weights
-get_default_l3_weights(const struct brw_device_info *devinfo,
+get_default_l3_weights(const struct gen_device_info *devinfo,
bool needs_dc, bool needs_slm)
{
struct anv_l3_weights w = {{ 0 }};
* client (URB for all validated configurations) set to the
* lower-bandwidth 2-bank address hashing mode.
*/
- const struct brw_device_info *devinfo = &cmd_buffer->device->info;
+ const struct gen_device_info *devinfo = &cmd_buffer->device->info;
const bool urb_low_bw = has_slm && !devinfo->is_baytrail;
assert(!urb_low_bw || cfg->n[L3P_URB] == cfg->n[L3P_SLM]);
/**
* Return the unit brw_context::urb::size is expressed in, in KB. \sa
- * brw_device_info::urb::size.
+ * gen_device_info::urb::size.
*/
static unsigned
-get_urb_size_scale(const struct brw_device_info *devinfo)
+get_urb_size_scale(const struct gen_device_info *devinfo)
{
return (devinfo->gen >= 8 ? devinfo->num_slices : 1);
}
genX(setup_pipeline_l3_config)(struct anv_pipeline *pipeline)
{
const struct anv_l3_weights w = get_pipeline_state_l3_weights(pipeline);
- const struct brw_device_info *devinfo = &pipeline->device->info;
+ const struct gen_device_info *devinfo = &pipeline->device->info;
const struct anv_l3_config *const cfg = get_l3_config(devinfo, w);
pipeline->urb.l3_config = cfg;
static void brw_clip_line_alloc_regs( struct brw_clip_compile *c )
{
- const struct brw_device_info *devinfo = c->func.devinfo;
+ const struct gen_device_info *devinfo = c->func.devinfo;
GLuint i = 0,j;
/* Register usage is static, precompute here:
void brw_clip_tri_alloc_regs( struct brw_clip_compile *c,
GLuint nr_verts )
{
- const struct brw_device_info *devinfo = c->func.devinfo;
+ const struct gen_device_info *devinfo = c->func.devinfo;
GLuint i = 0,j;
/* Register usage is static, precompute here:
};
struct brw_compiler *
-brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
+brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo)
{
struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
#pragma once
#include <stdio.h>
-#include "common/brw_device_info.h"
+#include "common/gen_device_info.h"
#include "main/mtypes.h"
#include "main/macros.h"
union gl_constant_value;
struct brw_compiler {
- const struct brw_device_info *devinfo;
+ const struct gen_device_info *devinfo;
struct {
struct ra_regs *regs;
return brw_vue_slot_to_offset(vue_map->varying_to_slot[varying]);
}
-void brw_compute_vue_map(const struct brw_device_info *devinfo,
+void brw_compute_vue_map(const struct gen_device_info *devinfo,
struct brw_vue_map *vue_map,
GLbitfield64 slots_valid,
bool separate_shader);
/** @} */
struct brw_compiler *
-brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo);
+brw_compiler_create(void *mem_ctx, const struct gen_device_info *devinfo);
/**
* Compile a vertex shader.
__DRIscreen *sPriv = driContextPriv->driScreenPriv;
struct gl_context *shareCtx = (struct gl_context *) sharedContextPrivate;
struct intel_screen *screen = sPriv->driverPrivate;
- const struct brw_device_info *devinfo = screen->devinfo;
+ const struct gen_device_info *devinfo = screen->devinfo;
struct dd_function_table functions;
/* Only allow the __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS flag if the kernel
GLuint cs_start;
/**
* URB size in the current configuration. The units this is expressed
- * in are somewhat inconsistent, see brw_device_info::urb::size.
+ * in are somewhat inconsistent, see gen_device_info::urb::size.
*
* FINISHME: Represent the URB size consistently in KB on all platforms.
*/
void brw_vec4_alloc_reg_set(struct brw_compiler *compiler);
/* brw_disasm.c */
-int brw_disassemble_inst(FILE *file, const struct brw_device_info *devinfo,
+int brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
struct brw_inst *inst, bool is_compacted);
/* brw_vs.c */
/* brw_pipe_control.c */
int brw_init_pipe_control(struct brw_context *brw,
- const struct brw_device_info *info);
+ const struct gen_device_info *info);
void brw_fini_pipe_control(struct brw_context *brw);
void brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags);
#include "compiler/glsl/ir_uniform.h"
static void
-assign_cs_binding_table_offsets(const struct brw_device_info *devinfo,
+assign_cs_binding_table_offsets(const struct gen_device_info *devinfo,
const struct gl_shader_program *shader_prog,
const struct gl_program *prog,
struct brw_cs_prog_data *prog_data)
#include "brw_eu.h"
static bool
-has_jip(const struct brw_device_info *devinfo, enum opcode opcode)
+has_jip(const struct gen_device_info *devinfo, enum opcode opcode)
{
if (devinfo->gen < 6)
return false;
}
static bool
-has_uip(const struct brw_device_info *devinfo, enum opcode opcode)
+has_uip(const struct gen_device_info *devinfo, enum opcode opcode)
{
if (devinfo->gen < 6)
return false;
}
static bool
-has_branch_ctrl(const struct brw_device_info *devinfo, enum opcode opcode)
+has_branch_ctrl(const struct gen_device_info *devinfo, enum opcode opcode)
{
if (devinfo->gen < 8)
return false;
}
static int
-print_opcode(FILE *file, const struct brw_device_info *devinfo,
+print_opcode(FILE *file, const struct gen_device_info *devinfo,
enum opcode id)
{
const struct opcode_desc *desc = brw_opcode_desc(devinfo, id);
}
static int
-dest(FILE *file, const struct brw_device_info *devinfo, brw_inst *inst)
+dest(FILE *file, const struct gen_device_info *devinfo, brw_inst *inst)
{
int err = 0;
}
static int
-dest_3src(FILE *file, const struct brw_device_info *devinfo, brw_inst *inst)
+dest_3src(FILE *file, const struct gen_device_info *devinfo, brw_inst *inst)
{
int err = 0;
uint32_t reg_file;
static int
src_da1(FILE *file,
- const struct brw_device_info *devinfo,
+ const struct gen_device_info *devinfo,
unsigned opcode,
unsigned type, unsigned _reg_file,
unsigned _vert_stride, unsigned _width, unsigned _horiz_stride,
static int
src_ia1(FILE *file,
- const struct brw_device_info *devinfo,
+ const struct gen_device_info *devinfo,
unsigned opcode,
unsigned type,
unsigned _reg_file,
static int
src_da16(FILE *file,
- const struct brw_device_info *devinfo,
+ const struct gen_device_info *devinfo,
unsigned opcode,
unsigned _reg_type,
unsigned _reg_file,
}
static int
-src0_3src(FILE *file, const struct brw_device_info *devinfo, brw_inst *inst)
+src0_3src(FILE *file, const struct gen_device_info *devinfo, brw_inst *inst)
{
int err = 0;
unsigned src0_subreg_nr = brw_inst_3src_src0_subreg_nr(devinfo, inst);
}
static int
-src1_3src(FILE *file, const struct brw_device_info *devinfo, brw_inst *inst)
+src1_3src(FILE *file, const struct gen_device_info *devinfo, brw_inst *inst)
{
int err = 0;
unsigned src1_subreg_nr = brw_inst_3src_src1_subreg_nr(devinfo, inst);
static int
-src2_3src(FILE *file, const struct brw_device_info *devinfo, brw_inst *inst)
+src2_3src(FILE *file, const struct gen_device_info *devinfo, brw_inst *inst)
{
int err = 0;
unsigned src2_subreg_nr = brw_inst_3src_src2_subreg_nr(devinfo, inst);
}
static int
-imm(FILE *file, const struct brw_device_info *devinfo, unsigned type, brw_inst *inst)
+imm(FILE *file, const struct gen_device_info *devinfo, unsigned type, brw_inst *inst)
{
switch (type) {
case BRW_HW_REG_TYPE_UD:
}
static int
-src0(FILE *file, const struct brw_device_info *devinfo, brw_inst *inst)
+src0(FILE *file, const struct gen_device_info *devinfo, brw_inst *inst)
{
if (brw_inst_src0_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) {
return imm(file, devinfo, brw_inst_src0_reg_type(devinfo, inst), inst);
}
static int
-src1(FILE *file, const struct brw_device_info *devinfo, brw_inst *inst)
+src1(FILE *file, const struct gen_device_info *devinfo, brw_inst *inst)
{
if (brw_inst_src1_reg_file(devinfo, inst) == BRW_IMMEDIATE_VALUE) {
return imm(file, devinfo, brw_inst_src1_reg_type(devinfo, inst), inst);
}
static int
-qtr_ctrl(FILE *file, const struct brw_device_info *devinfo, brw_inst *inst)
+qtr_ctrl(FILE *file, const struct gen_device_info *devinfo, brw_inst *inst)
{
int qtr_ctl = brw_inst_qtr_control(devinfo, inst);
int exec_size = 1 << brw_inst_exec_size(devinfo, inst);
#ifdef DEBUG
static __attribute__((__unused__)) int
-brw_disassemble_imm(const struct brw_device_info *devinfo,
+brw_disassemble_imm(const struct gen_device_info *devinfo,
uint32_t dw3, uint32_t dw2, uint32_t dw1, uint32_t dw0)
{
brw_inst inst;
#endif
int
-brw_disassemble_inst(FILE *file, const struct brw_device_info *devinfo,
+brw_disassemble_inst(FILE *file, const struct gen_device_info *devinfo,
brw_inst *inst, bool is_compacted)
{
int err = 0;
* the currently selected channel enable group untouched.
*/
void
-brw_inst_set_compression(const struct brw_device_info *devinfo,
+brw_inst_set_compression(const struct gen_device_info *devinfo,
brw_inst *inst, bool on)
{
if (devinfo->gen >= 6) {
* [group, group + exec_size) to the instruction passed as argument.
*/
void
-brw_inst_set_group(const struct brw_device_info *devinfo,
+brw_inst_set_group(const struct gen_device_info *devinfo,
brw_inst *inst, unsigned group)
{
if (devinfo->gen >= 7) {
/***********************************************************************
*/
void
-brw_init_codegen(const struct brw_device_info *devinfo,
+brw_init_codegen(const struct gen_device_info *devinfo,
struct brw_codegen *p, void *mem_ctx)
{
memset(p, 0, sizeof(*p));
}
void
-brw_disassemble(const struct brw_device_info *devinfo,
+brw_disassemble(const struct gen_device_info *devinfo,
void *assembly, int start, int end, FILE *out)
{
bool dump_hex = (INTEL_DEBUG & DEBUG_HEX) != 0;
};
static enum gen
-gen_from_devinfo(const struct brw_device_info *devinfo)
+gen_from_devinfo(const struct gen_device_info *devinfo)
{
switch (devinfo->gen) {
case 4: return devinfo->is_g4x ? GEN45 : GEN4;
* hardware generation, or NULL if the opcode is not supported by the device.
*/
const struct opcode_desc *
-brw_opcode_desc(const struct brw_device_info *devinfo, enum opcode opcode)
+brw_opcode_desc(const struct gen_device_info *devinfo, enum opcode opcode)
{
if (opcode >= ARRAY_SIZE(opcode_descs))
return NULL;
brw_inst *current;
bool single_program_flow;
- const struct brw_device_info *devinfo;
+ const struct gen_device_info *devinfo;
/* Control flow stacks:
* - if_stack contains IF and ELSE instructions which must be patched
void brw_set_default_mask_control( struct brw_codegen *p, unsigned value );
void brw_set_default_saturate( struct brw_codegen *p, bool enable );
void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode );
-void brw_inst_set_compression(const struct brw_device_info *devinfo,
+void brw_inst_set_compression(const struct gen_device_info *devinfo,
brw_inst *inst, bool on);
void brw_set_default_compression(struct brw_codegen *p, bool on);
-void brw_inst_set_group(const struct brw_device_info *devinfo,
+void brw_inst_set_group(const struct gen_device_info *devinfo,
brw_inst *inst, unsigned group);
void brw_set_default_group(struct brw_codegen *p, unsigned group);
void brw_set_default_compression_control(struct brw_codegen *p, enum brw_compression c);
void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg);
void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value);
-void brw_init_codegen(const struct brw_device_info *, struct brw_codegen *p,
+void brw_init_codegen(const struct gen_device_info *, struct brw_codegen *p,
void *mem_ctx);
-void brw_disassemble(const struct brw_device_info *devinfo, void *assembly,
+void brw_disassemble(const struct gen_device_info *devinfo, void *assembly,
int start, int end, FILE *out);
const unsigned *brw_get_program( struct brw_codegen *p, unsigned *sz );
* instruction.
*/
static inline unsigned
-brw_jump_scale(const struct brw_device_info *devinfo)
+brw_jump_scale(const struct gen_device_info *devinfo)
{
/* Broadwell measures jump targets in bytes. */
if (devinfo->gen >= 8)
enum brw_conditional_mod brw_swap_cmod(uint32_t cmod);
/* brw_eu_compact.c */
-void brw_init_compaction_tables(const struct brw_device_info *devinfo);
+void brw_init_compaction_tables(const struct gen_device_info *devinfo);
void brw_compact_instructions(struct brw_codegen *p, int start_offset,
int num_annotations, struct annotation *annotation);
-void brw_uncompact_instruction(const struct brw_device_info *devinfo,
+void brw_uncompact_instruction(const struct gen_device_info *devinfo,
brw_inst *dst, brw_compact_inst *src);
-bool brw_try_compact_instruction(const struct brw_device_info *devinfo,
+bool brw_try_compact_instruction(const struct gen_device_info *devinfo,
brw_compact_inst *dst, brw_inst *src);
-void brw_debug_compact_uncompact(const struct brw_device_info *devinfo,
+void brw_debug_compact_uncompact(const struct gen_device_info *devinfo,
brw_inst *orig, brw_inst *uncompacted);
/* brw_eu_validate.c */
struct annotation_info *annotation);
static inline int
-next_offset(const struct brw_device_info *devinfo, void *store, int offset)
+next_offset(const struct gen_device_info *devinfo, void *store, int offset)
{
brw_inst *insn = (brw_inst *)((char *)store + offset);
};
const struct opcode_desc *
-brw_opcode_desc(const struct brw_device_info *devinfo, enum opcode opcode);
+brw_opcode_desc(const struct gen_device_info *devinfo, enum opcode opcode);
static inline bool
-is_3src(const struct brw_device_info *devinfo, enum opcode opcode)
+is_3src(const struct gen_device_info *devinfo, enum opcode opcode)
{
const struct opcode_desc *desc = brw_opcode_desc(devinfo, opcode);
return desc && desc->nsrc == 3;
static const uint16_t *src_index_table;
static bool
-set_control_index(const struct brw_device_info *devinfo,
+set_control_index(const struct gen_device_info *devinfo,
brw_compact_inst *dst, brw_inst *src)
{
uint32_t uncompacted = devinfo->gen >= 8 /* 17b/G45; 19b/IVB+ */
}
static bool
-set_datatype_index(const struct brw_device_info *devinfo, brw_compact_inst *dst,
+set_datatype_index(const struct gen_device_info *devinfo, brw_compact_inst *dst,
brw_inst *src)
{
uint32_t uncompacted = devinfo->gen >= 8 /* 18b/G45+; 21b/BDW+ */
}
static bool
-set_subreg_index(const struct brw_device_info *devinfo, brw_compact_inst *dst,
+set_subreg_index(const struct gen_device_info *devinfo, brw_compact_inst *dst,
brw_inst *src, bool is_immediate)
{
uint16_t uncompacted = /* 15b */
}
static bool
-set_src0_index(const struct brw_device_info *devinfo,
+set_src0_index(const struct gen_device_info *devinfo,
brw_compact_inst *dst, brw_inst *src)
{
uint16_t compacted;
}
static bool
-set_src1_index(const struct brw_device_info *devinfo, brw_compact_inst *dst,
+set_src1_index(const struct gen_device_info *devinfo, brw_compact_inst *dst,
brw_inst *src, bool is_immediate)
{
uint16_t compacted;
}
static bool
-set_3src_control_index(const struct brw_device_info *devinfo,
+set_3src_control_index(const struct gen_device_info *devinfo,
brw_compact_inst *dst, brw_inst *src)
{
assert(devinfo->gen >= 8);
}
static bool
-set_3src_source_index(const struct brw_device_info *devinfo,
+set_3src_source_index(const struct gen_device_info *devinfo,
brw_compact_inst *dst, brw_inst *src)
{
assert(devinfo->gen >= 8);
}
static bool
-has_unmapped_bits(const struct brw_device_info *devinfo, brw_inst *src)
+has_unmapped_bits(const struct gen_device_info *devinfo, brw_inst *src)
{
/* EOT can only be mapped on a send if the src1 is an immediate */
if ((brw_inst_opcode(devinfo, src) == BRW_OPCODE_SENDC ||
}
static bool
-has_3src_unmapped_bits(const struct brw_device_info *devinfo, brw_inst *src)
+has_3src_unmapped_bits(const struct gen_device_info *devinfo, brw_inst *src)
{
/* Check for three-source instruction bits that don't map to any of the
* fields of the compacted instruction. All of them seem to be reserved
}
static bool
-brw_try_compact_3src_instruction(const struct brw_device_info *devinfo,
+brw_try_compact_3src_instruction(const struct gen_device_info *devinfo,
brw_compact_inst *dst, brw_inst *src)
{
assert(devinfo->gen >= 8);
* brw_compact_instructions().
*/
bool
-brw_try_compact_instruction(const struct brw_device_info *devinfo,
+brw_try_compact_instruction(const struct gen_device_info *devinfo,
brw_compact_inst *dst, brw_inst *src)
{
brw_compact_inst temp;
}
static void
-set_uncompacted_control(const struct brw_device_info *devinfo, brw_inst *dst,
+set_uncompacted_control(const struct gen_device_info *devinfo, brw_inst *dst,
brw_compact_inst *src)
{
uint32_t uncompacted =
}
static void
-set_uncompacted_datatype(const struct brw_device_info *devinfo, brw_inst *dst,
+set_uncompacted_datatype(const struct gen_device_info *devinfo, brw_inst *dst,
brw_compact_inst *src)
{
uint32_t uncompacted =
}
static void
-set_uncompacted_subreg(const struct brw_device_info *devinfo, brw_inst *dst,
+set_uncompacted_subreg(const struct gen_device_info *devinfo, brw_inst *dst,
brw_compact_inst *src)
{
uint16_t uncompacted =
}
static void
-set_uncompacted_src0(const struct brw_device_info *devinfo, brw_inst *dst,
+set_uncompacted_src0(const struct gen_device_info *devinfo, brw_inst *dst,
brw_compact_inst *src)
{
uint32_t compacted = brw_compact_inst_src0_index(devinfo, src);
}
static void
-set_uncompacted_src1(const struct brw_device_info *devinfo, brw_inst *dst,
+set_uncompacted_src1(const struct gen_device_info *devinfo, brw_inst *dst,
brw_compact_inst *src, bool is_immediate)
{
if (is_immediate) {
}
static void
-set_uncompacted_3src_control_index(const struct brw_device_info *devinfo,
+set_uncompacted_3src_control_index(const struct gen_device_info *devinfo,
brw_inst *dst, brw_compact_inst *src)
{
assert(devinfo->gen >= 8);
}
static void
-set_uncompacted_3src_source_index(const struct brw_device_info *devinfo,
+set_uncompacted_3src_source_index(const struct gen_device_info *devinfo,
brw_inst *dst, brw_compact_inst *src)
{
assert(devinfo->gen >= 8);
}
static void
-brw_uncompact_3src_instruction(const struct brw_device_info *devinfo,
+brw_uncompact_3src_instruction(const struct gen_device_info *devinfo,
brw_inst *dst, brw_compact_inst *src)
{
assert(devinfo->gen >= 8);
}
void
-brw_uncompact_instruction(const struct brw_device_info *devinfo, brw_inst *dst,
+brw_uncompact_instruction(const struct gen_device_info *devinfo, brw_inst *dst,
brw_compact_inst *src)
{
memset(dst, 0, sizeof(*dst));
#undef uncompact
}
-void brw_debug_compact_uncompact(const struct brw_device_info *devinfo,
+void brw_debug_compact_uncompact(const struct gen_device_info *devinfo,
brw_inst *orig,
brw_inst *uncompacted)
{
}
static void
-update_uip_jip(const struct brw_device_info *devinfo, brw_inst *insn,
+update_uip_jip(const struct gen_device_info *devinfo, brw_inst *insn,
int this_old_ip, int *compacted_counts)
{
/* JIP and UIP are in units of:
}
static void
-update_gen4_jump_count(const struct brw_device_info *devinfo, brw_inst *insn,
+update_gen4_jump_count(const struct gen_device_info *devinfo, brw_inst *insn,
int this_old_ip, int *compacted_counts)
{
assert(devinfo->gen == 5 || devinfo->is_g4x);
}
void
-brw_init_compaction_tables(const struct brw_device_info *devinfo)
+brw_init_compaction_tables(const struct gen_device_info *devinfo)
{
static bool initialized;
if (initialized || p_atomic_cmpxchg(&initialized, false, true) != false)
if (unlikely(INTEL_DEBUG & DEBUG_NO_COMPACTION))
return;
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
void *store = p->store + start_offset / 16;
/* For an instruction at byte offset 16*i before compaction, this is the
* number of compacted instructions minus the number of padding NOP/NENOPs
struct brw_reg *src,
unsigned msg_reg_nr)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
if (devinfo->gen < 6)
return;
* Since we're pretending to have 16 MRFs anyway, we may as well use the
* registers required for messages with EOT.
*/
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
if (devinfo->gen >= 7 && reg->file == BRW_MESSAGE_REGISTER_FILE) {
reg->file = BRW_GENERAL_REGISTER_FILE;
reg->nr += GEN7_MRF_HACK_START;
* The hardware encoding may depend on whether the value is an immediate.
*/
unsigned
-brw_reg_type_to_hw_type(const struct brw_device_info *devinfo,
+brw_reg_type_to_hw_type(const struct gen_device_info *devinfo,
enum brw_reg_type type, enum brw_reg_file file)
{
if (file == BRW_IMMEDIATE_VALUE) {
void
brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
if (dest.file == BRW_MESSAGE_REGISTER_FILE)
assert((dest.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->gen));
extern int reg_type_size[];
static void
-validate_reg(const struct brw_device_info *devinfo,
+validate_reg(const struct gen_device_info *devinfo,
brw_inst *inst, struct brw_reg reg)
{
const int hstride_for_reg[] = {0, 1, 2, 4};
void
brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
if (reg.file == BRW_MESSAGE_REGISTER_FILE)
assert((reg.nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(devinfo->gen));
void
brw_set_src1(struct brw_codegen *p, brw_inst *inst, struct brw_reg reg)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
if (reg.file != BRW_ARCHITECTURE_REGISTER_FILE)
assert(reg.nr < 128);
bool header_present,
bool end_of_thread)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
brw_set_src1(p, inst, brw_imm_d(0));
bool low_precision,
unsigned dataType )
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
unsigned msg_length;
unsigned response_length;
unsigned response_length,
bool end_of_thread)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
brw_set_message_descriptor(p, insn, BRW_SFID_URB,
1, response_length, true, end_of_thread);
unsigned offset,
unsigned swizzle_control )
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
assert(devinfo->gen < 7 || swizzle_control != BRW_URB_SWIZZLE_TRANSPOSE);
assert(devinfo->gen < 7 || !(flags & BRW_URB_WRITE_ALLOCATE));
unsigned end_of_thread,
unsigned send_commit_msg)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
unsigned sfid;
if (devinfo->gen >= 7) {
bool header_present,
unsigned response_length)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
unsigned sfid;
if (devinfo->gen >= 7) {
unsigned simd_mode,
unsigned return_format)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
brw_set_message_descriptor(p, inst, BRW_SFID_SAMPLER, msg_length,
response_length, header_present, false);
unsigned rlen,
bool header_present)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
assert(num_regs == 1 || num_regs == 2 || num_regs == 4 ||
(devinfo->gen >= 8 && num_regs == 8));
const unsigned block_size = (devinfo->gen >= 8 ? _mesa_logbase2(num_regs) :
brw_inst *
brw_next_insn(struct brw_codegen *p, unsigned opcode)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
brw_inst *insn;
if (p->nr_insn + 1 > p->store_size) {
brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
struct brw_reg src0, struct brw_reg src1, struct brw_reg src2)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
brw_inst *inst = next_insn(p, opcode);
gen7_convert_mrf_to_grf(p, &dest);
struct brw_reg dest, \
struct brw_reg src) \
{ \
- const struct brw_device_info *devinfo = p->devinfo; \
+ const struct gen_device_info *devinfo = p->devinfo; \
brw_inst *rnd, *add; \
rnd = next_insn(p, BRW_OPCODE_##OP); \
brw_set_dest(p, rnd, dest); \
brw_inst *
brw_F32TO16(struct brw_codegen *p, struct brw_reg dst, struct brw_reg src)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
const bool align16 = brw_inst_access_mode(devinfo, p->current) == BRW_ALIGN_16;
/* The F32TO16 instruction doesn't support 32-bit destination types in
* Align1 mode, and neither does the Gen8 implementation in terms of a
brw_inst *
brw_F16TO32(struct brw_codegen *p, struct brw_reg dst, struct brw_reg src)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
bool align16 = brw_inst_access_mode(devinfo, p->current) == BRW_ALIGN_16;
if (align16) {
brw_JMPI(struct brw_codegen *p, struct brw_reg index,
unsigned predicate_control)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
struct brw_reg ip = brw_ip_reg();
brw_inst *inst = brw_alu2(p, BRW_OPCODE_JMPI, ip, ip, index);
brw_inst *
brw_IF(struct brw_codegen *p, unsigned execute_size)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
brw_inst *insn;
insn = next_insn(p, BRW_OPCODE_IF);
gen6_IF(struct brw_codegen *p, enum brw_conditional_mod conditional,
struct brw_reg src0, struct brw_reg src1)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
brw_inst *insn;
insn = next_insn(p, BRW_OPCODE_IF);
convert_IF_ELSE_to_ADD(struct brw_codegen *p,
brw_inst *if_inst, brw_inst *else_inst)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
/* The next instruction (where the ENDIF would be, if it existed) */
brw_inst *next_inst = &p->store[p->nr_insn];
patch_IF_ELSE(struct brw_codegen *p,
brw_inst *if_inst, brw_inst *else_inst, brw_inst *endif_inst)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
/* We shouldn't be patching IF and ELSE instructions in single program flow
* mode when gen < 6, because in single program flow mode on those
void
brw_ELSE(struct brw_codegen *p)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
brw_inst *insn;
insn = next_insn(p, BRW_OPCODE_ELSE);
void
brw_ENDIF(struct brw_codegen *p)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
brw_inst *insn = NULL;
brw_inst *else_inst = NULL;
brw_inst *if_inst = NULL;
brw_inst *
brw_BREAK(struct brw_codegen *p)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
brw_inst *insn;
insn = next_insn(p, BRW_OPCODE_BREAK);
brw_inst *
brw_CONT(struct brw_codegen *p)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
brw_inst *insn;
insn = next_insn(p, BRW_OPCODE_CONTINUE);
brw_inst *
gen6_HALT(struct brw_codegen *p)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
brw_inst *insn;
insn = next_insn(p, BRW_OPCODE_HALT);
brw_inst *
brw_DO(struct brw_codegen *p, unsigned execute_size)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
if (devinfo->gen >= 6 || p->single_program_flow) {
push_loop_stack(p, &p->store[p->nr_insn]);
static void
brw_patch_break_cont(struct brw_codegen *p, brw_inst *while_inst)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
brw_inst *do_inst = get_inner_do_insn(p);
brw_inst *inst;
unsigned br = brw_jump_scale(devinfo);
brw_inst *
brw_WHILE(struct brw_codegen *p)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
brw_inst *insn, *do_insn;
unsigned br = brw_jump_scale(devinfo);
*/
void brw_land_fwd_jump(struct brw_codegen *p, int jmp_insn_idx)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
brw_inst *jmp_insn = &p->store[jmp_insn_idx];
unsigned jmpi = 1;
struct brw_reg src0,
struct brw_reg src1)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
brw_inst *insn = next_insn(p, BRW_OPCODE_CMP);
brw_inst_set_cond_modifier(devinfo, insn, conditional);
struct brw_reg src,
unsigned precision )
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
brw_inst *insn = next_insn(p, BRW_OPCODE_SEND);
unsigned data_type;
if (has_scalar_region(src)) {
struct brw_reg src0,
struct brw_reg src1)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
brw_inst *insn = next_insn(p, BRW_OPCODE_MATH);
assert(devinfo->gen >= 6);
int num_regs,
unsigned offset)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
uint32_t msg_type;
if (devinfo->gen >= 6)
int num_regs,
unsigned offset)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
if (devinfo->gen >= 6)
offset /= 16;
int num_regs,
unsigned offset)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
brw_inst *insn = next_insn(p, BRW_OPCODE_SEND);
assert(brw_inst_pred_control(devinfo, insn) == BRW_PREDICATE_NONE);
uint32_t offset,
uint32_t bind_table_index)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
/* On newer hardware, offset is in units of owords. */
if (devinfo->gen >= 6)
bool last_render_target,
bool header_present)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
brw_inst *insn;
unsigned msg_type;
struct brw_reg dest, src0;
unsigned simd_mode,
unsigned return_format)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
brw_inst *insn;
if (msg_reg_nr != -1)
* exclusively use the offset - we have to use both.
*/
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
const int sampler_state_size = 16; /* 16 bytes */
unsigned offset,
unsigned swizzle)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
brw_inst *insn;
gen6_resolve_implied_move(p, &src0, msg_reg_nr);
struct brw_reg payload,
struct brw_reg desc)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
struct brw_inst *send;
int setup;
unsigned response_len,
bool header_present)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
struct brw_inst *insn;
if (surface.file != BRW_IMMEDIATE_VALUE) {
}
static bool
-while_jumps_before_offset(const struct brw_device_info *devinfo,
+while_jumps_before_offset(const struct gen_device_info *devinfo,
brw_inst *insn, int while_offset, int start_offset)
{
int scale = 16 / brw_jump_scale(devinfo);
{
int offset;
void *store = p->store;
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
int depth = 0;
static int
brw_find_loop_end(struct brw_codegen *p, int start_offset)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
int offset;
void *store = p->store;
void
brw_set_uip_jip(struct brw_codegen *p, int start_offset)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
int offset;
int br = brw_jump_scale(devinfo);
int scale = 16 / br;
unsigned response_length,
bool eot)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
brw_inst *insn;
gen6_resolve_implied_move(p, &src0, msg_reg_nr);
unsigned atomic_op,
bool response_expected)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
unsigned msg_control =
atomic_op | /* Atomic Operation Type: BRW_AOP_* */
(response_expected ? 1 << 5 : 0); /* Return data expected */
unsigned msg_length,
bool response_expected)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
const unsigned sfid = (devinfo->gen >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN7_SFID_DATAPORT_DATA_CACHE);
struct brw_inst *insn,
unsigned num_channels)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
/* Set mask of 32-bit channels to drop. */
unsigned msg_control = 0xf & (0xf << num_channels);
unsigned msg_length,
unsigned num_channels)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
const unsigned sfid = (devinfo->gen >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN7_SFID_DATAPORT_DATA_CACHE);
struct brw_inst *insn,
unsigned num_channels)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
/* Set mask of 32-bit channels to drop. */
unsigned msg_control = 0xf & (0xf << num_channels);
unsigned msg_length,
unsigned num_channels)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
const unsigned sfid = (devinfo->gen >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN7_SFID_DATAPORT_DATA_CACHE);
unsigned atomic_op,
bool response_expected)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
unsigned msg_control =
atomic_op | /* Atomic Operation Type: BRW_AOP_* */
(response_expected ? 1 << 5 : 0); /* Return data expected */
unsigned atomic_op,
unsigned msg_length,
bool response_expected) {
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
const unsigned sfid = (devinfo->gen >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN6_SFID_DATAPORT_RENDER_CACHE);
struct brw_inst *insn,
unsigned num_channels)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
/* Set mask of unused channels. */
unsigned msg_control = 0xf & (0xf << num_channels);
unsigned msg_length,
unsigned num_channels)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
const unsigned sfid = (devinfo->gen >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN6_SFID_DATAPORT_RENDER_CACHE);
struct brw_inst *insn,
unsigned num_channels)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
/* Set mask of unused channels. */
unsigned msg_control = 0xf & (0xf << num_channels);
unsigned msg_length,
unsigned num_channels)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
const unsigned sfid = (devinfo->gen >= 8 || devinfo->is_haswell ?
HSW_SFID_DATAPORT_DATA_CACHE_1 :
GEN6_SFID_DATAPORT_RENDER_CACHE);
enum brw_message_target sfid,
bool commit_enable)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
brw_set_message_descriptor(p, insn, sfid,
1 /* message length */,
brw_memory_fence(struct brw_codegen *p,
struct brw_reg dst)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
const bool commit_enable = devinfo->gen == 7 && !devinfo->is_haswell;
struct brw_inst *insn;
unsigned msg_length,
unsigned response_length)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
struct brw_inst *insn;
const uint16_t exec_size = brw_inst_exec_size(devinfo, p->current);
void
brw_find_live_channel(struct brw_codegen *p, struct brw_reg dst)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
const unsigned exec_size = 1 << brw_inst_exec_size(devinfo, p->current);
const unsigned qtr_control = brw_inst_qtr_control(devinfo, p->current);
brw_inst *inst;
struct brw_reg src,
struct brw_reg idx)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
const bool align1 = brw_inst_access_mode(devinfo, p->current) == BRW_ALIGN_1;
brw_inst *inst;
void
brw_barrier(struct brw_codegen *p, struct brw_reg src)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
struct brw_inst *inst;
assert(devinfo->gen >= 7);
void
brw_WAIT(struct brw_codegen *p)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
struct brw_inst *insn;
struct brw_reg src = brw_notification_reg();
} while(0)
static bool
-src0_is_null(const struct brw_device_info *devinfo, const brw_inst *inst)
+src0_is_null(const struct gen_device_info *devinfo, const brw_inst *inst)
{
return brw_inst_src0_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE &&
brw_inst_src0_da_reg_nr(devinfo, inst) == BRW_ARF_NULL;
}
static bool
-src1_is_null(const struct brw_device_info *devinfo, const brw_inst *inst)
+src1_is_null(const struct gen_device_info *devinfo, const brw_inst *inst)
{
return brw_inst_src1_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE &&
brw_inst_src1_da_reg_nr(devinfo, inst) == BRW_ARF_NULL;
}
static bool
-src0_is_grf(const struct brw_device_info *devinfo, const brw_inst *inst)
+src0_is_grf(const struct gen_device_info *devinfo, const brw_inst *inst)
{
return brw_inst_src0_reg_file(devinfo, inst) == BRW_GENERAL_REGISTER_FILE;
}
static unsigned
-num_sources_from_inst(const struct brw_device_info *devinfo,
+num_sources_from_inst(const struct gen_device_info *devinfo,
const brw_inst *inst)
{
const struct opcode_desc *desc =
}
static bool
-is_unsupported_inst(const struct brw_device_info *devinfo,
+is_unsupported_inst(const struct gen_device_info *devinfo,
const brw_inst *inst)
{
return brw_opcode_desc(devinfo, brw_inst_opcode(devinfo, inst)) == NULL;
brw_validate_instructions(const struct brw_codegen *p, int start_offset,
struct annotation_info *annotation)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
const void *store = p->store + start_offset / 16;
bool valid = true;
using namespace brw;
-static unsigned get_lowered_simd_width(const struct brw_device_info *devinfo,
+static unsigned get_lowered_simd_width(const struct gen_device_info *devinfo,
const fs_inst *inst);
void
}
bool
-fs_inst::can_do_source_mods(const struct brw_device_info *devinfo)
+fs_inst::can_do_source_mods(const struct gen_device_info *devinfo)
{
if (devinfo->gen == 6 && is_math())
return false;
}
unsigned
-fs_inst::flags_read(const brw_device_info *devinfo) const
+fs_inst::flags_read(const gen_device_info *devinfo) const
{
/* XXX - This doesn't consider explicit uses of the flag register as source
* region.
const fs_visitor::thread_payload &payload)
{
assert(inst->src[FB_WRITE_LOGICAL_SRC_COMPONENTS].file == IMM);
- const brw_device_info *devinfo = bld.shader->devinfo;
+ const gen_device_info *devinfo = bld.shader->devinfo;
const fs_reg &color0 = inst->src[FB_WRITE_LOGICAL_SRC_COLOR0];
const fs_reg &color1 = inst->src[FB_WRITE_LOGICAL_SRC_COLOR1];
const fs_reg &src0_alpha = inst->src[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA];
}
static bool
-is_high_sampler(const struct brw_device_info *devinfo, const fs_reg &sampler)
+is_high_sampler(const struct gen_device_info *devinfo, const fs_reg &sampler)
{
if (devinfo->gen < 8 && !devinfo->is_haswell)
return false;
unsigned coord_components,
unsigned grad_components)
{
- const brw_device_info *devinfo = bld.shader->devinfo;
+ const gen_device_info *devinfo = bld.shader->devinfo;
int reg_width = bld.dispatch_width() / 8;
unsigned header_size = 0, length = 0;
fs_reg sources[MAX_SAMPLER_MESSAGE_SIZE];
static void
lower_sampler_logical_send(const fs_builder &bld, fs_inst *inst, opcode op)
{
- const brw_device_info *devinfo = bld.shader->devinfo;
+ const gen_device_info *devinfo = bld.shader->devinfo;
const fs_reg &coordinate = inst->src[TEX_LOGICAL_SRC_COORDINATE];
const fs_reg &shadow_c = inst->src[TEX_LOGICAL_SRC_SHADOW_C];
const fs_reg &lod = inst->src[TEX_LOGICAL_SRC_LOD];
static void
lower_varying_pull_constant_logical_send(const fs_builder &bld, fs_inst *inst)
{
- const brw_device_info *devinfo = bld.shader->devinfo;
+ const gen_device_info *devinfo = bld.shader->devinfo;
if (devinfo->gen >= 7) {
/* We are switching the instruction from an ALU-like instruction to a
* excessively restrictive.
*/
static unsigned
-get_fpu_lowered_simd_width(const struct brw_device_info *devinfo,
+get_fpu_lowered_simd_width(const struct gen_device_info *devinfo,
const fs_inst *inst)
{
/* Maximum execution size representable in the instruction controls. */
max_width = MIN2(max_width, 16);
/* From the IVB PRMs (applies to other devices that don't have the
- * brw_device_info::supports_simd16_3src flag set):
+ * gen_device_info::supports_simd16_3src flag set):
* "In Align16 access mode, SIMD16 is not allowed for DW operations and
* SIMD8 is not allowed for DF operations."
*/
* represent).
*/
static unsigned
-get_sampler_lowered_simd_width(const struct brw_device_info *devinfo,
+get_sampler_lowered_simd_width(const struct gen_device_info *devinfo,
const fs_inst *inst)
{
/* Calculate the number of coordinate components that have to be present
* original execution size.
*/
static unsigned
-get_lowered_simd_width(const struct brw_device_info *devinfo,
+get_lowered_simd_width(const struct gen_device_info *devinfo,
const fs_inst *inst)
{
switch (inst->opcode) {
* also need the BRW_BARYCENTRIC_[NON]PERSPECTIVE_CENTROID mode set up.
*/
static unsigned
-brw_compute_barycentric_interp_modes(const struct brw_device_info *devinfo,
+brw_compute_barycentric_interp_modes(const struct gen_device_info *devinfo,
const nir_shader *shader)
{
unsigned barycentric_interp_modes = 0;
* Apply default interpolation settings to FS inputs which don't specify any.
*/
static void
-brw_nir_set_default_interpolation(const struct brw_device_info *devinfo,
+brw_nir_set_default_interpolation(const struct gen_device_info *devinfo,
struct nir_shader *nir,
bool api_flat_shade,
bool per_sample_interpolation)
}
static void
-cs_fill_push_const_info(const struct brw_device_info *devinfo,
+cs_fill_push_const_info(const struct gen_device_info *devinfo,
struct brw_cs_prog_data *cs_prog_data)
{
const struct brw_stage_prog_data *prog_data =
const struct brw_compiler *compiler;
void *log_data; /* Passed to compiler->*_log functions */
- const struct brw_device_info *devinfo;
+ const struct gen_device_info *devinfo;
struct brw_codegen *p;
const void * const key;
*/
static bool
-opt_cmod_propagation_local(const brw_device_info *devinfo, bblock_t *block)
+opt_cmod_propagation_local(const gen_device_info *devinfo, bblock_t *block)
{
bool progress = false;
int ip = block->end_ip + 1;
* replaced with a GRF source.
*/
static bool
-could_coissue(const struct brw_device_info *devinfo, const fs_inst *inst)
+could_coissue(const struct gen_device_info *devinfo, const fs_inst *inst)
{
if (devinfo->gen != 7)
return false;
* Returns true for instructions that don't support immediate sources.
*/
static bool
-must_promote_imm(const struct brw_device_info *devinfo, const fs_inst *inst)
+must_promote_imm(const struct gen_device_info *devinfo, const fs_inst *inst)
{
switch (inst->opcode) {
case SHADER_OPCODE_POW:
static bool
can_take_stride(fs_inst *inst, unsigned arg, unsigned stride,
- const brw_device_info *devinfo)
+ const gen_device_info *devinfo)
{
if (stride > 4)
return false;
fs_reg
setup_imm_df(const fs_builder &bld, double v)
{
- const struct brw_device_info *devinfo = bld.shader->devinfo;
+ const struct gen_device_info *devinfo = bld.shader->devinfo;
assert(devinfo->gen >= 7);
if (devinfo->gen >= 8)
static void
brw_alloc_reg_set(struct brw_compiler *compiler, int dispatch_width)
{
- const struct brw_device_info *devinfo = compiler->devinfo;
+ const struct gen_device_info *devinfo = compiler->devinfo;
int base_reg_count = BRW_MAX_GRF;
const int index = _mesa_logbase2(dispatch_width / 8);
emit_unspill(const fs_builder &bld, fs_reg dst,
uint32_t spill_offset, unsigned count)
{
- const brw_device_info *devinfo = bld.shader->devinfo;
+ const gen_device_info *devinfo = bld.shader->devinfo;
const unsigned reg_size = dst.component_size(bld.dispatch_width()) /
REG_SIZE;
assert(count % reg_size == 0);
* Return true if the format conversion boils down to a trivial copy.
*/
inline bool
- is_conversion_trivial(const brw_device_info *devinfo, isl_format format)
+ is_conversion_trivial(const gen_device_info *devinfo, isl_format format)
{
return (get_bit_widths(format).r == 32 && is_homogeneous(format)) ||
format == isl_lower_storage_image_format(devinfo, format);
* compatible bitfield layout, but possibly different data types.
*/
inline bool
- has_supported_bit_layout(const brw_device_info *devinfo,
+ has_supported_bit_layout(const gen_device_info *devinfo,
isl_format format)
{
const color_u widths = get_bit_widths(format);
* friends implemented as RGBA16UI).
*/
inline bool
- has_split_bit_layout(const brw_device_info *devinfo, isl_format format)
+ has_split_bit_layout(const gen_device_info *devinfo, isl_format format)
{
const isl_format lower_format =
isl_lower_storage_image_format(devinfo, format);
* significant bits.
*/
inline bool
- has_undefined_high_bits(const brw_device_info *devinfo,
+ has_undefined_high_bits(const gen_device_info *devinfo,
isl_format format)
{
const isl_format lower_format =
emit_untyped_image_check(const fs_builder &bld, const fs_reg &image,
brw_predicate pred)
{
- const brw_device_info *devinfo = bld.shader->devinfo;
+ const gen_device_info *devinfo = bld.shader->devinfo;
const fs_reg stride = offset(image, bld, BRW_IMAGE_PARAM_STRIDE_OFFSET);
if (devinfo->gen == 7 && !devinfo->is_haswell) {
brw_predicate
emit_typed_atomic_check(const fs_builder &bld, const fs_reg &image)
{
- const brw_device_info *devinfo = bld.shader->devinfo;
+ const gen_device_info *devinfo = bld.shader->devinfo;
const fs_reg size = offset(image, bld, BRW_IMAGE_PARAM_SIZE_OFFSET);
if (devinfo->gen == 7 && !devinfo->is_haswell) {
emit_address_calculation(const fs_builder &bld, const fs_reg &image,
const fs_reg &coord, unsigned dims)
{
- const brw_device_info *devinfo = bld.shader->devinfo;
+ const gen_device_info *devinfo = bld.shader->devinfo;
const fs_reg off = offset(image, bld, BRW_IMAGE_PARAM_OFFSET_OFFSET);
const fs_reg stride = offset(image, bld, BRW_IMAGE_PARAM_STRIDE_OFFSET);
const fs_reg tile = offset(image, bld, BRW_IMAGE_PARAM_TILING_OFFSET);
using namespace image_validity;
using namespace image_coordinates;
using namespace surface_access;
- const brw_device_info *devinfo = bld.shader->devinfo;
+ const gen_device_info *devinfo = bld.shader->devinfo;
const isl_format format = isl_format_for_gl_format(gl_format);
const isl_format lower_format =
isl_lower_storage_image_format(devinfo, format);
using namespace image_coordinates;
using namespace surface_access;
const isl_format format = isl_format_for_gl_format(gl_format);
- const brw_device_info *devinfo = bld.shader->devinfo;
+ const gen_device_info *devinfo = bld.shader->devinfo;
/* Transform the image coordinates into actual surface coordinates. */
const fs_reg saddr =
}
static void
-assign_gs_binding_table_offsets(const struct brw_device_info *devinfo,
+assign_gs_binding_table_offsets(const struct gen_device_info *devinfo,
const struct gl_shader_program *shader_prog,
const struct gl_program *prog,
struct brw_gs_prog_data *prog_data)
#define FC(name, high, low, assertions) \
static inline void \
-brw_inst_set_##name(const struct brw_device_info *devinfo, \
+brw_inst_set_##name(const struct gen_device_info *devinfo, \
brw_inst *inst, uint64_t v) \
{ \
assert(assertions); \
brw_inst_set_bits(inst, high, low, v); \
} \
static inline uint64_t \
-brw_inst_##name(const struct brw_device_info *devinfo, \
+brw_inst_##name(const struct gen_device_info *devinfo, \
const brw_inst *inst) \
{ \
assert(assertions); \
*/
#define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8)\
static inline void \
-brw_inst_set_##name(const struct brw_device_info *devinfo, \
+brw_inst_set_##name(const struct gen_device_info *devinfo, \
brw_inst *inst, uint64_t value) \
{ \
BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
brw_inst_set_bits(inst, high, low, value); \
} \
static inline uint64_t \
-brw_inst_##name(const struct brw_device_info *devinfo, const brw_inst *inst) \
+brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
{ \
BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
return brw_inst_bits(inst, high, low); \
* @{
*/
static inline void
-brw_inst_set_uip(const struct brw_device_info *devinfo,
+brw_inst_set_uip(const struct gen_device_info *devinfo,
brw_inst *inst, int32_t value)
{
assert(devinfo->gen >= 6);
}
static inline int32_t
-brw_inst_uip(const struct brw_device_info *devinfo, const brw_inst *inst)
+brw_inst_uip(const struct gen_device_info *devinfo, const brw_inst *inst)
{
assert(devinfo->gen >= 6);
}
static inline void
-brw_inst_set_jip(const struct brw_device_info *devinfo,
+brw_inst_set_jip(const struct gen_device_info *devinfo,
brw_inst *inst, int32_t value)
{
assert(devinfo->gen >= 6);
}
static inline int32_t
-brw_inst_jip(const struct brw_device_info *devinfo, const brw_inst *inst)
+brw_inst_jip(const struct gen_device_info *devinfo, const brw_inst *inst)
{
assert(devinfo->gen >= 6);
/** Like FC, but using int16_t to handle negative jump targets. */
#define FJ(name, high, low, assertions) \
static inline void \
-brw_inst_set_##name(const struct brw_device_info *devinfo, brw_inst *inst, int16_t v) \
+brw_inst_set_##name(const struct gen_device_info *devinfo, brw_inst *inst, int16_t v) \
{ \
assert(assertions); \
(void) devinfo; \
brw_inst_set_bits(inst, high, low, (uint16_t) v); \
} \
static inline int16_t \
-brw_inst_##name(const struct brw_device_info *devinfo, const brw_inst *inst) \
+brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
{ \
assert(assertions); \
(void) devinfo; \
* @{
*/
static inline int
-brw_inst_imm_d(const struct brw_device_info *devinfo, const brw_inst *insn)
+brw_inst_imm_d(const struct gen_device_info *devinfo, const brw_inst *insn)
{
(void) devinfo;
return brw_inst_bits(insn, 127, 96);
}
static inline unsigned
-brw_inst_imm_ud(const struct brw_device_info *devinfo, const brw_inst *insn)
+brw_inst_imm_ud(const struct gen_device_info *devinfo, const brw_inst *insn)
{
(void) devinfo;
return brw_inst_bits(insn, 127, 96);
}
static inline float
-brw_inst_imm_f(const struct brw_device_info *devinfo, const brw_inst *insn)
+brw_inst_imm_f(const struct gen_device_info *devinfo, const brw_inst *insn)
{
fi_type ft;
(void) devinfo;
}
static inline double
-brw_inst_imm_df(const struct brw_device_info *devinfo, const brw_inst *insn)
+brw_inst_imm_df(const struct gen_device_info *devinfo, const brw_inst *insn)
{
union {
double d;
}
static inline void
-brw_inst_set_imm_d(const struct brw_device_info *devinfo,
+brw_inst_set_imm_d(const struct gen_device_info *devinfo,
brw_inst *insn, int value)
{
(void) devinfo;
}
static inline void
-brw_inst_set_imm_ud(const struct brw_device_info *devinfo,
+brw_inst_set_imm_ud(const struct gen_device_info *devinfo,
brw_inst *insn, unsigned value)
{
(void) devinfo;
}
static inline void
-brw_inst_set_imm_f(const struct brw_device_info *devinfo,
+brw_inst_set_imm_f(const struct gen_device_info *devinfo,
brw_inst *insn, float value)
{
fi_type ft;
}
static inline void
-brw_inst_set_imm_df(const struct brw_device_info *devinfo,
+brw_inst_set_imm_df(const struct gen_device_info *devinfo,
brw_inst *insn, double value)
{
union {
/* The AddrImm fields are split into two discontiguous sections on Gen8+ */
#define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
static inline void \
-brw_inst_set_##reg##_ia1_addr_imm(const struct brw_device_info *devinfo, \
+brw_inst_set_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
brw_inst *inst, \
unsigned value) \
{ \
} \
} \
static inline unsigned \
-brw_inst_##reg##_ia1_addr_imm(const struct brw_device_info *devinfo, \
+brw_inst_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
const brw_inst *inst) \
{ \
if (devinfo->gen >= 8) { \
#define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
static inline void \
-brw_inst_set_##reg##_ia16_addr_imm(const struct brw_device_info *devinfo, \
+brw_inst_set_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
brw_inst *inst, unsigned value) \
{ \
assert((value & ~0x3ff) == 0); \
} \
} \
static inline unsigned \
-brw_inst_##reg##_ia16_addr_imm(const struct brw_device_info *devinfo, \
+brw_inst_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
const brw_inst *inst) \
{ \
if (devinfo->gen >= 8) { \
#define FC(name, high, low, assertions) \
static inline void \
-brw_compact_inst_set_##name(const struct brw_device_info *devinfo, \
+brw_compact_inst_set_##name(const struct gen_device_info *devinfo, \
brw_compact_inst *inst, unsigned v) \
{ \
assert(assertions); \
brw_compact_inst_set_bits(inst, high, low, v); \
} \
static inline unsigned \
-brw_compact_inst_##name(const struct brw_device_info *devinfo, \
+brw_compact_inst_##name(const struct gen_device_info *devinfo, \
const brw_compact_inst *inst) \
{ \
assert(assertions); \
bool is_copy_payload(const brw::simple_allocator &grf_alloc) const;
unsigned components_read(unsigned i) const;
int regs_read(int arg) const;
- bool can_do_source_mods(const struct brw_device_info *devinfo);
+ bool can_do_source_mods(const struct gen_device_info *devinfo);
bool can_change_types() const;
bool has_side_effects() const;
bool has_source_and_destination_hazard() const;
* Return the subset of flag registers read by the instruction as a bitset
* with byte granularity.
*/
- unsigned flags_read(const brw_device_info *devinfo) const;
+ unsigned flags_read(const gen_device_info *devinfo) const;
/**
* Return the subset of flag registers updated by the instruction (either
bool is_send_from_grf();
unsigned regs_read(unsigned arg) const;
- bool can_reswizzle(const struct brw_device_info *devinfo, int dst_writemask,
+ bool can_reswizzle(const struct gen_device_info *devinfo, int dst_writemask,
int swizzle, int swizzle_mask);
void reswizzle(int dst_writemask, int swizzle);
- bool can_do_source_mods(const struct brw_device_info *devinfo);
- bool can_do_writemask(const struct brw_device_info *devinfo);
+ bool can_do_source_mods(const struct gen_device_info *devinfo);
+ bool can_do_writemask(const struct gen_device_info *devinfo);
bool can_change_types() const;
bool has_source_and_destination_hazard() const;
void
brw_nir_lower_vs_inputs(nir_shader *nir,
- const struct brw_device_info *devinfo,
+ const struct gen_device_info *devinfo,
bool is_scalar,
bool use_legacy_snorm_formula,
const uint8_t *vs_attrib_wa_flags)
*/
nir_shader *
brw_postprocess_nir(nir_shader *nir,
- const struct brw_device_info *devinfo,
+ const struct gen_device_info *devinfo,
bool is_scalar)
{
bool debug_enabled =
nir_shader *
brw_nir_apply_sampler_key(nir_shader *nir,
- const struct brw_device_info *devinfo,
+ const struct gen_device_info *devinfo,
const struct brw_sampler_prog_key_data *key_tex,
bool is_scalar)
{
bool brw_nir_lower_intrinsics(nir_shader *nir,
struct brw_stage_prog_data *prog_data);
void brw_nir_lower_vs_inputs(nir_shader *nir,
- const struct brw_device_info *devinfo,
+ const struct gen_device_info *devinfo,
bool is_scalar,
bool use_legacy_snorm_formula,
const uint8_t *vs_attrib_wa_flags);
void brw_nir_lower_cs_shared(nir_shader *nir);
nir_shader *brw_postprocess_nir(nir_shader *nir,
- const struct brw_device_info *devinfo,
+ const struct gen_device_info *devinfo,
bool is_scalar);
bool brw_nir_apply_attribute_workarounds(nir_shader *nir,
void brw_nir_apply_tcs_quads_workaround(nir_shader *nir);
nir_shader *brw_nir_apply_sampler_key(nir_shader *nir,
- const struct brw_device_info *devinfo,
+ const struct gen_device_info *devinfo,
const struct brw_sampler_prog_key_data *key,
bool is_scalar);
int
brw_init_pipe_control(struct brw_context *brw,
- const struct brw_device_info *devinfo)
+ const struct gen_device_info *devinfo)
{
if (devinfo->gen < 6)
return 0;
extern "C" {
#endif
-struct brw_device_info;
+struct gen_device_info;
/** Number of general purpose registers (VS, WM, etc) */
#define BRW_MAX_GRF 128
BRW_REGISTER_TYPE_Q,
};
-unsigned brw_reg_type_to_hw_type(const struct brw_device_info *devinfo,
+unsigned brw_reg_type_to_hw_type(const struct gen_device_info *devinfo,
enum brw_reg_type type, enum brw_reg_file file);
const char *brw_reg_type_letters(unsigned brw_reg_type);
uint32_t brw_swizzle_immediate(enum brw_reg_type type, uint32_t x, unsigned swz);
schedule_node::schedule_node(backend_instruction *inst,
instruction_scheduler *sched)
{
- const struct brw_device_info *devinfo = sched->bs->devinfo;
+ const struct gen_device_info *devinfo = sched->bs->devinfo;
this->inst = inst;
this->child_array_size = 0;
void
instruction_scheduler::schedule_instructions(bblock_t *block)
{
- const struct brw_device_info *devinfo = bs->devinfo;
+ const struct gen_device_info *devinfo = bs->devinfo;
time = 0;
if (!post_reg_alloc)
reg_pressure = reg_pressure_in[block->num];
}
const char *
-brw_instruction_name(const struct brw_device_info *devinfo, enum opcode op)
+brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
{
switch (op) {
case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
}
bool
-backend_instruction::is_3src(const struct brw_device_info *devinfo) const
+backend_instruction::is_3src(const struct gen_device_info *devinfo) const
{
return ::is_3src(devinfo, opcode);
}
}
bool
-backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
+backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
{
return writes_accumulator ||
(devinfo->gen < 6 &&
*/
uint32_t
brw_assign_common_binding_table_offsets(gl_shader_stage stage,
- const struct brw_device_info *devinfo,
+ const struct gen_device_info *devinfo,
const struct gl_shader_program *shader_prog,
const struct gl_program *prog,
struct brw_stage_prog_data *stage_prog_data,
unsigned *final_assembly_size,
char **error_str)
{
- const struct brw_device_info *devinfo = compiler->devinfo;
+ const struct gen_device_info *devinfo = compiler->devinfo;
struct gl_linked_shader *shader =
shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
#ifdef __cplusplus
struct backend_instruction : public exec_node {
- bool is_3src(const struct brw_device_info *devinfo) const;
+ bool is_3src(const struct gen_device_info *devinfo) const;
bool is_tex() const;
bool is_math() const;
bool is_control_flow() const;
bool can_do_saturate() const;
bool can_do_cmod() const;
bool reads_accumulator_implicitly() const;
- bool writes_accumulator_implicitly(const struct brw_device_info *devinfo) const;
+ bool writes_accumulator_implicitly(const struct gen_device_info *devinfo) const;
void remove(bblock_t *block);
void insert_after(bblock_t *block, backend_instruction *inst);
const struct brw_compiler *compiler;
void *log_data; /* Passed to compiler->*_log functions */
- const struct brw_device_info * const devinfo;
+ const struct gen_device_info * const devinfo;
const nir_shader *nir;
struct brw_stage_prog_data * const stage_prog_data;
enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op);
uint32_t brw_math_function(enum opcode op);
-const char *brw_instruction_name(const struct brw_device_info *devinfo,
+const char *brw_instruction_name(const struct gen_device_info *devinfo,
enum opcode op);
bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg);
bool brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg);
uint32_t
brw_assign_common_binding_table_offsets(gl_shader_stage stage,
- const struct brw_device_info *devinfo,
+ const struct gen_device_info *devinfo,
const struct gl_shader_program *shader_prog,
const struct gl_program *prog,
struct brw_stage_prog_data *stage_prog_data,
void
brw_init_surface_formats(struct brw_context *brw)
{
- const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
+ const struct gen_device_info *devinfo = brw->intelScreen->devinfo;
struct gl_context *ctx = &brw->ctx;
int gen;
mesa_format format;
{
struct gl_context *ctx = &brw->ctx;
const struct brw_compiler *compiler = brw->intelScreen->compiler;
- const struct brw_device_info *devinfo = compiler->devinfo;
+ const struct gen_device_info *devinfo = compiler->devinfo;
struct brw_stage_state *stage_state = &brw->tcs.base;
nir_shader *nir;
struct brw_tcs_prog_data prog_data;
struct brw_tes_prog_key *key)
{
const struct brw_compiler *compiler = brw->intelScreen->compiler;
- const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
+ const struct gen_device_info *devinfo = brw->intelScreen->devinfo;
struct brw_stage_state *stage_state = &brw->tes.base;
nir_shader *nir = tep->program.Base.nir;
struct brw_tes_prog_data prog_data;
}
bool
-vec4_instruction::can_do_source_mods(const struct brw_device_info *devinfo)
+vec4_instruction::can_do_source_mods(const struct gen_device_info *devinfo)
{
if (devinfo->gen == 6 && is_math())
return false;
}
bool
-vec4_instruction::can_do_writemask(const struct brw_device_info *devinfo)
+vec4_instruction::can_do_writemask(const struct gen_device_info *devinfo)
{
switch (opcode) {
case SHADER_OPCODE_GEN4_SCRATCH_READ:
}
bool
-vec4_instruction::can_reswizzle(const struct brw_device_info *devinfo,
+vec4_instruction::can_reswizzle(const struct gen_device_info *devinfo,
int dst_writemask,
int swizzle,
int swizzle_mask)
}
static bool
-try_constant_propagate(const struct brw_device_info *devinfo,
+try_constant_propagate(const struct gen_device_info *devinfo,
vec4_instruction *inst,
int arg, const copy_entry *entry)
{
}
static bool
-try_copy_propagate(const struct brw_device_info *devinfo,
+try_copy_propagate(const struct gen_device_info *devinfo,
vec4_instruction *inst, int arg,
const copy_entry *entry, int attributes_per_reg)
{
struct brw_reg surface_index,
struct brw_reg sampler_index)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
int msg_type = -1;
if (devinfo->gen >= 5) {
static void
generate_tcs_get_instance_id(struct brw_codegen *p, struct brw_reg dst)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
const bool ivb = devinfo->is_ivybridge || devinfo->is_baytrail;
/* "Instance Count" comes as part of the payload in r0.2 bits 23:17.
vec4_instruction *inst,
struct brw_reg urb_header)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
brw_set_dest(p, send, brw_null_reg());
struct brw_reg dst,
struct brw_reg header)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
assert(header.file == BRW_GENERAL_REGISTER_FILE);
assert(header.type == BRW_REGISTER_TYPE_UD);
struct brw_reg vertex,
struct brw_reg is_unpaired)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
assert(vertex.file == BRW_IMMEDIATE_VALUE);
assert(vertex.type == BRW_REGISTER_TYPE_UD);
struct brw_vue_prog_data *prog_data,
struct brw_reg dst)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
const bool ivb = devinfo->is_ivybridge || devinfo->is_baytrail;
struct brw_reg m0_2 = get_element_ud(dst, 2);
unsigned instances = ((struct brw_tcs_prog_data *) prog_data)->instances;
struct brw_reg dst,
struct brw_reg index)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
struct brw_reg header = brw_vec8_grf(0, 0);
gen6_resolve_implied_move(p, &header, inst->base_mrf);
struct brw_reg src,
struct brw_reg index)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
struct brw_reg header = brw_vec8_grf(0, 0);
bool write_commit;
struct brw_reg index,
struct brw_reg offset)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
assert(index.file == BRW_IMMEDIATE_VALUE &&
index.type == BRW_REGISTER_TYPE_UD);
uint32_t surf_index = index.ud;
struct brw_vue_prog_data *prog_data,
const struct cfg_t *cfg)
{
- const struct brw_device_info *devinfo = p->devinfo;
+ const struct gen_device_info *devinfo = p->devinfo;
const char *stage_abbrev = _mesa_shader_stage_to_abbrev(nir->stage);
bool debug_flag = INTEL_DEBUG &
intel_debug_flag_for_shader_stage(nir->stage);
unsigned *final_assembly_size,
char **error_str)
{
- const struct brw_device_info *devinfo = compiler->devinfo;
+ const struct gen_device_info *devinfo = compiler->devinfo;
struct brw_vue_prog_data *vue_prog_data = &prog_data->base;
const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_CTRL];
}
static int
-align_interleaved_urb_mlen(const struct brw_device_info *devinfo, int mlen)
+align_interleaved_urb_mlen(const struct gen_device_info *devinfo, int mlen)
{
if (devinfo->gen >= 6) {
/* URB data written (does not include the message header reg) must
* Compute the VUE map for a shader stage.
*/
void
-brw_compute_vue_map(const struct brw_device_info *devinfo,
+brw_compute_vue_map(const struct gen_device_info *devinfo,
struct brw_vue_map *vue_map,
GLbitfield64 slots_valid,
bool separate)
#include "util/ralloc.h"
static void
-assign_fs_binding_table_offsets(const struct brw_device_info *devinfo,
+assign_fs_binding_table_offsets(const struct gen_device_info *devinfo,
const struct gl_shader_program *shader_prog,
const struct gl_program *prog,
const struct brw_wm_prog_key *key,
static uint32_t
get_image_format(struct brw_context *brw, mesa_format format, GLenum access)
{
- const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
+ const struct gen_device_info *devinfo = brw->intelScreen->devinfo;
uint32_t hw_format = brw_format_for_mesa_format(format);
if (access == GL_WRITE_ONLY) {
return hw_format;
struct brw_stage_state *stage_state = &brw->cs.base;
struct brw_cs_prog_data *cs_prog_data = brw->cs.prog_data;
struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
- const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
+ const struct gen_device_info *devinfo = brw->intelScreen->devinfo;
if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
brw_emit_buffer_surface_state(
* specified device.
*/
static const struct brw_l3_config *
-get_l3_configs(const struct brw_device_info *devinfo)
+get_l3_configs(const struct gen_device_info *devinfo)
{
switch (devinfo->gen) {
case 7:
* Return the size of an L3 way in KB.
*/
static unsigned
-get_l3_way_size(const struct brw_device_info *devinfo)
+get_l3_way_size(const struct gen_device_info *devinfo)
{
if (devinfo->is_baytrail)
return 2;
* weight vector.
*/
static const struct brw_l3_config *
-get_l3_config(const struct brw_device_info *devinfo, struct brw_l3_weights w0)
+get_l3_config(const struct gen_device_info *devinfo, struct brw_l3_weights w0)
{
const struct brw_l3_config *const cfgs = get_l3_configs(devinfo);
const struct brw_l3_config *cfg_best = NULL;
* is intended to approximately resemble the hardware defaults.
*/
static struct brw_l3_weights
-get_default_l3_weights(const struct brw_device_info *devinfo,
+get_default_l3_weights(const struct gen_device_info *devinfo,
bool needs_dc, bool needs_slm)
{
struct brw_l3_weights w = {{ 0 }};
/**
* Return the unit brw_context::urb::size is expressed in, in KB. \sa
- * brw_device_info::urb::size.
+ * gen_device_info::urb::size.
*/
static unsigned
-get_urb_size_scale(const struct brw_device_info *devinfo)
+get_urb_size_scale(const struct gen_device_info *devinfo)
{
return (devinfo->gen >= 8 ? devinfo->num_slices : 1);
}
static void
update_urb_size(struct brw_context *brw, const struct brw_l3_config *cfg)
{
- const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
+ const struct gen_device_info *devinfo = brw->intelScreen->devinfo;
/* From the SKL "L3 Allocation and Programming" documentation:
*
* "URB is limited to 1008KB due to programming restrictions. This is not
void
gen7_restore_default_l3_config(struct brw_context *brw)
{
- const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
+ const struct gen_device_info *devinfo = brw->intelScreen->devinfo;
/* For efficiency assume that the first entry of the array matches the
* default configuration.
*/
gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
bool gs_present, bool tess_present)
{
- const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
+ const struct gen_device_info *devinfo = brw->intelScreen->devinfo;
const int push_size_kB =
(brw->gen >= 8 || (brw->is_haswell && brw->gt == 3)) ? 32 : 16;
void
dump_assembly(void *assembly, int num_annotations, struct annotation *annotation,
- const struct brw_device_info *devinfo)
+ const struct gen_device_info *devinfo)
{
const char *last_annotation_string = NULL;
const void *last_annotation_ir = NULL;
return true;
}
-void annotate(const struct brw_device_info *devinfo,
+void annotate(const struct gen_device_info *devinfo,
struct annotation_info *annotation, const struct cfg_t *cfg,
struct backend_instruction *inst, unsigned offset)
{
void
dump_assembly(void *assembly, int num_annotations, struct annotation *annotation,
- const struct brw_device_info *devinfo);
+ const struct gen_device_info *devinfo);
void
-annotate(const struct brw_device_info *devinfo,
+annotate(const struct gen_device_info *devinfo,
struct annotation_info *annotation, const struct cfg_t *cfg,
struct backend_instruction *inst, unsigned offset);
void
static const uint8_t multisample_samples[2] = {4, 8};
struct intel_screen *screen = dri_screen->driverPrivate;
- const struct brw_device_info *devinfo = screen->devinfo;
+ const struct gen_device_info *devinfo = screen->devinfo;
uint8_t depth_bits[4], stencil_bits[4];
__DRIconfig **configs = NULL;
#include "dri_util.h"
#include "intel_bufmgr.h"
-#include "common/brw_device_info.h"
+#include "common/gen_device_info.h"
#include "i915_drm.h"
#include "xmlconfig.h"
struct intel_screen
{
int deviceID;
- const struct brw_device_info *devinfo;
+ const struct gen_device_info *devinfo;
__DRIscreen *driScrnPriv;
* become meaningless once fuzzing twiddles a related bit.
*/
static void
-clear_pad_bits(const struct brw_device_info *devinfo, brw_inst *inst)
+clear_pad_bits(const struct gen_device_info *devinfo, brw_inst *inst)
{
if (brw_inst_opcode(devinfo, inst) != BRW_OPCODE_SEND &&
brw_inst_opcode(devinfo, inst) != BRW_OPCODE_SENDC &&
}
static bool
-skip_bit(const struct brw_device_info *devinfo, brw_inst *src, int bit)
+skip_bit(const struct gen_device_info *devinfo, brw_inst *src, int bit)
{
/* pad bit */
if (bit == 7)
};
static bool
-run_tests(const struct brw_device_info *devinfo)
+run_tests(const struct gen_device_info *devinfo)
{
bool fail = false;
int
main(int argc, char **argv)
{
- struct brw_device_info *devinfo = calloc(1, sizeof(*devinfo));
+ struct gen_device_info *devinfo = calloc(1, sizeof(*devinfo));
devinfo->gen = 6;
bool fail = false;
public:
struct brw_compiler *compiler;
- struct brw_device_info *devinfo;
+ struct gen_device_info *devinfo;
struct gl_context *ctx;
struct brw_wm_prog_data *prog_data;
struct gl_shader_program *shader_prog;
{
ctx = (struct gl_context *)calloc(1, sizeof(*ctx));
compiler = (struct brw_compiler *)calloc(1, sizeof(*compiler));
- devinfo = (struct brw_device_info *)calloc(1, sizeof(*devinfo));
+ devinfo = (struct gen_device_info *)calloc(1, sizeof(*devinfo));
compiler->devinfo = devinfo;
prog_data = ralloc(NULL, struct brw_wm_prog_data);
public:
struct brw_compiler *compiler;
- struct brw_device_info *devinfo;
+ struct gen_device_info *devinfo;
struct gl_context *ctx;
struct brw_wm_prog_data *prog_data;
struct gl_shader_program *shader_prog;
{
ctx = (struct gl_context *)calloc(1, sizeof(*ctx));
compiler = (struct brw_compiler *)calloc(1, sizeof(*compiler));
- devinfo = (struct brw_device_info *)calloc(1, sizeof(*devinfo));
+ devinfo = (struct gen_device_info *)calloc(1, sizeof(*devinfo));
compiler->devinfo = devinfo;
prog_data = ralloc(NULL, struct brw_wm_prog_data);
public:
struct brw_compiler *compiler;
- struct brw_device_info *devinfo;
+ struct gen_device_info *devinfo;
struct gl_context *ctx;
struct gl_shader_program *shader_prog;
struct brw_vue_prog_data *prog_data;
{
ctx = (struct gl_context *)calloc(1, sizeof(*ctx));
compiler = (struct brw_compiler *)calloc(1, sizeof(*compiler));
- devinfo = (struct brw_device_info *)calloc(1, sizeof(*devinfo));
+ devinfo = (struct gen_device_info *)calloc(1, sizeof(*devinfo));
prog_data = (struct brw_vue_prog_data *)calloc(1, sizeof(*prog_data));
compiler->devinfo = devinfo;
public:
struct brw_compiler *compiler;
- struct brw_device_info *devinfo;
+ struct gen_device_info *devinfo;
struct gl_context *ctx;
struct gl_shader_program *shader_prog;
struct brw_vue_prog_data *prog_data;
{
ctx = (struct gl_context *)calloc(1, sizeof(*ctx));
compiler = (struct brw_compiler *)calloc(1, sizeof(*compiler));
- devinfo = (struct brw_device_info *)calloc(1, sizeof(*devinfo));
+ devinfo = (struct gen_device_info *)calloc(1, sizeof(*devinfo));
prog_data = (struct brw_vue_prog_data *)calloc(1, sizeof(*prog_data));
compiler->devinfo = devinfo;
public:
struct brw_compiler *compiler;
- struct brw_device_info *devinfo;
+ struct gen_device_info *devinfo;
struct gl_context *ctx;
struct gl_shader_program *shader_prog;
struct brw_vue_prog_data *prog_data;
{
ctx = (struct gl_context *)calloc(1, sizeof(*ctx));
compiler = (struct brw_compiler *)calloc(1, sizeof(*compiler));
- devinfo = (struct brw_device_info *)calloc(1, sizeof(*devinfo));
+ devinfo = (struct gen_device_info *)calloc(1, sizeof(*devinfo));
prog_data = (struct brw_vue_prog_data *)calloc(1, sizeof(*prog_data));
compiler->devinfo = devinfo;
projects / mesa.git / commitdiff