CPU: Tidy up endianness handling for mmapped "IPR"s.

diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 41b0f2043d8e2496ca63a36b4dc629ffef928820..9d3b22657af6e7ebea61e6fb6c30ce673580919b 100644 (file)
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -1049,7 +1049,7 @@ doMmuReadError:
 Tick
 TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
 {
-    uint64_t data = gtoh(pkt->get<uint64_t>());
+    uint64_t data = pkt->get<uint64_t>();
     Addr va = pkt->getAddr();
     ASI asi = (ASI)pkt->req->getAsi();
 

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index d96adffd5dc9315bbb1de0b909395c3a2567f2c8..f8819c7349a52d914f905b9dd0986251d16078e4 100644 (file)
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -450,6 +450,8 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         traceData->setData(data);
     }
 
+    data = htog(data);
+
     //The block size of our peer.
     unsigned blockSize = dcachePort.peerBlockSize();
     //The size of the data we're trying to read.
@@ -496,10 +498,6 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
                     dcache_latency +=
                         TheISA::handleIprWrite(thread->getTC(), &pkt);
                 } else {
-                    //XXX This needs to be outside of the loop in order to
-                    //work properly for cache line boundary crossing
-                    //accesses in transendian simulations.
-                    data = htog(data);
                     if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
                         dcache_latency += physmemPort.sendAtomic(&pkt);
                     else