accidental removal of bold

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index fd2c133ce247669828f1791fccbe51a5afd97cba..c772af8071e770446044b0554b9e2515ed5886c3 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -1,4 +1,4 @@
-# OPF ISA WG External RFC LS001 v2 14Sep2022
+# OPF ISA WG External RFC LS001 v3 24mar2022
 
 * RFC Author: Luke Kenneth Casson Leighton.
 * RFC Contributors/Ideas: Brad Frey, Paul Mackerras, Konstantinos Magritis,
@@ -10,8 +10,8 @@
   [[ls001/discussion]]
 
 This proposal is to extend the Power ISA with an Abstract RISC-Paradigm
-Vectorisation Concept that may be orthogonally applied to **all and any** suitable
-Scalar instructions, present and future, in the Scalar Power ISA.
+Vectorisation Concept that may be orthogonally applied to **all and any**
+suitable Scalar instructions, present and future, in the Scalar Power ISA.
 The Vectorisation System is called
 ["Simple-V"](https://libre-soc.org/openpower/sv/)
 and the Prefix Format is called
@@ -33,7 +33,7 @@ Stakeholder, is to bring to market mass-volume general-purpose compute
 processors that are competitive in the 3D GPU Audio Visual DSP EDGE IoT
 desktop chromebook netbook smartphone laptop markets, performance-leveraged
 by Simple-V.  To achieve this goal both Simple-V and accompanying
-Scalar** Power ISA instructions are needed.  These include IEEE754
+**Scalar** Power ISA instructions are needed.  These include IEEE754
 [Transcendentals](https://libre-soc.org/openpower/transcendentals/)
 [AV](https://libre-soc.org/openpower/sv/av_opcodes/)
 cryptographic