Add more checks in delayed_enter

diff --git a/gram/compat.py b/gram/compat.py
index 6f72d5ea5d4170da2af2f839f33ea230aa227a60..c05300650fdc7d9cd8956a7715e2abfdd0e6c5ab 100644 (file)
--- a/gram/compat.py
+++ b/gram/compat.py
@@ -11,7 +11,12 @@ __ALL__ = ["delayed_enter", "Timeline", "CSRPrefixProxy"]
 
 
 def delayed_enter(m, src, dst, delay):
-    assert delay > 0
+    if not isinstance(m, Module):
+        raise ValueError("m must be a module object, not {!r}".format(m))
+    if not isinstance(delay, int):
+        raise ValueError("Delay must be an integer, not {!r}".format(delay))
+    if delay < 1:
+        raise ValueError("Delay must be at least one cycle, not {!r}".format(delay))
 
     for i in range(delay):
         if i == 0:

diff --git a/gram/test/test_compat.py b/gram/test/test_compat.py
index 47934729662ba1454d553667b2a7f34070678c61..4835bd5e4d1c4f497c3c08bafdf095f2767f3813 100644 (file)
--- a/gram/test/test_compat.py
+++ b/gram/test/test_compat.py
@@ -37,7 +37,7 @@ class DelayedEnterTestCase(FHDLTestCase):
 
             runSimulation(m, process, "test_delayedenter.vcd")
 
-        with self.assertRaises(AssertionError):
+        with self.assertRaises(ValueError):
             sequence(0)
         sequence(1)
         sequence(2)