+++ /dev/null
-generate
-generate.lst
-rtl
-xst
-xst_temp
-vivado
-vivado_temp
-quartus
-quartus_temp
-report
-report_temp
-check
-check_temp
-check_vivado
-check_quartus
+++ /dev/null
-
-include generate.lst
-
-test: $(TARGETS)
-
-vivado: $(addprefix check_vivado/,$(notdir $(TARGETS)))
-
-quartus: $(addprefix check_quartus/,$(notdir $(TARGETS)))
-
-report:
- ls check check_quartus/ check_vivado | grep '\.err$$' | sort -u | cut -f1 -d. | gawk '{ print "report/" $$0 ".html"; }' | xargs -r $(MAKE)
-
-report/%.html:
- bash report.sh $(notdir $(basename $@))
-
-check/%.log: rtl/%.v xst/%.v
- bash run-check.sh $(notdir $(basename $<))
-
-check_vivado/%.log: rtl/%.v vivado/%.v
- bash run-check.sh -vivado $(notdir $(basename $<))
-
-check_quartus/%.log: rtl/%.v quartus/%.v
- bash run-check.sh -quartus $(notdir $(basename $<))
-
-xst/%.v: rtl/%.v
- bash run-xst.sh $(notdir $(basename $<))
-
-vivado/%.v: rtl/%.v
- bash run-vivado.sh $(notdir $(basename $<))
-
-quartus/%.v: rtl/%.v
- bash run-quartus.sh $(notdir $(basename $<))
-
-generate.lst: generate.cc
- clang -Wall -o generate generate.cc -lstdc++
- ./generate
- { echo -n "TARGETS := "; ls rtl/ | sed 's,\.v$$,.log,; s,^,check/,;' | tr '\n' ' '; } > generate.lst
-
-check_xl_cells:
- ../../yosys xl_cells_tb.ys
-
-clean:
- rm -rf generate generate.lst check_temp xst_temp
-
-mrproper: clean
- rm -rf rtl xst check
-
-backup:
- mkdir -p ~/.yosys/xhammer
- tar cvzf ~/.yosys/xhammer/xst_files.tar.gz xst
- tar cvzf ~/.yosys/xhammer/vivado_files.tar.gz vivado
- tar cvzf ~/.yosys/xhammer/quartus_files.tar.gz quartus
-
-restore:
- tar xvzf ~/.yosys/xhammer/xst_files.tar.gz
- tar xvzf ~/.yosys/xhammer/vivado_files.tar.gz
- tar xvzf ~/.yosys/xhammer/quartus_files.tar.gz
-
-.PHONY: test vivado quartus report check_xl_cells clean mrproper backup restore
-.PRECIOUS: check/%.log xst/%.v vivado/%.v quartus/%.v rtl/%.v generate.lst
-
+++ /dev/null
-
- ================================
- This is work under construction!
- ================================
-
-
-This is going to be a collection of auto-generated test cases. The goal is
-to synthesize them with Yosys and Xilinx XST and perform formal equivialence
-checks using the Yosys SAT-based equivialence checker. This will hopefully
-reveal some bugs in both applications.. ;-)
-
-Simply run 'make' to generate all test cases and run all the tests.
-(Use 'make -j N' to use N parallel cores.)
-
+++ /dev/null
-
-// Based on the simulation models from /opt/altera/13.0/quartus/eda/sim_lib/cycloneiii_atoms.v
-
-module cycloneiii_lcell_comb (dataa, datab, datac, datad, cin, combout, cout);
-
-input dataa, datab, datac, datad, cin;
-output combout, cout;
-
-parameter lut_mask = 16'hFFFF;
-parameter sum_lutc_input = "datac";
-parameter dont_touch = "off";
-parameter lpm_type = "cycloneiii_lcell_comb";
-
-reg cout_tmp, combout_tmp;
-reg [1:0] isum_lutc_input;
-
-// 4-input LUT function
-function lut4;
- input [15:0] mask;
- input dataa, datab, datac, datad;
- begin
- lut4 = datad ? ( datac ? ( datab ? ( dataa ? mask[15] : mask[14])
- : ( dataa ? mask[13] : mask[12]))
- : ( datab ? ( dataa ? mask[11] : mask[10])
- : ( dataa ? mask[ 9] : mask[ 8])))
- : ( datac ? ( datab ? ( dataa ? mask[ 7] : mask[ 6])
- : ( dataa ? mask[ 5] : mask[ 4]))
- : ( datab ? ( dataa ? mask[ 3] : mask[ 2])
- : ( dataa ? mask[ 1] : mask[ 0])));
- end
-endfunction
-
-initial
- if (sum_lutc_input == "datac")
- isum_lutc_input = 0;
- else if (sum_lutc_input == "cin")
- isum_lutc_input = 1;
- else
- isum_lutc_input = 2;
-
-always @* begin
- if (isum_lutc_input == 0) // datac
- combout_tmp = lut4(lut_mask, dataa, datab, datac, datad);
- else if (isum_lutc_input == 1) // cin
- combout_tmp = lut4(lut_mask, dataa, datab, cin, datad);
- cout_tmp = lut4(lut_mask, dataa, datab, cin, 'b0);
-end
-
-assign combout = combout_tmp;
-assign cout = cout_tmp;
-
-endmodule
-
-// ----------------------------------------------------------------------
-
-module cycloneiii_io_ibuf (i, ibar, o);
-
-parameter differential_mode = "false";
-parameter bus_hold = "false";
-parameter simulate_z_as = "Z";
-parameter lpm_type = "cycloneiii_io_ibuf";
-
-input i, ibar;
-output o;
-
-assign o = i;
-
-endmodule
-
-// ----------------------------------------------------------------------
-
-module cycloneiii_io_obuf (i, oe, seriesterminationcontrol, devoe, o, obar);
-
-parameter open_drain_output = "false";
-parameter bus_hold = "false";
-parameter lpm_type = "cycloneiii_io_obuf";
-
-input i, oe, devoe;
-input [15:0] seriesterminationcontrol;
-output o, obar;
-
-assign o = i;
-assign obar = ~i;
-
-endmodule
-
-// ----------------------------------------------------------------------
-
-module cycloneiii_mac_data_reg (clk,
- data,
- ena,
- aclr,
- dataout
- );
-
- parameter data_width = 18;
-
- // INPUT PORTS
- input clk;
- input [17 : 0] data;
- input ena;
- input aclr;
-
- // OUTPUT PORTS
- output [17:0] dataout;
-
- // INTERNAL VARIABLES AND NETS
- reg clk_last_value;
- reg [17:0] dataout_tmp;
- wire [17:0] dataout_wire;
-
- // INTERNAL VARIABLES
- wire [17:0] data_ipd;
- wire enable;
- wire no_clr;
- reg d_viol;
- reg ena_viol;
- wire clk_ipd;
- wire ena_ipd;
- wire aclr_ipd;
-
-
- // BUFFER INPUTS
- buf (clk_ipd, clk);
- buf (ena_ipd, ena);
- buf (aclr_ipd, aclr);
-
- buf (data_ipd[0], data[0]);
- buf (data_ipd[1], data[1]);
- buf (data_ipd[2], data[2]);
- buf (data_ipd[3], data[3]);
- buf (data_ipd[4], data[4]);
- buf (data_ipd[5], data[5]);
- buf (data_ipd[6], data[6]);
- buf (data_ipd[7], data[7]);
- buf (data_ipd[8], data[8]);
- buf (data_ipd[9], data[9]);
- buf (data_ipd[10], data[10]);
- buf (data_ipd[11], data[11]);
- buf (data_ipd[12], data[12]);
- buf (data_ipd[13], data[13]);
- buf (data_ipd[14], data[14]);
- buf (data_ipd[15], data[15]);
- buf (data_ipd[16], data[16]);
- buf (data_ipd[17], data[17]);
-
- assign enable = (!aclr_ipd) && (ena_ipd);
- assign no_clr = (!aclr_ipd);
-
- initial
- begin
- clk_last_value <= 'b0;
- dataout_tmp <= 18'b0;
- end
-
- always @(clk_ipd or aclr_ipd)
- begin
- if (d_viol == 1'b1 || ena_viol == 1'b1)
- begin
- dataout_tmp <= 'bX;
- end
- else if (aclr_ipd == 1'b1)
- begin
- dataout_tmp <= 'b0;
- end
- else
- begin
- if ((clk_ipd === 1'b1) && (clk_last_value == 1'b0))
- if (ena_ipd === 1'b1)
- dataout_tmp <= data_ipd;
- end
-
- clk_last_value <= clk_ipd;
-
- end // always
-
- assign dataout_wire = dataout_tmp;
-
- and (dataout[0], dataout_wire[0], 1'b1);
- and (dataout[1], dataout_wire[1], 1'b1);
- and (dataout[2], dataout_wire[2], 1'b1);
- and (dataout[3], dataout_wire[3], 1'b1);
- and (dataout[4], dataout_wire[4], 1'b1);
- and (dataout[5], dataout_wire[5], 1'b1);
- and (dataout[6], dataout_wire[6], 1'b1);
- and (dataout[7], dataout_wire[7], 1'b1);
- and (dataout[8], dataout_wire[8], 1'b1);
- and (dataout[9], dataout_wire[9], 1'b1);
- and (dataout[10], dataout_wire[10], 1'b1);
- and (dataout[11], dataout_wire[11], 1'b1);
- and (dataout[12], dataout_wire[12], 1'b1);
- and (dataout[13], dataout_wire[13], 1'b1);
- and (dataout[14], dataout_wire[14], 1'b1);
- and (dataout[15], dataout_wire[15], 1'b1);
- and (dataout[16], dataout_wire[16], 1'b1);
- and (dataout[17], dataout_wire[17], 1'b1);
-
-endmodule //cycloneiii_mac_data_reg
-
-module cycloneiii_mac_sign_reg (
- clk,
- d,
- ena,
- aclr,
- q
- );
-
- // INPUT PORTS
- input clk;
- input d;
- input ena;
- input aclr;
-
- // OUTPUT PORTS
- output q;
-
- // INTERNAL VARIABLES
- reg clk_last_value;
- reg q_tmp;
- reg ena_viol;
- reg d_viol;
-
- wire enable;
-
- // DEFAULT VALUES THRO' PULLUPs
- // tri1 aclr, ena;
-
- wire d_ipd;
- wire clk_ipd;
- wire ena_ipd;
- wire aclr_ipd;
-
- buf (d_ipd, d);
- buf (clk_ipd, clk);
- buf (ena_ipd, ena);
- buf (aclr_ipd, aclr);
-
- assign enable = (!aclr_ipd) && (ena_ipd);
-
- initial
- begin
- clk_last_value <= 'b0;
- q_tmp <= 'b0;
- end
-
- always @ (clk_ipd or aclr_ipd)
- begin
- if (d_viol == 1'b1 || ena_viol == 1'b1)
- begin
- q_tmp <= 'bX;
- end
- else
- begin
- if (aclr_ipd == 1'b1)
- q_tmp <= 0;
- else if ((clk_ipd == 1'b1) && (clk_last_value == 1'b0))
- if (ena_ipd == 1'b1)
- q_tmp <= d_ipd;
- end
-
- clk_last_value <= clk_ipd;
- end
-
- and (q, q_tmp, 'b1);
-
-endmodule // cycloneiii_mac_sign_reg
-
-module cycloneiii_mac_mult_internal
- (
- dataa,
- datab,
- signa,
- signb,
- dataout
- );
-
- parameter dataa_width = 18;
- parameter datab_width = 18;
- parameter dataout_width = dataa_width + datab_width;
-
- // INPUT
- input [dataa_width-1:0] dataa;
- input [datab_width-1:0] datab;
- input signa;
- input signb;
-
- // OUTPUT
- output [dataout_width-1:0] dataout;
-
- // Internal variables
- wire [17:0] dataa_ipd;
- wire [17:0] datab_ipd;
- wire signa_ipd;
- wire signb_ipd;
-
- wire [dataout_width-1:0] dataout_tmp;
-
- wire ia_is_positive;
- wire ib_is_positive;
- wire [17:0] iabsa; // absolute value (i.e. positive) form of dataa input
- wire [17:0] iabsb; // absolute value (i.e. positive) form of datab input
- wire [35:0] iabsresult; // absolute value (i.e. positive) form of product (a * b)
-
-
- reg [17:0] i_ones; // padding with 1's for input negation
-
- // Input buffers
- buf (signa_ipd, signa);
- buf (signb_ipd, signb);
-
- // buf dataa_buf [dataa_width-1:0] (dataa_ipd[dataa_width-1:0], dataa);
- // buf datab_buf [datab_width-1:0] (datab_ipd[datab_width-1:0], datab);
- assign dataa_ipd[dataa_width-1:0] = dataa;
- assign datab_ipd[datab_width-1:0] = datab;
-
- initial
- begin
- // 1's padding for 18-bit wide inputs
- i_ones = ~0;
- end
-
- // get signs of a and b, and get absolute values since Verilog '*' operator
- // is an unsigned multiplication
- assign ia_is_positive = ~signa_ipd | ~dataa_ipd[dataa_width-1];
- assign ib_is_positive = ~signb_ipd | ~datab_ipd[datab_width-1];
-
- assign iabsa = ia_is_positive == 1 ? dataa_ipd[dataa_width-1:0] : -(dataa_ipd | (i_ones << dataa_width));
- assign iabsb = ib_is_positive == 1 ? datab_ipd[datab_width-1:0] : -(datab_ipd | (i_ones << datab_width));
-
- // multiply a * b
- assign iabsresult = iabsa * iabsb;
- assign dataout_tmp = (ia_is_positive ^ ib_is_positive) == 1 ? -iabsresult : iabsresult;
-
- // buf dataout_buf [dataout_width-1:0] (dataout, dataout_tmp);
- assign dataout = dataout_tmp;
-
-endmodule
-
-module cycloneiii_mac_mult
- (
- dataa,
- datab,
- signa,
- signb,
- clk,
- aclr,
- ena,
- dataout,
- devclrn,
- devpor
- );
-
- parameter dataa_width = 18;
- parameter datab_width = 18;
- parameter dataa_clock = "none";
- parameter datab_clock = "none";
- parameter signa_clock = "none";
- parameter signb_clock = "none";
- parameter lpm_hint = "true";
- parameter lpm_type = "cycloneiii_mac_mult";
-
-// SIMULATION_ONLY_PARAMETERS_BEGIN
-
- parameter dataout_width = dataa_width + datab_width;
-
-// SIMULATION_ONLY_PARAMETERS_END
-
- input [dataa_width-1:0] dataa;
- input [datab_width-1:0] datab;
- input signa;
- input signb;
- input clk;
- input aclr;
- input ena;
- input devclrn;
- input devpor;
-
- output [dataout_width-1:0] dataout;
-
- // tri1 devclrn;
- // tri1 devpor;
-
- wire [dataout_width-1:0] dataout_tmp;
-
- wire [17:0] idataa_reg; // optional register for dataa input
- wire [17:0] idatab_reg; // optional register for datab input
- wire [17:0] dataa_pad; // padded dataa input
- wire [17:0] datab_pad; // padded datab input
- wire isigna_reg; // optional register for signa input
- wire isignb_reg; // optional register for signb input
-
- wire [17:0] idataa_int; // dataa as seen by the multiplier input
- wire [17:0] idatab_int; // datab as seen by the multiplier input
- wire isigna_int; // signa as seen by the multiplier input
- wire isignb_int; // signb as seen by the multiplier input
-
- wire ia_is_positive;
- wire ib_is_positive;
- wire [17:0] iabsa; // absolute value (i.e. positive) form of dataa input
- wire [17:0] iabsb; // absolute value (i.e. positive) form of datab input
- wire [35:0] iabsresult; // absolute value (i.e. positive) form of product (a * b)
-
- wire dataa_use_reg; // equivalent to dataa_clock parameter
- wire datab_use_reg; // equivalent to datab_clock parameter
- wire signa_use_reg; // equivalent to signa_clock parameter
- wire signb_use_reg; // equivalent to signb_clock parameter
-
- reg [17:0] i_ones; // padding with 1's for input negation
-
- wire reg_aclr;
-
- assign reg_aclr = (!devpor) || (!devclrn) || (aclr);
-
- // optional registering parameters
- assign dataa_use_reg = (dataa_clock != "none") ? 1'b1 : 1'b0;
- assign datab_use_reg = (datab_clock != "none") ? 1'b1 : 1'b0;
- assign signa_use_reg = (signa_clock != "none") ? 1'b1 : 1'b0;
- assign signb_use_reg = (signb_clock != "none") ? 1'b1 : 1'b0;
- assign dataa_pad = ((18-dataa_width) == 0) ? dataa : {{(18-dataa_width){1'b0}},dataa};
- assign datab_pad = ((18-datab_width) == 0) ? datab : {{(18-datab_width){1'b0}},datab};
-
- initial
- begin
- // 1's padding for 18-bit wide inputs
- i_ones = ~0;
- end
-
- // Optional input registers for dataa,b and signa,b
- cycloneiii_mac_data_reg dataa_reg (
- .clk(clk),
- .data(dataa_pad),
- .ena(ena),
- .aclr(reg_aclr),
- .dataout(idataa_reg)
- );
- defparam dataa_reg.data_width = dataa_width;
-
- cycloneiii_mac_data_reg datab_reg (
- .clk(clk),
- .data(datab_pad),
- .ena(ena),
- .aclr(reg_aclr),
- .dataout(idatab_reg)
- );
- defparam datab_reg.data_width = datab_width;
-
- cycloneiii_mac_sign_reg signa_reg (
- .clk(clk),
- .d(signa),
- .ena(ena),
- .aclr(reg_aclr),
- .q(isigna_reg)
- );
-
- cycloneiii_mac_sign_reg signb_reg (
- .clk(clk),
- .d(signb),
- .ena(ena),
- .aclr(reg_aclr),
- .q(isignb_reg)
- );
-
- // mux input sources from direct inputs or optional registers
- assign idataa_int = dataa_use_reg == 1'b1 ? idataa_reg : dataa;
- assign idatab_int = datab_use_reg == 1'b1 ? idatab_reg : datab;
- assign isigna_int = signa_use_reg == 1'b1 ? isigna_reg : signa;
- assign isignb_int = signb_use_reg == 1'b1 ? isignb_reg : signb;
-
- cycloneiii_mac_mult_internal mac_multiply (
- .dataa(idataa_int[dataa_width-1:0]),
- .datab(idatab_int[datab_width-1:0]),
- .signa(isigna_int),
- .signb(isignb_int),
- .dataout(dataout)
- );
- defparam mac_multiply.dataa_width = dataa_width;
- defparam mac_multiply.datab_width = datab_width;
- defparam mac_multiply.dataout_width = dataout_width;
-
-endmodule
-
-module cycloneiii_mac_out
- (
- dataa,
- clk,
- aclr,
- ena,
- dataout,
- devclrn,
- devpor
- );
-
- parameter dataa_width = 1;
- parameter output_clock = "none";
- parameter lpm_hint = "true";
- parameter lpm_type = "cycloneiii_mac_out";
-
-// SIMULATION_ONLY_PARAMETERS_BEGIN
-
- parameter dataout_width = dataa_width;
-
-// SIMULATION_ONLY_PARAMETERS_END
-
- input [dataa_width-1:0] dataa;
- input clk;
- input aclr;
- input ena;
- input devclrn;
- input devpor;
- output [dataout_width-1:0] dataout;
-
- // tri1 devclrn;
- // tri1 devpor;
-
- wire [dataa_width-1:0] dataa_ipd; // internal dataa
- wire clk_ipd; // internal clk
- wire aclr_ipd; // internal aclr
- wire ena_ipd; // internal ena
-
- // internal variable
- wire [dataout_width-1:0] dataout_tmp;
-
- reg [dataa_width-1:0] idataout_reg; // optional register for dataout output
-
- wire use_reg; // equivalent to dataout_clock parameter
-
- wire enable;
- wire no_aclr;
-
- // Input buffers
- buf (clk_ipd, clk);
- buf (aclr_ipd, aclr);
- buf (ena_ipd, ena);
-
- // buf dataa_buf [dataa_width-1:0] (dataa_ipd, dataa);
- assign dataa_ipd = dataa;
-
- // optional registering parameter
- assign use_reg = (output_clock != "none") ? 1 : 0;
- assign enable = (!aclr) && (ena) && use_reg;
- assign no_aclr = (!aclr) && use_reg;
-
- initial
- begin
- // initial values for optional register
- idataout_reg = 0;
- end
-
- // Optional input registers for dataa,b and signa,b
- always @* // (posedge clk_ipd or posedge aclr_ipd or negedge devclrn or negedge devpor)
- begin
- if (devclrn == 0 || devpor == 0 || aclr_ipd == 1)
- begin
- idataout_reg <= 0;
- end
- else if (ena_ipd == 1)
- begin
- idataout_reg <= dataa_ipd;
- end
- end
-
- // mux input sources from direct inputs or optional registers
- assign dataout_tmp = use_reg == 1 ? idataout_reg : dataa_ipd;
-
- // accelerate outputs
- // buf dataout_buf [dataout_width-1:0] (dataout, dataout_tmp);
- assign dataout = dataout_tmp;
-
-endmodule
+++ /dev/null
-
-#define GENERATE_BINARY_OPS
-#define GENERATE_UNARY_OPS
-#define GENERATE_TERNARY_OPS
-#define GENERATE_CONCAT_OPS
-#undef GENERATE_REPEAT_OPS // disabled because of XST bug
-#define GENERATE_EXPRESSIONS
-
-#include <sys/stat.h>
-#include <sys/types.h>
-#include <string.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <string>
-
-const char *arg_types[][3] = {
- { "{dir} [3:0] {name}", "{name}", "4" }, // 00
- { "{dir} [4:0] {name}", "{name}", "5" }, // 01
- { "{dir} [5:0] {name}", "{name}", "6" }, // 02
- { "{dir} signed [3:0] {name}", "{name}", "4" }, // 03
- { "{dir} signed [4:0] {name}", "{name}", "5" }, // 04
- { "{dir} signed [5:0] {name}", "{name}", "6" } // 05
-};
-
-const char *small_arg_types[][3] = {
- { "{dir} [0:0] {name}", "{name}", "1" }, // 00
- { "{dir} [1:0] {name}", "{name}", "2" }, // 01
- { "{dir} [2:0] {name}", "{name}", "3" }, // 02
- { "{dir} signed [0:0] {name}", "{name}", "1" }, // 03
- { "{dir} signed [1:0] {name}", "{name}", "2" }, // 04
- { "{dir} signed [2:0] {name}", "{name}", "3" }, // 05
-};
-
-// See Table 5-1 (page 42) in IEEE Std 1364-2005
-// for a list of all Verilog oprators.
-
-const char *binary_ops[] = {
- "+", // 00
- "-", // 01
- "*", // 02
-// "/",
-// "%",
-// "**",
- ">", // 03
- ">=", // 04
- "<", // 05
- "<=", // 06
- "&&", // 07
- "||", // 08
- "==", // 09
- "!=", // 10
- "===", // 11
- "!==", // 12
- "&", // 13
- "|", // 14
- "^", // 15
- "^~", // 16
- "<<", // 17
- ">>", // 18
- "<<<", // 19
- ">>>", // 20
-};
-
-const char *unary_ops[] = {
- "+", // 00
- "-", // 01
- "!", // 02
- "~", // 03
- "&", // 04
- "~&", // 05
- "|", // 06
- "~|", // 07
- "^", // 08
- "~^", // 09
-};
-
-void strsubst(std::string &str, const std::string &match, const std::string &replace)
-{
- size_t pos;
- while ((pos = str.find(match)) != std::string::npos)
- str.replace(pos, match.size(), replace);
-}
-
-uint32_t xorshift32(uint32_t seed = 0) {
- static uint32_t x = 314159265;
- if (seed)
- x = seed;
- x ^= x << 13;
- x ^= x >> 17;
- x ^= x << 5;
- return x;
-}
-
-void print_expression(FILE *f, int budget, uint32_t mask = 0)
-{
- size_t num_binary_ops = sizeof(binary_ops)/sizeof(*binary_ops);
- size_t num_unary_ops = sizeof(unary_ops)/sizeof(*unary_ops);
- size_t num_arg_types = sizeof(arg_types)/sizeof(*arg_types);
- int i, j, k, mode;
-
- if (budget == 0) {
- fprintf(f, "%c%d", 'a' + char(xorshift32() % 2), int(xorshift32() % num_arg_types));
- return;
- }
-
- int num_modes = 4;
- while ((mask & ~((~0) << num_modes)) == 0)
- mask = xorshift32();
- do {
- mode = xorshift32() % num_modes;
- } while (((1 << mode) & mask) == 0);
- // fprintf(f, "/* %d */", mode);
-
- budget--;
- switch (mode)
- {
- case 0:
- fprintf(f, "(");
- print_expression(f, budget, mask);
- fprintf(f, ")");
- break;
- case 1:
- fprintf(f, "(");
- print_expression(f, budget/2, mask);
- #if 1
- // FIXME: relational operators disabled because there is an xst bug..
- do k = xorshift32() % num_binary_ops; while ((k >= 9 && k <= 12) || (k >= 3 && k <= 6));
- fprintf(f, "%s", binary_ops[k]);
- #else
- fprintf(f, "%s", binary_ops[xorshift32() % num_binary_ops]);
- #endif
- print_expression(f, budget/2, mask);
- fprintf(f, ")");
- break;
- case 2:
- fprintf(f, "(%s", unary_ops[xorshift32() % num_unary_ops]);
- print_expression(f, budget, mask);
- fprintf(f, ")");
- break;
- case 3:
- i = 1 + xorshift32() % 3;
- fprintf(f, "{");
- for (j = 0; j < i; j++) {
- if (j)
- fprintf(f, ",");
- print_expression(f, budget / i, mask);
- }
- fprintf(f, "}");
- break;
-#if 0
- // FIXME: disabled because there is an xst bug..
- case 4:
- i = xorshift32() % 4;
- fprintf(f, "{%d{", i);
- print_expression(f, budget, mask);
- fprintf(f, "}}");
- break;
-#endif
- }
-}
-
-int main()
-{
- mkdir("rtl", 0777);
-
-#ifdef GENERATE_BINARY_OPS
- for (int ai = 0; ai < sizeof(arg_types)/sizeof(arg_types[0]); ai++)
- for (int bi = 0; bi < sizeof(arg_types)/sizeof(arg_types[0]); bi++)
- for (int yi = 0; yi < sizeof(arg_types)/sizeof(arg_types[0]); yi++)
- for (int oi = 0; oi < sizeof(binary_ops)/sizeof(binary_ops[0]); oi++)
- {
- std::string a_decl = arg_types[ai][0];
- strsubst(a_decl, "{dir}", "input");
- strsubst(a_decl, "{name}", "a");
-
- std::string b_decl = arg_types[bi][0];
- strsubst(b_decl, "{dir}", "input");
- strsubst(b_decl, "{name}", "b");
-
- std::string y_decl = arg_types[yi][0];
- strsubst(y_decl, "{dir}", "output");
- strsubst(y_decl, "{name}", "y");
-
- std::string a_ref = arg_types[ai][1];
- strsubst(a_ref, "{dir}", "input");
- strsubst(a_ref, "{name}", "a");
-
- std::string b_ref = arg_types[bi][1];
- strsubst(b_ref, "{dir}", "input");
- strsubst(b_ref, "{name}", "b");
-
- std::string y_ref = arg_types[yi][1];
- strsubst(y_ref, "{dir}", "output");
- strsubst(y_ref, "{name}", "y");
-
- char buffer[1024];
- snprintf(buffer, 1024, "rtl/binary_ops_%02d%02d%02d%02d.v", ai, bi, yi, oi);
-
- FILE *f = fopen(buffer, "w");
- fprintf(f, "module binary_ops_%02d%02d%02d%02d(a, b, y);\n", ai, bi, yi, oi);
- fprintf(f, "%s;\n", a_decl.c_str());
- fprintf(f, "%s;\n", b_decl.c_str());
- fprintf(f, "%s;\n", y_decl.c_str());
- fprintf(f, "assign %s = %s %s %s;\n", y_ref.c_str(),
- a_ref.c_str(), binary_ops[oi], b_ref.c_str());
- fprintf(f, "endmodule\n");
- fclose(f);
- }
-#endif
-
-#ifdef GENERATE_UNARY_OPS
- for (int ai = 0; ai < sizeof(arg_types)/sizeof(arg_types[0]); ai++)
- for (int yi = 0; yi < sizeof(arg_types)/sizeof(arg_types[0]); yi++)
- for (int oi = 0; oi < sizeof(unary_ops)/sizeof(unary_ops[0]); oi++)
- {
- std::string a_decl = arg_types[ai][0];
- strsubst(a_decl, "{dir}", "input");
- strsubst(a_decl, "{name}", "a");
-
- std::string y_decl = arg_types[yi][0];
- strsubst(y_decl, "{dir}", "output");
- strsubst(y_decl, "{name}", "y");
-
- std::string a_ref = arg_types[ai][1];
- strsubst(a_ref, "{dir}", "input");
- strsubst(a_ref, "{name}", "a");
-
- std::string y_ref = arg_types[yi][1];
- strsubst(y_ref, "{dir}", "output");
- strsubst(y_ref, "{name}", "y");
-
- char buffer[1024];
- snprintf(buffer, 1024, "rtl/unary_ops_%02d%02d%02d.v", ai, yi, oi);
-
- FILE *f = fopen(buffer, "w");
- fprintf(f, "module unary_ops_%02d%02d%02d(a, b, y);\n", ai, yi, oi);
- fprintf(f, "%s;\n", a_decl.c_str());
- fprintf(f, "input b;\n");
- fprintf(f, "%s;\n", y_decl.c_str());
- fprintf(f, "assign %s = %s %s;\n", y_ref.c_str(),
- unary_ops[oi], a_ref.c_str());
- fprintf(f, "endmodule\n");
- fclose(f);
- }
-#endif
-
-#ifdef GENERATE_TERNARY_OPS
- for (int ai = 0; ai < sizeof(small_arg_types)/sizeof(small_arg_types[0]); ai++)
- for (int bi = 0; bi < sizeof(arg_types)/sizeof(arg_types[0]); bi++)
- for (int ci = 0; ci < sizeof(arg_types)/sizeof(arg_types[0]); ci++)
- for (int yi = 0; yi < sizeof(arg_types)/sizeof(arg_types[0]); yi++)
- {
- if (!strcmp(small_arg_types[ai][2], "3"))
- continue;
- if (!strcmp(arg_types[bi][2], "6"))
- continue;
- if (!strcmp(arg_types[ci][2], "6"))
- continue;
-
- std::string a_decl = small_arg_types[ai][0];
- strsubst(a_decl, "{dir}", "input");
- strsubst(a_decl, "{name}", "a");
-
- std::string b1_decl = arg_types[bi][0];
- strsubst(b1_decl, "{dir}", "wire");
- strsubst(b1_decl, "{name}", "b1");
-
- std::string b2_decl = arg_types[ci][0];
- strsubst(b2_decl, "{dir}", "wire");
- strsubst(b2_decl, "{name}", "b2");
-
- std::string y_decl = arg_types[yi][0];
- strsubst(y_decl, "{dir}", "output");
- strsubst(y_decl, "{name}", "y");
-
- std::string a_ref = small_arg_types[ai][1];
- strsubst(a_ref, "{dir}", "input");
- strsubst(a_ref, "{name}", "a");
-
- std::string b1_ref = arg_types[bi][1];
- strsubst(b1_ref, "{dir}", "wire");
- strsubst(b1_ref, "{name}", "b1");
-
- std::string b2_ref = arg_types[ci][1];
- strsubst(b2_ref, "{dir}", "wire");
- strsubst(b2_ref, "{name}", "b2");
-
- std::string y_ref = arg_types[yi][1];
- strsubst(y_ref, "{dir}", "output");
- strsubst(y_ref, "{name}", "y");
-
- char buffer[1024];
- snprintf(buffer, 1024, "rtl/ternary_ops_%02d%02d%02d%02d.v", ai, bi, ci, yi);
-
- FILE *f = fopen(buffer, "w");
- fprintf(f, "module ternary_ops_%02d%02d%02d%02d(a, b, y);\n", ai, bi, ci, yi);
- fprintf(f, "%s;\n", a_decl.c_str());
- fprintf(f, "input [%s+%s-1:0] b;\n", arg_types[bi][2], arg_types[ci][2]);
- fprintf(f, "%s = b[%s+%s-1:%s];\n", b1_decl.c_str(), arg_types[bi][2], arg_types[ci][2], arg_types[ci][2]);
- fprintf(f, "%s = b[%s-1:0];\n", b2_decl.c_str(), arg_types[ci][2]);
- fprintf(f, "%s;\n", y_decl.c_str());
- fprintf(f, "assign %s = %s ? %s : %s;\n", y_ref.c_str(),
- a_ref.c_str(), b1_ref.c_str(), b2_ref.c_str());
- fprintf(f, "endmodule\n");
- fclose(f);
- }
-#endif
-
-#ifdef GENERATE_CONCAT_OPS
- for (int ai = 0; ai < sizeof(small_arg_types)/sizeof(small_arg_types[0]); ai++)
- for (int bi = 0; bi < sizeof(small_arg_types)/sizeof(small_arg_types[0]); bi++)
- for (int yi = 0; yi < sizeof(arg_types)/sizeof(arg_types[0]); yi++)
- {
- std::string a_decl = small_arg_types[ai][0];
- strsubst(a_decl, "{dir}", "input");
- strsubst(a_decl, "{name}", "a");
-
- std::string b_decl = small_arg_types[bi][0];
- strsubst(b_decl, "{dir}", "input");
- strsubst(b_decl, "{name}", "b");
-
- std::string y_decl = arg_types[yi][0];
- strsubst(y_decl, "{dir}", "output");
- strsubst(y_decl, "{name}", "y");
-
- std::string a_ref = small_arg_types[ai][1];
- strsubst(a_ref, "{dir}", "input");
- strsubst(a_ref, "{name}", "a");
-
- std::string b_ref = small_arg_types[bi][1];
- strsubst(b_ref, "{dir}", "input");
- strsubst(b_ref, "{name}", "b");
-
- std::string y_ref = arg_types[yi][1];
- strsubst(y_ref, "{dir}", "output");
- strsubst(y_ref, "{name}", "y");
-
- char buffer[1024];
- snprintf(buffer, 1024, "rtl/concat_ops_%02d%02d%02d.v", ai, bi, yi);
-
- FILE *f = fopen(buffer, "w");
- fprintf(f, "module concat_ops_%02d%02d%02d(a, b, y);\n", ai, bi, yi);
- fprintf(f, "%s;\n", a_decl.c_str());
- fprintf(f, "%s;\n", b_decl.c_str());
- fprintf(f, "%s;\n", y_decl.c_str());
- fprintf(f, "assign %s = {%s, %s};\n", y_ref.c_str(), a_ref.c_str(), b_ref.c_str());
- fprintf(f, "endmodule\n");
- fclose(f);
- }
-#endif
-
-#ifdef GENERATE_REPEAT_OPS
- for (int a = 0; a < 4; a++)
- for (int bi = 0; bi < sizeof(small_arg_types)/sizeof(small_arg_types[0]); bi++)
- for (int yi = 0; yi < sizeof(arg_types)/sizeof(arg_types[0]); yi++)
- {
- std::string b_decl = small_arg_types[bi][0];
- strsubst(b_decl, "{dir}", "input");
- strsubst(b_decl, "{name}", "b");
-
- std::string y_decl = arg_types[yi][0];
- strsubst(y_decl, "{dir}", "output");
- strsubst(y_decl, "{name}", "y");
-
- std::string b_ref = small_arg_types[bi][1];
- strsubst(b_ref, "{dir}", "input");
- strsubst(b_ref, "{name}", "b");
-
- std::string y_ref = arg_types[yi][1];
- strsubst(y_ref, "{dir}", "output");
- strsubst(y_ref, "{name}", "y");
-
- char buffer[1024];
- snprintf(buffer, 1024, "rtl/repeat_ops_%02d%02d%02d.v", a, bi, yi);
-
- FILE *f = fopen(buffer, "w");
- fprintf(f, "module repeat_ops_%02d%02d%02d(a, b, y);\n", a, bi, yi);
- fprintf(f, "input a;\n");
- fprintf(f, "%s;\n", b_decl.c_str());
- fprintf(f, "%s;\n", y_decl.c_str());
- fprintf(f, "assign %s = {%d{%s}};\n", y_ref.c_str(), a, b_ref.c_str());
- fprintf(f, "endmodule\n");
- fclose(f);
- }
-#endif
-
-#ifdef GENERATE_EXPRESSIONS
- for (int i = 0; i < 1000; i++)
- {
- xorshift32(1234 + i);
- xorshift32();
- xorshift32();
- xorshift32();
-
- char buffer[1024];
- snprintf(buffer, 1024, "rtl/expression_%05d.v", i);
-
- FILE *f = fopen(buffer, "w");
- fprintf(f, "module expression_%05d(a, b, y);\n", i);
-
- for (char var = 'a'; var <= 'y'; var++)
- {
- fprintf(f, "%s [", var != 'y' ? "input" : "output");
- for (int j = 0; j < sizeof(arg_types)/sizeof(arg_types[0]); j++)
- fprintf(f, "%s%s", j ? "+" : "", arg_types[j][2]);
- fprintf(f, "-1:0] %c;\n", var);
-
- for (int j = 0; j < sizeof(arg_types)/sizeof(arg_types[0]); j++)
- {
- std::string decl = arg_types[j][0];
- strsubst(decl, "{dir}", "wire");
- snprintf(buffer, 1024, "%c%d", var, j);
- strsubst(decl, "{name}", buffer);
-
- if (var != 'y') {
- fprintf(f, "%s = %c[", decl.c_str(), var);
- for (int k = 0; k <= j; k++)
- fprintf(f, "%s%s", k ? "+" : "", arg_types[k][2]);
- fprintf(f, "-1:");
- for (int k = 0; k < j; k++)
- fprintf(f, "%s%s", k ? "+" : "", arg_types[k][2]);
- fprintf(f, "%s];\n", j ? "" : "0");
- } else
- fprintf(f, "%s;\n", decl.c_str());
- }
-
- if (var == 'b')
- var = 'x';
- }
-
- fprintf(f, "assign y = {");
- for (int j = 0; j < sizeof(arg_types)/sizeof(arg_types[0]); j++)
- fprintf(f, "%sy%d", j ? "," : "", j);
- fprintf(f, "};\n");
-
- for (int j = 0; j < sizeof(arg_types)/sizeof(arg_types[0]); j++) {
- fprintf(f, "assign y%d = ", j);
- print_expression(f, 1 + xorshift32() % 20);
- fprintf(f, ";\n");
- }
-
- fprintf(f, "endmodule\n");
- fclose(f);
- }
-#endif
-
- return 0;
-}
-
+++ /dev/null
-#!/bin/bash
-
-if [ $# -eq 0 ]; then
- echo "Usage: $0 <job_id>" >&2
- exit 1
-fi
-
-job="$1"
-set --
-
-set -ex
-rm -rf report_temp/$job
-mkdir -p report report_temp/$job
-cd report_temp/$job
-
-cp ../../vivado/$job.v syn_vivado.v
-cp ../../quartus/$job.v syn_quartus.v
-cp ../../xst/$job.v syn_xst.v
-cp ../../rtl/$job.v rtl.v
-
-yosys -p 'hierarchy; proc; opt; techmap; abc; opt' -b 'verilog -noattr' -o syn_yosys.v ../../rtl/$job.v
-cat ../../xl_cells.v ../../cy_cells.v > cells.v
-
-{
- echo "module ${job}_test(a, b, y1, y2);"
- sed -r '/^(input|output) / !d; /output/ { s/ y;/ y1;/; p; }; s/ y1;/ y2;/;' rtl.v
- echo "${job}_1 uut1 (.a(a), .b(b), .y(y1));"
- echo "${job}_2 uut2 (.a(a), .b(b), .y(y2));"
- echo "endmodule"
-} > test.v
-
-echo -n > fail_patterns.txt
-for p in syn_vivado syn_quartus syn_xst syn_yosys rtl; do
-for q in syn_vivado syn_quartus syn_xst syn_yosys rtl; do
- if test -f result.${q}.${p}.txt; then
- cp result.${q}.${p}.txt result.${p}.${q}.txt
- continue
- fi
-
- {
- echo "read_verilog -DGLBL $p.v"
- echo "rename $job ${job}_1"
-
- echo "read_verilog -DGLBL $q.v"
- echo "rename $job ${job}_2"
-
- echo "read_verilog cells.v test.v"
- echo "hierarchy -top ${job}_test"
- echo "proc; opt; flatten ${job}_test"
- echo "hierarchy -check -top ${job}_test"
-
- echo "! touch test.$p.$q.input_ok"
- echo "sat -timeout 10 -verify-no-timeout -show a,b,y1,y2 -prove y1 y2 ${job}_test"
- } > test.$p.$q.ys
-
- if yosys -l test.$p.$q.log test.$p.$q.ys; then
- if grep TIMEOUT test.$p.$q.log; then
- echo TIMEOUT > result.${p}.${q}.txt
- else
- echo PASS > result.${p}.${q}.txt
- fi
- else
- echo $( grep '^ *\\[ab] ' test.$p.$q.log | gawk '{ print $4; }' | tr -d '\n' ) >> fail_patterns.txt
- echo FAIL > result.${p}.${q}.txt
- fi
-
- # this fails if an error was encountered before the 'sat' command
- rm test.$p.$q.input_ok
-done; done
-
-{
- echo "module testbench;"
-
- sed -r '/^input / !d; s/^input/reg/;' rtl.v
- for p in syn_vivado syn_quartus syn_xst syn_yosys rtl; do
- sed -r "/^output / !d; s/^output/wire/; s/ y;/ ${p}_y;/;" rtl.v
- echo "${job}_${p} uut_${p} (.a(a), .b(b), .y(${p}_y));"
- done
-
- echo "initial begin"
- extra_patterns=""
- bits=$( echo $( grep '^input' rtl.v | cut -f2 -d'[' | cut -f1 -d: | tr '\n' '+' )2 | bc; )
- for x in 1 2 3 4 5 6 7 8 9 0; do
- extra_patterns="$extra_patterns $( echo $job$x | sha1sum | gawk "{ print \"160'h\" \$1; }" )"
- done
- for pattern in $bits\'b0 ~$bits\'b0 $( sed "s/^/$bits'b/;" < fail_patterns.txt ) $extra_patterns; do
- echo " { a, b } <= $pattern; #1;"
- for p in syn_vivado syn_quartus syn_xst syn_yosys rtl; do
- echo " \$display(\"++RPT++ %b $p\", ${p}_y);"
- done
- echo " \$display(\"++RPT++ ----\");"
- done
- echo "end"
-
- echo "endmodule"
-
- for p in syn_vivado syn_quartus syn_xst syn_yosys rtl; do
- sed "s/^module ${job}/module ${job}_${p}/; /^\`timescale/ d;" < $p.v
- done
-
- cat cells.v
-} > testbench.v
-
-/opt/altera/13.0/modelsim_ase/bin/vlib work
-/opt/altera/13.0/modelsim_ase/bin/vlog testbench.v
-/opt/altera/13.0/modelsim_ase/bin/vsim -c -do "run; exit" work.testbench | tee sim_modelsim.log
-
-. /opt/Xilinx/14.5/ISE_DS/settings64.sh
-vlogcomp testbench.v
-fuse -o testbench testbench
-{ echo "run all"; echo "exit"; } > run-all.tcl
-./testbench -tclbatch run-all.tcl | tee sim_isim.log
-
-for p in syn_vivado syn_quartus syn_xst syn_yosys rtl; do
-for q in isim modelsim; do
- echo $( grep '++RPT++' sim_$q.log | sed 's,.*++RPT++ ,,' | grep " $p\$" | gawk '{ print $1; }' | md5sum | gawk '{ print $1; }' ) > result.${p}.${q}.txt
-done; done
-
-echo "#00ff00" > color_PASS.txt
-echo "#ff0000" > color_FAIL.txt
-
-if cmp result.rtl.isim.txt result.rtl.modelsim.txt; then
- echo "#00ff00" > color_$( cat result.rtl.isim.txt ).txt
-else
- echo "#00ff00" > color_NO_SIM_COMMON.txt
-fi
-
-{
- echo "<h3>Hammer Report: $job</h3>"
- echo "<table border>"
- echo "<tr><th width=\"100\"></th>"
- for q in syn_vivado syn_quartus syn_xst syn_yosys rtl isim modelsim; do
- echo "<th width=\"100\">$q</th>"
- done
- echo "</tr>"
- for p in syn_vivado syn_quartus syn_xst syn_yosys rtl; do
- echo "<tr><th>$p</th>"
- for q in syn_vivado syn_quartus syn_xst syn_yosys rtl isim modelsim; do
- read result < result.${p}.${q}.txt
- if ! test -f color_$result.txt; then
- case $( ls color_*.txt | wc -l ) in
- 3) echo "#ffff00" > color_$result.txt ;;
- 4) echo "#ff00ff" > color_$result.txt ;;
- 5) echo "#00ffff" > color_$result.txt ;;
- *) echo "#888888" > color_$result.txt ;;
- esac
- fi
- echo "<td align=\"center\" bgcolor=\"$( cat color_$result.txt )\">$( echo $result | cut -c1-8 )</td>"
- done
- echo "</tr>"
- done
- echo "<tr><td colspan=\"8\"><pre>$( perl -pe 's/([<>&])/"&#".ord($1).";"/eg;' rtl.v |
- perl -pe 's!([^\w#]|^)(\w+)\b!$x = $1; $y = $2; sprintf("%s<span style=\"color: %s;\">%s</span>", $x, $y =~ /module|input|wire|output|assign|signed|endmodule/ ? "#008800;" : "#000088;", $y)!eg' )</pre></td></tr>"
- #perl -pe 's,\b(module|input|wire|output|assign|signed|endmodule)\b,<span style="color: #008800;">$1</span>,g' )</pre></td></tr>"
- echo "</table>"
-} > ../../report/$job.html
-
-sync
-echo READY.
-
+++ /dev/null
-#!/bin/bash
-
-use_vivado=false
-use_quartus=false
-checkdir="check"
-
-if [ "$1" = "-vivado" ]; then
- use_vivado=true
- checkdir="check_vivado"
- shift
-fi
-
-if [ "$1" = "-quartus" ]; then
- use_quartus=true
- checkdir="check_quartus"
- shift
-fi
-
-if [ $# -eq 0 ]; then
- echo "Usage: $0 <job_id>" >&2
- exit 1
-fi
-
-job="$1"
-set --
-
-set -e
-mkdir -p $checkdir check_temp/$job
-cd check_temp/$job
-
-{
- echo "module ${job}_top(a, b, y_rtl, y_syn);"
- sed -r '/^(input|output) / !d; /output/ { s/ y;/ y_rtl;/; p; }; s/ y_rtl;/ y_syn;/;' ../../rtl/$job.v
- echo "${job}_rtl rtl_variant (.a(a), .b(b), .y(y_rtl));"
- echo "${job}_syn syn_variant (.a(a), .b(b), .y(y_syn));"
- echo "endmodule"
-} > ${job}_top.v
-
-for mode in nomap techmap; do
- {
- if $use_quartus; then
- echo "read_verilog ../../quartus/$job.v"
- elif $use_vivado; then
- echo "read_verilog ../../vivado/$job.v"
- else
- echo "read_verilog -DGLBL ../../xst/$job.v"
- fi
- echo "rename $job ${job}_syn"
-
- echo "read_verilog ../../rtl/$job.v"
- echo "rename $job ${job}_rtl"
- if [ $mode = techmap ]; then
- echo "techmap ${job}_rtl"
- fi
-
- echo "read_verilog ${job}_top.v"
- if $use_quartus; then
- echo "read_verilog ../../cy_cells.v"
- else
- echo "read_verilog ../../xl_cells.v"
- fi
-
- echo "hierarchy -top ${job}_top"
- echo "proc"
-
- echo "flatten ${job}_syn"
- echo "flatten ${job}_rtl"
- echo "flatten ${job}_top"
- echo "opt_clean"
-
- echo "rename ${job}_syn ${job}_syn_${mode}"
- echo "rename ${job}_rtl ${job}_rtl_${mode}"
- echo "rename ${job}_top ${job}_top_${mode}"
- echo "dump -outfile ${job}_top_${mode}.il ${job}_syn_${mode} ${job}_rtl_${mode} ${job}_top_${mode}"
- } > ${job}_top_${mode}.ys
- ../../../../yosys -q ${job}_top_${mode}.ys
-done
-
-{
- echo "read_ilang ${job}_top_nomap.il"
- echo "read_ilang ${job}_top_techmap.il"
- echo "sat -timeout 60 -verify-no-timeout -show a,b,y_rtl,y_syn -prove y_rtl y_syn ${job}_top_nomap"
- echo "sat -timeout 60 -verify-no-timeout -show a,b,y_rtl,y_syn -prove y_rtl y_syn ${job}_top_techmap"
- if [[ $job != expression_* ]] && ! $use_quartus && ! $use_vivado; then
- echo "eval -brute_force_equiv_checker ${job}_rtl_nomap ${job}_syn_nomap"
- echo "eval -brute_force_equiv_checker ${job}_rtl_techmap ${job}_syn_techmap"
- fi
-} > ${job}_cmp.ys
-
-if ../../../../yosys -l ${job}.log ${job}_cmp.ys; then
- mv ${job}.log ../../$checkdir/${job}.log
- rm -f ../../$checkdir/${job}.err
- touch ../../$checkdir/${job}.log
-else
- mv ${job}.log ../../$checkdir/${job}.err
- rm -f ../../$checkdir/${job}.log
-fi
-
-exit 0
-
+++ /dev/null
-#!/bin/bash
-
-if [ $# -eq 0 ]; then
- echo "Usage: $0 <job_id>" >&2
- exit 1
-fi
-
-job="$1"
-set --
-
-set -e
-mkdir -p quartus quartus_temp/$job
-cd quartus_temp/$job
-
-rm -rf *
-cp ../../rtl/$job.v .
-/opt/altera/13.0/quartus/bin/quartus_map $job --source=$job.v --family="Cyclone III"
-/opt/altera/13.0/quartus/bin/quartus_fit $job
-/opt/altera/13.0/quartus/bin/quartus_eda $job --formal_verification --tool=conformal
-cp -v fv/conformal/$job.vo ../../quartus/$job.v
-
-sync
-exit 0
-
+++ /dev/null
-#!/bin/bash
-
-if [ $# -eq 0 ]; then
- echo "Usage: $0 <job_id>" >&2
- exit 1
-fi
-
-job="$1"
-set --
-
-set -e
-mkdir -p vivado vivado_temp/$job
-cd vivado_temp/$job
-
-sed 's/^module/(* use_dsp48="no" *) module/;' < ../../rtl/$job.v > rtl.v
-cat > $job.tcl <<- EOT
- read_verilog rtl.v
- synth_design -part xc7k70t -top $job
- write_verilog -force ../../vivado/$job.v
-EOT
-
-/opt/Xilinx/Vivado/2013.2/bin/vivado -mode batch -source $job.tcl
-
-sync
-exit 0
-
+++ /dev/null
-#!/bin/bash
-
-if [ $# -eq 0 ]; then
- echo "Usage: $0 <job_id>" >&2
- exit 1
-fi
-
-job="$1"
-set --
-
-set -e
-mkdir -p xst xst_temp/$job
-cd xst_temp/$job
-
-cat > $job.xst <<- EOT
- run
- -ifn $job.prj -ofn $job -p artix7 -top $job
- -iobuf NO -ram_extract NO -rom_extract NO -use_dsp48 NO
- -fsm_extract YES -fsm_encoding Auto
-EOT
-
-cat > $job.prj <<- EOT
- verilog work "../../rtl/$job.v"
-EOT
-
-. /opt/Xilinx/14.5/ISE_DS/settings64.sh
-
-xst -ifn $job.xst
-netgen -w -ofmt verilog $job.ngc $job
-cp $job.v ../../xst/$job.v
-
-sync
-exit 0
-
+++ /dev/null
-
-module IBUF(O, I);
-output O;
-input I;
-assign O = I;
-endmodule
-
-module OBUF(O, I);
-output O;
-input I;
-assign O = I;
-endmodule
-
-module GND(G);
-output G;
-assign G = 0;
-endmodule
-
-module INV(O, I);
-input I;
-output O;
-assign O = !I;
-endmodule
-
-module LUT1(O, I0);
-parameter INIT = 0;
-input I0;
-wire [1:0] lutdata = INIT;
-wire [0:0] idx = { I0 };
-output O;
-assign O = lutdata[idx];
-endmodule
-
-module LUT2(O, I0, I1);
-parameter INIT = 0;
-input I0, I1;
-wire [3:0] lutdata = INIT;
-wire [1:0] idx = { I1, I0 };
-output O;
-assign O = lutdata[idx];
-endmodule
-
-module LUT3(O, I0, I1, I2);
-parameter INIT = 0;
-input I0, I1, I2;
-wire [7:0] lutdata = INIT;
-wire [2:0] idx = { I2, I1, I0 };
-output O;
-assign O = lutdata[idx];
-endmodule
-
-module LUT4(O, I0, I1, I2, I3);
-parameter INIT = 0;
-input I0, I1, I2, I3;
-wire [15:0] lutdata = INIT;
-wire [3:0] idx = { I3, I2, I1, I0 };
-output O;
-assign O = lutdata[idx];
-endmodule
-
-module LUT5(O, I0, I1, I2, I3, I4);
-parameter INIT = 0;
-input I0, I1, I2, I3, I4;
-wire [31:0] lutdata = INIT;
-wire [4:0] idx = { I4, I3, I2, I1, I0 };
-output O;
-assign O = lutdata[idx];
-endmodule
-
-module LUT6(O, I0, I1, I2, I3, I4, I5);
-parameter INIT = 0;
-input I0, I1, I2, I3, I4, I5;
-wire [63:0] lutdata = INIT;
-wire [5:0] idx = { I5, I4, I3, I2, I1, I0 };
-output O;
-assign O = lutdata[idx];
-endmodule
-
-module MUXCY(O, CI, DI, S);
-input CI, DI, S;
-output O;
-assign O = S ? CI : DI;
-endmodule
-
-module MUXF7(O, I0, I1, S);
-input I0, I1, S;
-output O;
-assign O = S ? I1 : I0;
-endmodule
-
-module MUXF8(O, I0, I1, S);
-input I0, I1, S;
-output O;
-assign O = S ? I1 : I0;
-endmodule
-
-module VCC(P);
-output P;
-assign P = 1;
-endmodule
-
-module XORCY(O, CI, LI);
-input CI, LI;
-output O;
-assign O = CI ^ LI;
-endmodule
-
-module CARRY4(CO, O, CI, CYINIT, DI, S);
-output [3:0] CO, O;
-input CI, CYINIT;
-input [3:0] DI, S;
-wire ci_or_cyinit;
-assign O = S ^ {CO[2:0], ci_or_cyinit};
-assign CO[0] = S[0] ? ci_or_cyinit : DI[0];
-assign CO[1] = S[1] ? CO[0] : DI[1];
-assign CO[2] = S[2] ? CO[1] : DI[2];
-assign CO[3] = S[3] ? CO[2] : DI[3];
-assign ci_or_cyinit = CI | CYINIT;
-endmodule
-
+++ /dev/null
-
-module TB_GND(ok);
-wire MY_G, XL_G;
-MY_GND MY(.G(MY_G));
-XL_GND XL(.G(XL_G));
-output ok = MY_G == XL_G;
-endmodule
-
-module TB_INV(ok, I);
-input I;
-wire MY_O, XL_O;
-MY_INV MY(.O(MY_O), .I(I));
-XL_INV XL(.O(XL_O), .I(I));
-output ok = MY_O == XL_O;
-endmodule
-
-module TB_LUT1(ok, I0);
-input I0;
-wire [1:0] MY_O, XL_O;
-genvar i;
-generate for (i=0; i<2; i=i+1) begin:V
- MY_LUT1 #(.INIT(i)) MY(.O(MY_O[i]), .I0(I0));
- XL_LUT1 #(.INIT(i)) XL(.O(XL_O[i]), .I0(I0));
-end endgenerate
-output ok = MY_O == XL_O;
-endmodule
-
-module TB_LUT2(ok, I0, I1);
-input I0, I1;
-wire [3:0] MY_O, XL_O;
-genvar i;
-generate for (i=0; i<4; i=i+1) begin:V
- MY_LUT2 #(.INIT(i)) MY(.O(MY_O[i]), .I0(I0), .I1(I1));
- XL_LUT2 #(.INIT(i)) XL(.O(XL_O[i]), .I0(I0), .I1(I1));
-end endgenerate
-output ok = MY_O == XL_O;
-endmodule
-
-module TB_LUT3(ok, I0, I1, I2);
-input I0, I1, I2;
-wire [7:0] MY_O, XL_O;
-genvar i;
-generate for (i=0; i<8; i=i+1) begin:V
- MY_LUT3 #(.INIT(i)) MY(.O(MY_O[i]), .I0(I0), .I1(I1), .I2(I2));
- XL_LUT3 #(.INIT(i)) XL(.O(XL_O[i]), .I0(I0), .I1(I1), .I2(I2));
-end endgenerate
-output ok = MY_O == XL_O;
-endmodule
-
-module TB_LUT4(ok, I0, I1, I2, I3);
-input I0, I1, I2, I3;
-wire [15:0] MY_O, XL_O;
-genvar i;
-generate for (i=0; i<16; i=i+1) begin:V
- MY_LUT4 #(.INIT(i)) MY(.O(MY_O[i]), .I0(I0), .I1(I1), .I2(I2), .I3(I3));
- XL_LUT4 #(.INIT(i)) XL(.O(XL_O[i]), .I0(I0), .I1(I1), .I2(I2), .I3(I3));
-end endgenerate
-output ok = MY_O == XL_O;
-endmodule
-
-module TB_LUT5(ok, I0, I1, I2, I3, I4);
-input I0, I1, I2, I3, I4;
-wire [31:0] MY_O, XL_O;
-genvar i;
-generate for (i=0; i<32; i=i+1) begin:V
- MY_LUT5 #(.INIT(i)) MY(.O(MY_O[i]), .I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4));
- XL_LUT5 #(.INIT(i)) XL(.O(XL_O[i]), .I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4));
-end endgenerate
-output ok = MY_O == XL_O;
-endmodule
-
-module TB_LUT6(ok, I0, I1, I2, I3, I4, I5);
-input I0, I1, I2, I3, I4, I5;
-wire [63:0] MY_O, XL_O;
-genvar i;
-generate for (i=0; i<64; i=i+1) begin:V
- MY_LUT6 #(.INIT(i)) MY(.O(MY_O[i]), .I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4), .I5(I5));
- XL_LUT6 #(.INIT(i)) XL(.O(XL_O[i]), .I0(I0), .I1(I1), .I2(I2), .I3(I3), .I4(I4), .I5(I5));
-end endgenerate
-output ok = MY_O == XL_O;
-endmodule
-
-module TB_MUXCY(ok, CI, DI, S);
-input CI, DI, S;
-wire MY_O, XL_O;
-MY_MUXCY MY(.O(MY_O), .CI(CI), .DI(DI), .S(S));
-XL_MUXCY XL(.O(XL_O), .CI(CI), .DI(DI), .S(S));
-output ok = MY_O == XL_O;
-endmodule
-
-module TB_MUXF7(ok, I0, I1, S);
-input I0, I1, S;
-wire MY_O, XL_O;
-MY_MUXF7 MY(.O(MY_O), .I0(I0), .I1(I1), .S(S));
-XL_MUXF7 XL(.O(XL_O), .I0(I0), .I1(I1), .S(S));
-output ok = MY_O == XL_O;
-endmodule
-
-module TB_VCC(ok);
-wire MY_P, XL_P;
-MY_VCC MY(.P(MY_P));
-XL_VCC XL(.P(XL_P));
-output ok = MY_P == XL_P;
-endmodule
-
-module TB_XORCY(ok, CI, LI);
-input CI, LI;
-wire MY_O, XL_O;
-MY_XORCY MY(.O(MY_O), .CI(CI), .LI(LI));
-XL_XORCY XL(.O(XL_O), .CI(CI), .LI(LI));
-output ok = MY_O == XL_O;
-endmodule
-
+++ /dev/null
-
-# Verify xilinx cell models
-
-read_verilog xl_cells.v
-read_verilog xl_cells_tb.v
-
-rename GND MY_GND
-rename INV MY_INV
-rename LUT1 MY_LUT1
-rename LUT2 MY_LUT2
-rename LUT3 MY_LUT3
-rename LUT4 MY_LUT4
-rename LUT5 MY_LUT5
-rename LUT6 MY_LUT6
-rename MUXCY MY_MUXCY
-rename MUXF7 MY_MUXF7
-rename VCC MY_VCC
-rename XORCY MY_XORCY
-
-read_verilog /opt/Xilinx/14.5/ISE_DS/ISE/verilog/src/unisims/GND.v
-read_verilog /opt/Xilinx/14.5/ISE_DS/ISE/verilog/src/unisims/INV.v
-read_verilog /opt/Xilinx/14.5/ISE_DS/ISE/verilog/src/unisims/LUT1.v
-read_verilog /opt/Xilinx/14.5/ISE_DS/ISE/verilog/src/unisims/LUT2.v
-read_verilog /opt/Xilinx/14.5/ISE_DS/ISE/verilog/src/unisims/LUT3.v
-read_verilog /opt/Xilinx/14.5/ISE_DS/ISE/verilog/src/unisims/LUT4.v
-read_verilog /opt/Xilinx/14.5/ISE_DS/ISE/verilog/src/unisims/LUT5.v
-read_verilog /opt/Xilinx/14.5/ISE_DS/ISE/verilog/src/unisims/LUT6.v
-read_verilog /opt/Xilinx/14.5/ISE_DS/ISE/verilog/src/unisims/MUXCY.v
-read_verilog /opt/Xilinx/14.5/ISE_DS/ISE/verilog/src/unisims/MUXF7.v
-read_verilog /opt/Xilinx/14.5/ISE_DS/ISE/verilog/src/unisims/VCC.v
-read_verilog /opt/Xilinx/14.5/ISE_DS/ISE/verilog/src/unisims/XORCY.v
-
-rename GND XL_GND
-rename INV XL_INV
-rename LUT1 XL_LUT1
-rename LUT2 XL_LUT2
-rename LUT3 XL_LUT3
-rename LUT4 XL_LUT4
-rename LUT5 XL_LUT5
-rename LUT6 XL_LUT6
-rename MUXCY XL_MUXCY
-rename MUXF7 XL_MUXF7
-rename VCC XL_VCC
-rename XORCY XL_XORCY
-
-hierarchy
-proc
-flatten TB_*
-opt_clean
-
-sat -verify -prove ok 1'b1 TB_GND
-sat -verify -prove ok 1'b1 TB_INV
-sat -verify -prove ok 1'b1 TB_LUT1
-sat -verify -prove ok 1'b1 TB_LUT2
-sat -verify -prove ok 1'b1 TB_LUT3
-sat -verify -prove ok 1'b1 TB_LUT4
-sat -verify -prove ok 1'b1 TB_LUT5
-sat -verify -prove ok 1'b1 TB_LUT6
-sat -verify -prove ok 1'b1 TB_MUXCY
-sat -verify -prove ok 1'b1 TB_MUXF7
-sat -verify -prove ok 1'b1 TB_VCC
-sat -verify -prove ok 1'b1 TB_XORCY
-
projects / yosys.git / commitdiff