Re: [libre-riscv-dev] additional ddr3 interfaces
authorStaf Verhaegen <staf@fibraservi.eu>
Wed, 1 Apr 2020 15:19:12 +0000 (17:19 +0200)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Wed, 1 Apr 2020 15:19:19 +0000 (16:19 +0100)
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+From: Staf Verhaegen <staf@fibraservi.eu>
+To: libre-riscv-dev@lists.libre-riscv.org
+Date: Wed, 01 Apr 2020 17:19:12 +0200
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+Subject: Re: [libre-riscv-dev] additional ddr3 interfaces
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+Luke Kenneth Casson Leighton schreef op wo 01-04-2020 om 11:10 [+0000]:
+> On Wed, Apr 1, 2020 at 1:44 AM Jacob Lifshay <programmerjake@gmail.com> w=
+rote:
+> > that would be nice, however the t2080 appears to have a 64-bit memoryin=
+terface along with some really high-speed serdes -- both of which will bemo=
+re difficult to achieve.
+> > However, if we get the funding required for the open-source custom DDR3=
+interface, we could potentially put two copies on our SoC,
+>=20
+> each DDR3/4 RAM interface adds around 0.4 watts per 800mhz clock ratewhic=
+h, due to power being a square law, ramps up 1.6 watts by 1600mhz.
+
+Power consumption is linear with frequency and square with voltage (P =3D f=
+ * C * V^2).
+For overclocking increasing frequency also likely means you need to increas=
+e voltage so you need to increase power consumption more than linear with f=
+requency.
+
+greets,
+Staf.
+
+
+
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