opcodes/arc: Fix incorrect insn_class for some nps insns

A small number of NPS400 instruction incorrectly used NONE as an
insn_class_t, which would trigger a build warning.  Fixed by changing to
MISC.

opcodes/ChangeLog:

	* arc-nps400-tbl.h: Change incorrect use of NONE to MISC.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 7107ee69a0d5bbc4b42b6d6254aeb5fb49b79112..70f146f418ee966943bcca2d0b4117f851cd7148 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2017-11-07  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+       * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
+
 2017-11-07  Alan Modra  <amodra@gmail.com>
 
        * opintl.h: Formatting, comment fixes.

diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h
index a40ee75a435a02e0a81a0227d0034e4d6e211bb0..15ef692f0a1fcd56f7d8d97f6fec860750b36202 100644 (file)
--- a/opcodes/arc-nps400-tbl.h
+++ b/opcodes/arc-nps400-tbl.h
@@ -980,13 +980,13 @@ ASRI_LIKE (0x4, C_NPS_GIC)
 /* Atomic Operations.  */
 
 /* exc<.di><.f> a,a,[xa:b] */
-{ "exc", 0x48060c21, 0xf80fbfff, ARC_OPCODE_ARC700, NONE, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_XA, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }},
+{ "exc", 0x48060c21, 0xf80fbfff, ARC_OPCODE_ARC700, MISC, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_XA, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }},
 
 /* exc<.di><.f> a,a,[sd:b] */
-{ "exc", 0x48060c61, 0xf80fbfff, ARC_OPCODE_ARC700, NONE, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_SD, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }},
+{ "exc", 0x48060c61, 0xf80fbfff, ARC_OPCODE_ARC700, MISC, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_SD, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }},
 
 /* exc<.di><.f> a,a,[xd:b] */
-{ "exc", 0x48060c81, 0xf80fbfff, ARC_OPCODE_ARC700, NONE, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_XD, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }},
+{ "exc", 0x48060c81, 0xf80fbfff, ARC_OPCODE_ARC700, MISC, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_XD, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }},
 
 /* exc<.di><.f> a,a,[b] */
-{ "exc", 0x48060c01, 0xf80fbfff, ARC_OPCODE_ARC700, NONE, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }},
+{ "exc", 0x48060c01, 0xf80fbfff, ARC_OPCODE_ARC700, MISC, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }},