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diff --git a/simple_v_extension/sv_prefix_proposal.rst b/simple_v_extension/sv_prefix_proposal.rst
index e043f96ac9697c8667addc20ed2219b0f388ecc6..10de0d43d362346a709433f63263f955076696aa 100644 (file)
--- a/simple_v_extension/sv_prefix_proposal.rst
+++ b/simple_v_extension/sv_prefix_proposal.rst
@@ -506,20 +506,9 @@ SetVL
 
 setvl rd, rs1, imm
 
-imm is the amount of space allocated from the register file by the compiler.
+This is done the same as Standard SV.
+There is alsO a MVL CSR.  CSRRW and CSRRWI operate in the same way as in SV. See Specification_.
 
-Pseudocode:
-
-1. Trap if imm > XLEN.
-2. If rs1 is x0, then
-    1. Set VL to imm.
-3. Else If regs[rs1] > 2 * imm, then
-    1. Set VL to XLEN.
-4. Else If regs[rs1] > imm, then
-    1. Set VL to regs[rs1] / 2 rounded down.
-5. Otherwise,
-    1. Set VL to regs[rs1].
-6. Set regs[rd] to VL.
 
 Additional Instructions
 =======================
@@ -564,3 +553,11 @@ Is MV.X good enough a substitute for swizzle?
 --
 
 Is vectorised srcbase ok as a gather scatter and ok substitute for register stride? 5 dependency registers (reg stride being the 5th) is quite scary
+
+--
+
+Why are integer conversion instructions needed, when the main SV spec covers them by allowing elwidth to be set on both src and dest regs?
+
+--
+
+Why are the SETVL rules so complex? What is the reason, how are loops carried out?