* simops.c (OP_F0FD): Initialise variable 'sp' for rti instruction.

diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog
index 700ca36f0f1963b1d86bc72934ae428dc09f2259..7e703369470e04a70f280f19fc3060347b9bcf98 100644 (file)
--- a/sim/mn10300/ChangeLog
+++ b/sim/mn10300/ChangeLog
@@ -1,3 +1,7 @@
+Wed Mar 25 12:08:00 1998  Joyce Janczyn  <janczyn@cygnus.com>
+
+       * simops.c (OP_F0FD): Initialise variable 'sp'.
+
 Thu Mar 26 00:21:32 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 
        * dv-mn103int.c (decode_group): A group register every 4 bytes not

diff --git a/sim/mn10300/simops.c b/sim/mn10300/simops.c
index c6b1448bb0300c15da7c1d15ae7aef0981df75ed..aaf7f488adb3d0945fe2ad248ff699d2efe37468 100644 (file)
--- a/sim/mn10300/simops.c
+++ b/sim/mn10300/simops.c
@@ -2846,6 +2846,7 @@ void OP_F0FD (insn, extension)
 {
   unsigned int sp, next_pc;
 
+  sp = State.regs[REG_SP];
   PSW = State.mem[sp] | (State.mem[sp + 1] << 8);
   State.regs[REG_PC] = (State.mem[sp+4] | (State.mem[sp+5] << 8)
              | (State.mem[sp+6] << 16) | (State.mem[sp+7] << 24));