revert 4-operand versions of dsld/dsrd

diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn
index b23fea1e08d227e741c62a08d4e01b1ceddcf5e3..7836743685607a8039f62e4783de33e9e908d1d4 100644 (file)
--- a/openpower/sv/biginteger.mdwn
+++ b/openpower/sv/biginteger.mdwn
@@ -53,15 +53,18 @@ operations.
 
 **DRAFT**
 
-`dsld` and `dsrd` are similar to v3.0 `sld`, and are VA2-Form
+`dsld` and `dsrd` are similar to v3.0 `sld`, and
+is Z23-Form in "overwrite" on RT.
 
-|0.....5|6..10|11..15|16..20|21..25|26..30|31|
-|-------|-----|------|------|------|------|--|
-| EXT04 | RT  |  RA  |  RB  |   RC |  XO  |Rc|
+|0.....5|6..10|11..15|16..20|21.22|23..30|31|
+|-------|-----|------|------|-----|------|--|
+| EXT04 | RT  |  RA  |  RB  | sm  |  XO  |Rc|
 
 Both instructions take two 64-bit sources, concatenate
 them together then extract 64 bits from it, the offset
-location determined by a third source.
+location determined by a third source.  So as to avoid
+costly 4-reg (VA-Form) a 2-bit mode `sm` gives four
+potential overwrite and zero-source options instead.
 
 # maddedu