anv/pipeline/gen7: Set the depth format in 3DSTATE_SF

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/intel/vulkan/gen7_pipeline.c b/src/intel/vulkan/gen7_pipeline.c
index df8fa289151001e2867226828548b8dba89d3372..1da28c03d54cccd818d8695f0e28fa1e1ab83835 100644 (file)
--- a/src/intel/vulkan/gen7_pipeline.c
+++ b/src/intel/vulkan/gen7_pipeline.c
@@ -67,7 +67,8 @@ genX(graphics_pipeline_create)(
    emit_vertex_input(pipeline, pCreateInfo->pVertexInputState, extra);
 
    assert(pCreateInfo->pRasterizationState);
-   emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra);
+   emit_rs_state(pipeline, pCreateInfo->pRasterizationState,
+                 pass, subpass, extra);
 
    emit_ds_state(pipeline, pCreateInfo->pDepthStencilState, pass, subpass);
 

diff --git a/src/intel/vulkan/gen8_pipeline.c b/src/intel/vulkan/gen8_pipeline.c
index e09d8cf628a2466d9de4867ccacefa6cef7a8d51..d16ce7b9690b5e18767ba2ce5bab3db1e2776533 100644 (file)
--- a/src/intel/vulkan/gen8_pipeline.c
+++ b/src/intel/vulkan/gen8_pipeline.c
@@ -119,7 +119,8 @@ genX(graphics_pipeline_create)(
    assert(pCreateInfo->pInputAssemblyState);
    emit_ia_state(pipeline, pCreateInfo->pInputAssemblyState, extra);
    assert(pCreateInfo->pRasterizationState);
-   emit_rs_state(pipeline, pCreateInfo->pRasterizationState, extra);
+   emit_rs_state(pipeline, pCreateInfo->pRasterizationState,
+                 pass, subpass, extra);
    emit_ms_state(pipeline, pCreateInfo->pMultisampleState);
    emit_ds_state(pipeline, pCreateInfo->pDepthStencilState, pass, subpass);
    emit_cb_state(pipeline, pCreateInfo->pColorBlendState,

diff --git a/src/intel/vulkan/genX_pipeline_util.h b/src/intel/vulkan/genX_pipeline_util.h
index 59941205529a6e9ff63c9aebced6f6537986adee..c17d9306dea0516d8bda3f8a58bd60299d953116 100644 (file)
--- a/src/intel/vulkan/genX_pipeline_util.h
+++ b/src/intel/vulkan/genX_pipeline_util.h
@@ -365,6 +365,8 @@ static const uint32_t vk_to_gen_front_face[] = {
 static void
 emit_rs_state(struct anv_pipeline *pipeline,
               const VkPipelineRasterizationStateCreateInfo *info,
+              const struct anv_render_pass *pass,
+              const struct anv_subpass *subpass,
               const struct anv_graphics_pipeline_create_info *extra)
 {
    struct GENX(3DSTATE_SF) sf = {
@@ -414,6 +416,25 @@ emit_rs_state(struct anv_pipeline *pipeline,
    raster.GlobalDepthOffsetEnableWireframe = info->depthBiasEnable;
    raster.GlobalDepthOffsetEnablePoint = info->depthBiasEnable;
 
+#if GEN_GEN == 7
+   /* Gen7 requires that we provide the depth format in 3DSTATE_SF so that it
+    * can get the depth offsets correct.
+    */
+   if (subpass->depth_stencil_attachment < pass->attachment_count) {
+      VkFormat vk_format =
+         pass->attachments[subpass->depth_stencil_attachment].format;
+      assert(vk_format_is_depth_or_stencil(vk_format));
+      if (vk_format_aspects(vk_format) & VK_IMAGE_ASPECT_DEPTH_BIT) {
+         enum isl_format isl_format =
+            anv_get_isl_format(&pipeline->device->info, vk_format,
+                               VK_IMAGE_ASPECT_DEPTH_BIT,
+                               VK_IMAGE_TILING_OPTIMAL);
+         sf.DepthBufferSurfaceFormat =
+            isl_format_get_depth_format(isl_format, false);
+      }
+   }
+#endif
+
 #if GEN_GEN >= 8
    GENX(3DSTATE_SF_pack)(NULL, pipeline->gen8.sf, &sf);
    GENX(3DSTATE_RASTER_pack)(NULL, pipeline->gen8.raster, &raster);