Pull in additional state setup from the DDX

diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index 7fd557ca8e2c97c5602dcb5c39ba1dd164b08515..8e7787eeef1eaa8429c5a34e2a1e99c7d6368352 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -57,6 +57,13 @@ GLboolean r700InitChipObject(context_t *context)
     r700->pStateList = (ContextState*) MALLOC (sizeof(ContextState)*sizeof(R700_CHIP_CONTEXT)/sizeof(unsigned int));
     pStateListWork = r700->pStateList;
 
+    // misc
+    LINK_STATES(TA_CNTL_AUX);
+    LINK_STATES(VC_ENHANCE);
+    LINK_STATES(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ);
+    LINK_STATES(DB_DEBUG);
+    LINK_STATES(DB_WATERMARKS);
+
     // DB
     LINK_STATES(DB_DEPTH_SIZE);
     LINK_STATES(DB_DEPTH_VIEW);
@@ -122,18 +129,26 @@ GLboolean r700InitChipObject(context_t *context)
     LINK_STATES(PA_CL_GB_HORZ_DISC_ADJ);
 
     // CB
+    LINK_STATES(CB_CLEAR_RED_R6XX);
+    LINK_STATES(CB_CLEAR_GREEN_R6XX);
+    LINK_STATES(CB_CLEAR_BLUE_R6XX);
+    LINK_STATES(CB_CLEAR_ALPHA_R6XX);
     LINK_STATES(CB_TARGET_MASK);
     LINK_STATES(CB_SHADER_MASK);
     LINK_STATES(CB_BLEND_RED);
     LINK_STATES(CB_BLEND_GREEN);
     LINK_STATES(CB_BLEND_BLUE);
     LINK_STATES(CB_BLEND_ALPHA);
+    LINK_STATES(CB_FOG_RED_R6XX);
+    LINK_STATES(CB_FOG_GREEN_R6XX);
+    LINK_STATES(CB_FOG_BLUE_R6XX);
     LINK_STATES(CB_SHADER_CONTROL);
     LINK_STATES(CB_COLOR_CONTROL);
     LINK_STATES(CB_CLRCMP_CONTROL);
     LINK_STATES(CB_CLRCMP_SRC);
     LINK_STATES(CB_CLRCMP_DST);
     LINK_STATES(CB_CLRCMP_MSK);
+    LINK_STATES(CB_BLEND_CONTROL);
 
     // SX
     LINK_STATES(SX_MISC);
@@ -145,6 +160,17 @@ GLboolean r700InitChipObject(context_t *context)
     LINK_STATES(VGT_INDX_OFFSET);
     LINK_STATES(VGT_MULTI_PRIM_IB_RESET_INDX);
     LINK_STATES(VGT_OUTPUT_PATH_CNTL);
+    LINK_STATES(VGT_HOS_CNTL);
+    LINK_STATES(VGT_HOS_MAX_TESS_LEVEL);
+    LINK_STATES(VGT_HOS_MIN_TESS_LEVEL);
+    LINK_STATES(VGT_HOS_REUSE_DEPTH);
+    LINK_STATES(VGT_GROUP_PRIM_TYPE);
+    LINK_STATES(VGT_GROUP_FIRST_DECR);
+    LINK_STATES(VGT_GROUP_DECR);
+    LINK_STATES(VGT_GROUP_VECT_0_CNTL);
+    LINK_STATES(VGT_GROUP_VECT_1_CNTL);
+    LINK_STATES(VGT_GROUP_VECT_0_FMT_CNTL);
+    LINK_STATES(VGT_GROUP_VECT_1_FMT_CNTL);
     LINK_STATES(VGT_GS_MODE);
     LINK_STATES(VGT_PRIMITIVEID_EN);
     LINK_STATES(VGT_DMA_NUM_INSTANCES);
@@ -153,6 +179,8 @@ GLboolean r700InitChipObject(context_t *context)
     LINK_STATES(VGT_INSTANCE_STEP_RATE_1);
     LINK_STATES(VGT_STRMOUT_EN);
     LINK_STATES(VGT_REUSE_OFF);
+    LINK_STATES(VGT_VTX_CNT_EN);
+    LINK_STATES(VGT_STRMOUT_BUFFER_EN);
 
     // SPI
     LINK_STATES(SPI_VS_OUT_ID_0);
@@ -172,6 +200,8 @@ GLboolean r700InitChipObject(context_t *context)
     LINK_STATES(SPI_INTERP_CONTROL_0);
     LINK_STATES(SPI_INPUT_Z);
     LINK_STATES(SPI_FOG_CNTL);
+    LINK_STATES(SPI_FOG_FUNC_SCALE);
+    LINK_STATES(SPI_FOG_FUNC_BIAS);
 
     // SQ
     LINK_STATES(SQ_ESGS_RING_ITEMSIZE);
@@ -570,3 +600,23 @@ GLboolean r700SendViewportState(context_t *context, int id)
 
        return GL_TRUE;
 }
+
+GLboolean r700SendSQConfig(context_t *context)
+{
+       R700_CHIP_CONTEXT *r700 = R700_CONTEXT_STATES(context);
+       BATCH_LOCALS(&context->radeon);
+
+        BEGIN_BATCH_NO_AUTOSTATE(8);
+       R600_OUT_BATCH_REGSEQ(SQ_CONFIG, 6);
+       R600_OUT_BATCH(r700->sq_config.SQ_CONFIG.u32All);
+       R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All);
+       R600_OUT_BATCH(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All);
+       R600_OUT_BATCH(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All);
+       R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All);
+       R600_OUT_BATCH(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All);
+        END_BATCH();
+       COMMIT_BATCH();
+
+       return GL_TRUE;
+}
+

diff --git a/src/mesa/drivers/dri/r600/r700_chip.h b/src/mesa/drivers/dri/r600/r700_chip.h
index 2129c0bdf493893497309ba4726bd365b80bcce1..f135b5e93960d3bbebbeac28605a3429795ea5b7 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_chip.h
+++ b/src/mesa/drivers/dri/r600/r700_chip.h
@@ -247,6 +247,16 @@ typedef struct _FS_STATE_STRUCT
        union UINT_FLOAT                SQ_PGM_CF_OFFSET_FS       ;  /* 0xA237 */
 } FS_STATE_STRUCT;
 
+typedef struct _SQ_CONFIG_STRUCT
+{
+       union UINT_FLOAT                SQ_CONFIG                 ;  /* 0x2300 */
+       union UINT_FLOAT                SQ_GPR_RESOURCE_MGMT_1    ;  /* 0x2301 */
+       union UINT_FLOAT                SQ_GPR_RESOURCE_MGMT_2    ;  /* 0x2302 */
+       union UINT_FLOAT                SQ_THREAD_RESOURCE_MGMT   ;  /* 0x2303 */
+       union UINT_FLOAT                SQ_STACK_RESOURCE_MGMT_1  ;  /* 0x2304 */
+       union UINT_FLOAT                SQ_STACK_RESOURCE_MGMT_2  ;  /* 0x2305 */
+} SQ_CONFIG_STRUCT;
+
 typedef struct ContextState
 {
     unsigned int * puiValue;
@@ -256,6 +266,13 @@ typedef struct ContextState
 
 typedef struct _R700_CHIP_CONTEXT
 {
+       // misc
+       union UINT_FLOAT                TA_CNTL_AUX               ;  /* 0x2542 */
+       union UINT_FLOAT                VC_ENHANCE                ;  /* 0x25C5 */
+       union UINT_FLOAT                SQ_DYN_GPR_CNTL_PS_FLUSH_REQ;  /* 0x2363 */
+       union UINT_FLOAT                DB_DEBUG                  ;  /* 0x260C */
+       union UINT_FLOAT                DB_WATERMARKS             ;  /* 0x260E */
+
        // DB
        union UINT_FLOAT                DB_DEPTH_SIZE             ;  /* 0xA000 */
        union UINT_FLOAT                DB_DEPTH_VIEW             ;  /* 0xA001 */
@@ -325,18 +342,26 @@ typedef struct _R700_CHIP_CONTEXT
        UCP_STATE_STRUCT                ucp[R700_MAX_UCP];
 
        // CB
+       union UINT_FLOAT                CB_CLEAR_RED_R6XX         ;  /* 0xA048 */
+       union UINT_FLOAT                CB_CLEAR_GREEN_R6XX       ;  /* 0xA049 */
+       union UINT_FLOAT                CB_CLEAR_BLUE_R6XX        ;  /* 0xA04A */
+       union UINT_FLOAT                CB_CLEAR_ALPHA_R6XX       ;  /* 0xA04B */
        union UINT_FLOAT                CB_TARGET_MASK            ;  /* 0xA08E */
        union UINT_FLOAT                CB_SHADER_MASK            ;  /* 0xA08F */
        union UINT_FLOAT                CB_BLEND_RED              ;  /* 0xA105 */
        union UINT_FLOAT                CB_BLEND_GREEN            ;  /* 0xA106 */
        union UINT_FLOAT                CB_BLEND_BLUE             ;  /* 0xA107 */
        union UINT_FLOAT                CB_BLEND_ALPHA            ;  /* 0xA108 */
+       union UINT_FLOAT                CB_FOG_RED_R6XX           ;  /* 0xA109 */
+       union UINT_FLOAT                CB_FOG_GREEN_R6XX         ;  /* 0xA10A */
+       union UINT_FLOAT                CB_FOG_BLUE_R6XX          ;  /* 0xA10B */
        union UINT_FLOAT                CB_SHADER_CONTROL         ;  /* 0xA1E8 */
        union UINT_FLOAT                CB_COLOR_CONTROL          ;  /* 0xA202 */
        union UINT_FLOAT                CB_CLRCMP_CONTROL         ;  /* 0xA30C */
        union UINT_FLOAT                CB_CLRCMP_SRC             ;  /* 0xA30D */
        union UINT_FLOAT                CB_CLRCMP_DST             ;  /* 0xA30E */
        union UINT_FLOAT                CB_CLRCMP_MSK             ;  /* 0xA30F */
+       union UINT_FLOAT                CB_BLEND_CONTROL          ;  /* 0xABD0 */
        RENDER_TARGET_STATE_STRUCT      render_target[R700_MAX_RENDER_TARGETS];
 
        // SX
@@ -349,6 +374,17 @@ typedef struct _R700_CHIP_CONTEXT
        union UINT_FLOAT                VGT_INDX_OFFSET           ;  /* 0xA102 */
        union UINT_FLOAT                VGT_MULTI_PRIM_IB_RESET_INDX;  /* 0xA103 */
        union UINT_FLOAT                VGT_OUTPUT_PATH_CNTL      ;  /* 0xA284 */
+       union UINT_FLOAT                VGT_HOS_CNTL              ;  /* 0xA285 */
+       union UINT_FLOAT                VGT_HOS_MAX_TESS_LEVEL    ;  /* 0xA286 */
+       union UINT_FLOAT                VGT_HOS_MIN_TESS_LEVEL    ;  /* 0xA287 */
+       union UINT_FLOAT                VGT_HOS_REUSE_DEPTH       ;  /* 0xA288 */
+       union UINT_FLOAT                VGT_GROUP_PRIM_TYPE       ;  /* 0xA289 */
+       union UINT_FLOAT                VGT_GROUP_FIRST_DECR      ;  /* 0xA28A */
+       union UINT_FLOAT                VGT_GROUP_DECR            ;  /* 0xA28B */
+       union UINT_FLOAT                VGT_GROUP_VECT_0_CNTL     ;  /* 0xA28C */
+       union UINT_FLOAT                VGT_GROUP_VECT_1_CNTL     ;  /* 0xA28D */
+       union UINT_FLOAT                VGT_GROUP_VECT_0_FMT_CNTL ;  /* 0xA28E */
+       union UINT_FLOAT                VGT_GROUP_VECT_1_FMT_CNTL ;  /* 0xA28F */
        union UINT_FLOAT                VGT_GS_MODE               ;  /* 0xA290 */
        union UINT_FLOAT                VGT_PRIMITIVEID_EN        ;  /* 0xA2A1 */
        union UINT_FLOAT                VGT_DMA_NUM_INSTANCES     ;  /* 0xA2A2 */
@@ -357,6 +393,8 @@ typedef struct _R700_CHIP_CONTEXT
        union UINT_FLOAT                VGT_INSTANCE_STEP_RATE_1  ;  /* 0xA2A9 */
        union UINT_FLOAT                VGT_STRMOUT_EN            ;  /* 0xA2AC */
        union UINT_FLOAT                VGT_REUSE_OFF             ;  /* 0xA2AD */
+       union UINT_FLOAT                VGT_VTX_CNT_EN            ;  /* 0xA2AE */
+       union UINT_FLOAT                VGT_STRMOUT_BUFFER_EN     ;  /* 0xA2C8 */
 
        // SPI
        union UINT_FLOAT                SPI_VS_OUT_ID_0           ;  /* 0xA185 */
@@ -376,6 +414,8 @@ typedef struct _R700_CHIP_CONTEXT
        union UINT_FLOAT                SPI_INTERP_CONTROL_0      ;  /* 0xA1B5 */
        union UINT_FLOAT                SPI_INPUT_Z               ;  /* 0xA1B6 */
        union UINT_FLOAT                SPI_FOG_CNTL              ;  /* 0xA1B7 */
+       union UINT_FLOAT                SPI_FOG_FUNC_SCALE        ;  /* 0xA1B8 */
+       union UINT_FLOAT                SPI_FOG_FUNC_BIAS         ;  /* 0xA1B9 */
        union UINT_FLOAT                SQ_VTX_SEMANTIC[R700_MAX_SHADER_EXPORTS];
        union UINT_FLOAT                SPI_PS_INPUT_CNTL[R700_MAX_SHADER_EXPORTS];
 
@@ -386,6 +426,9 @@ typedef struct _R700_CHIP_CONTEXT
        ES_STATE_STRUCT                 es;
        PS_STATE_STRUCT                 fs;
 
+       // SQ CONFIG
+       SQ_CONFIG_STRUCT                sq_config;
+
        // SQ
        union UINT_FLOAT                SQ_ESGS_RING_ITEMSIZE     ;  /* 0xA22A */
        union UINT_FLOAT                SQ_GSVS_RING_ITEMSIZE     ;  /* 0xA22B */

diff --git a/src/mesa/drivers/dri/r600/r700_chipoffset.h b/src/mesa/drivers/dri/r600/r700_chipoffset.h
index 9050b9a71554439724d609cbe3bf9682c163b12c..4d73fb99a7def171f2d395000aff64d45def1638 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_chipoffset.h
+++ b/src/mesa/drivers/dri/r600/r700_chipoffset.h
@@ -51,6 +51,12 @@
 #define mmCP_COHER_BASE                                 0x217E
 #define mmCP_COHER_STATUS                               0x217F
 
+#define mmTA_CNTL_AUX                                   0x2542
+#define mmVC_ENHANCE                                    0x25C5
+#define mmSQ_DYN_GPR_CNTL_PS_FLUSH_REQ                  0x2363
+#define mmDB_DEBUG                                      0x260C
+#define mmDB_WATERMARKS                                 0x260E
+
 #define mmPA_CL_VPORT_XSCALE                            0xA10F
 #define mmPA_CL_VPORT_XOFFSET                           0xA110
 #define mmPA_CL_VPORT_YSCALE                            0xA111
@@ -568,7 +574,6 @@
 #define mmSPI_FOG_FUNC_BIAS                             0xA1B9
 
 #define mmSX_MISC                                       0xA0D4
-
 #define mmSX_ALPHA_TEST_CONTROL                         0xA104
 #define mmSX_ALPHA_REF                                  0xA10E
 
@@ -592,6 +597,10 @@
 #define mmDB_DEPTH_CONTROL                              0xA200
 #define mmDB_ALPHA_TO_MASK                              0xA351
 
+#define mmCB_CLEAR_RED_R6XX                             0xA048
+#define mmCB_CLEAR_GREEN_R6XX                           0xA049
+#define mmCB_CLEAR_BLUE_R6XX                            0xA04A
+#define mmCB_CLEAR_ALPHA_R6XX                           0xA04B
 #define mmCB_BLEND_RED                                  0xA105
 #define mmCB_BLEND_GREEN                                0xA106
 #define mmCB_BLEND_BLUE                                 0xA107

diff --git a/src/mesa/drivers/dri/r600/r700_render.c b/src/mesa/drivers/dri/r600/r700_render.c
index 2c6700621758a911cc728ed17dc4c7fca25ade5b..4693cfbd8278d54c03fa64d2c557dcd7f7497905 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_render.c
+++ b/src/mesa/drivers/dri/r600/r700_render.c
@@ -256,6 +256,8 @@ static GLboolean r700RunRender(GLcontext * ctx,
 
     r700SyncSurf(context); /* TODO : make it light. */
 
+    r700SendSQConfig(context);
+
     r700UpdateShaders(ctx);
 
     r700SetScissor(context);

diff --git a/src/mesa/drivers/dri/r600/r700_state.c b/src/mesa/drivers/dri/r600/r700_state.c
index 17e99bf5e101dad34f62b43f479eec86184f731d..cf1383d5ebefed0ddefa208179b6dd7160287177 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_state.c
+++ b/src/mesa/drivers/dri/r600/r700_state.c
@@ -630,9 +630,6 @@ void r700SetScissor(context_t *context) //---------------
                y2 = rrb->height - 1;
        }
 
-       /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
-       r700->PA_SC_CLIPRECT_RULE.u32All = 0x0000FFFF;
-
        /* window */
        SETbit(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, WINDOW_OFFSET_DISABLE_bit);
        SETfield(r700->PA_SC_WINDOW_SCISSOR_TL.u32All, x1,
@@ -756,10 +753,18 @@ void r700SetDepthTarget(context_t *context)
     r700->DB_DEPTH_VIEW.u32All      = 0;
     r700->DB_RENDER_CONTROL.u32All  = 0;
     r700->DB_RENDER_OVERRIDE.u32All = 0;
+    if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
+           SETbit(r700->DB_RENDER_OVERRIDE.u32All, FORCE_SHADER_Z_ORDER_bit);
     SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIZ_ENABLE_shift, FORCE_HIZ_ENABLE_mask);
     SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE0_shift, FORCE_HIS_ENABLE0_mask);
     SETfield(r700->DB_RENDER_OVERRIDE.u32All, FORCE_DISABLE, FORCE_HIS_ENABLE1_shift, FORCE_HIS_ENABLE1_mask);
 
+    r700->DB_ALPHA_TO_MASK.u32All = 0;
+    SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET0_shift, ALPHA_TO_MASK_OFFSET0_mask);
+    SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET1_shift, ALPHA_TO_MASK_OFFSET1_mask);
+    SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET2_shift, ALPHA_TO_MASK_OFFSET2_mask);
+    SETfield(r700->DB_ALPHA_TO_MASK.u32All, 2, ALPHA_TO_MASK_OFFSET3_shift, ALPHA_TO_MASK_OFFSET3_mask);
+
     rrb = radeon_get_depthbuffer(&context->radeon);
        if (!rrb)
                return;
@@ -796,6 +801,195 @@ void r700SetDepthTarget(context_t *context)
     /* r700->DB_PREFETCH_LIMIT.bits.DEPTH_HEIGHT_TILE_MAX = (context->currentDraw->h >> 3) - 1; */ /* z buffer sie may much bigger than what need, so use actual used h. */
 }
 
+static void r700InitSQConfig(GLcontext * ctx)
+{
+    context_t *context = R700_CONTEXT(ctx);
+    R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
+    int ps_prio;
+    int vs_prio;
+    int gs_prio;
+    int es_prio;
+    int num_ps_gprs;
+    int num_vs_gprs;
+    int num_gs_gprs;
+    int num_es_gprs;
+    int num_temp_gprs;
+    int num_ps_threads;
+    int num_vs_threads;
+    int num_gs_threads;
+    int num_es_threads;
+    int num_ps_stack_entries;
+    int num_vs_stack_entries;
+    int num_gs_stack_entries;
+    int num_es_stack_entries;
+
+    // SQ
+    ps_prio = 0;
+    vs_prio = 1;
+    gs_prio = 2;
+    es_prio = 3;
+    switch (context->radeon.radeonScreen->chip_family) {
+    case CHIP_FAMILY_R600:
+           num_ps_gprs = 192;
+           num_vs_gprs = 56;
+           num_temp_gprs = 4;
+           num_gs_gprs = 0;
+           num_es_gprs = 0;
+           num_ps_threads = 136;
+           num_vs_threads = 48;
+           num_gs_threads = 4;
+           num_es_threads = 4;
+           num_ps_stack_entries = 128;
+           num_vs_stack_entries = 128;
+           num_gs_stack_entries = 0;
+           num_es_stack_entries = 0;
+           break;
+    case CHIP_FAMILY_RV630:
+    case CHIP_FAMILY_RV635:
+           num_ps_gprs = 84;
+           num_vs_gprs = 36;
+           num_temp_gprs = 4;
+           num_gs_gprs = 0;
+           num_es_gprs = 0;
+           num_ps_threads = 144;
+           num_vs_threads = 40;
+           num_gs_threads = 4;
+           num_es_threads = 4;
+           num_ps_stack_entries = 40;
+           num_vs_stack_entries = 40;
+           num_gs_stack_entries = 32;
+           num_es_stack_entries = 16;
+           break;
+    case CHIP_FAMILY_RV610:
+    case CHIP_FAMILY_RV620:
+    case CHIP_FAMILY_RS780:
+    default:
+           num_ps_gprs = 84;
+           num_vs_gprs = 36;
+           num_temp_gprs = 4;
+           num_gs_gprs = 0;
+           num_es_gprs = 0;
+           num_ps_threads = 136;
+           num_vs_threads = 48;
+           num_gs_threads = 4;
+           num_es_threads = 4;
+           num_ps_stack_entries = 40;
+           num_vs_stack_entries = 40;
+           num_gs_stack_entries = 32;
+           num_es_stack_entries = 16;
+           break;
+    case CHIP_FAMILY_RV670:
+           num_ps_gprs = 144;
+           num_vs_gprs = 40;
+           num_temp_gprs = 4;
+           num_gs_gprs = 0;
+           num_es_gprs = 0;
+           num_ps_threads = 136;
+           num_vs_threads = 48;
+           num_gs_threads = 4;
+           num_es_threads = 4;
+           num_ps_stack_entries = 40;
+           num_vs_stack_entries = 40;
+           num_gs_stack_entries = 32;
+           num_es_stack_entries = 16;
+           break;
+    case CHIP_FAMILY_RV770:
+           num_ps_gprs = 192;
+           num_vs_gprs = 56;
+           num_temp_gprs = 4;
+           num_gs_gprs = 0;
+           num_es_gprs = 0;
+           num_ps_threads = 188;
+           num_vs_threads = 60;
+           num_gs_threads = 0;
+           num_es_threads = 0;
+           num_ps_stack_entries = 256;
+           num_vs_stack_entries = 256;
+           num_gs_stack_entries = 0;
+           num_es_stack_entries = 0;
+           break;
+    case CHIP_FAMILY_RV730:
+           //case CHIP_FAMILY_RV740:
+           num_ps_gprs = 84;
+           num_vs_gprs = 36;
+           num_temp_gprs = 4;
+           num_gs_gprs = 0;
+           num_es_gprs = 0;
+           num_ps_threads = 188;
+           num_vs_threads = 60;
+           num_gs_threads = 0;
+           num_es_threads = 0;
+           num_ps_stack_entries = 128;
+           num_vs_stack_entries = 128;
+           num_gs_stack_entries = 0;
+           num_es_stack_entries = 0;
+           break;
+    case CHIP_FAMILY_RV710:
+           num_ps_gprs = 192;
+           num_vs_gprs = 56;
+           num_temp_gprs = 4;
+           num_gs_gprs = 0;
+           num_es_gprs = 0;
+           num_ps_threads = 144;
+           num_vs_threads = 48;
+           num_gs_threads = 0;
+           num_es_threads = 0;
+           num_ps_stack_entries = 128;
+           num_vs_stack_entries = 128;
+           num_gs_stack_entries = 0;
+           num_es_stack_entries = 0;
+           break;
+    }
+
+    r700->sq_config.SQ_CONFIG.u32All = 0;
+    if ((context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV610) ||
+        (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV620) ||
+       (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RS780) ||
+        (context->radeon.radeonScreen->chip_family == CHIP_FAMILY_RV710))
+           CLEARbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
+    else
+           SETbit(r700->sq_config.SQ_CONFIG.u32All, VC_ENABLE_bit);
+    SETbit(r700->sq_config.SQ_CONFIG.u32All, DX9_CONSTS_bit);
+    SETbit(r700->sq_config.SQ_CONFIG.u32All, ALU_INST_PREFER_VECTOR_bit);
+    SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, PS_PRIO_shift, PS_PRIO_mask);
+    SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, VS_PRIO_shift, VS_PRIO_mask);
+    SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, GS_PRIO_shift, GS_PRIO_mask);
+    SETfield(r700->sq_config.SQ_CONFIG.u32All, ps_prio, ES_PRIO_shift, ES_PRIO_mask);
+
+    r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All = 0;
+    SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_ps_gprs, NUM_PS_GPRS_shift, NUM_PS_GPRS_mask);
+    SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_vs_gprs, NUM_VS_GPRS_shift, NUM_VS_GPRS_mask);
+    SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_1.u32All, num_temp_gprs,
+            NUM_CLAUSE_TEMP_GPRS_shift, NUM_CLAUSE_TEMP_GPRS_mask);
+
+    r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All = 0;
+    SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_gs_gprs, NUM_GS_GPRS_shift, NUM_GS_GPRS_mask);
+    SETfield(r700->sq_config.SQ_GPR_RESOURCE_MGMT_2.u32All, num_es_gprs, NUM_ES_GPRS_shift, NUM_ES_GPRS_mask);
+
+    r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All = 0;
+    SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_ps_threads,
+            NUM_PS_THREADS_shift, NUM_PS_THREADS_mask);
+    SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_vs_threads,
+            NUM_VS_THREADS_shift, NUM_VS_THREADS_mask);
+    SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_gs_threads,
+            NUM_GS_THREADS_shift, NUM_GS_THREADS_mask);
+    SETfield(r700->sq_config.SQ_THREAD_RESOURCE_MGMT.u32All, num_es_threads,
+            NUM_ES_THREADS_shift, NUM_ES_THREADS_mask);
+
+    r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All = 0;
+    SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_ps_stack_entries,
+            NUM_PS_STACK_ENTRIES_shift, NUM_PS_STACK_ENTRIES_mask);
+    SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_1.u32All, num_vs_stack_entries,
+            NUM_VS_STACK_ENTRIES_shift, NUM_VS_STACK_ENTRIES_mask);
+
+    r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All = 0;
+    SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_gs_stack_entries,
+            NUM_GS_STACK_ENTRIES_shift, NUM_GS_STACK_ENTRIES_mask);
+    SETfield(r700->sq_config.SQ_STACK_RESOURCE_MGMT_2.u32All, num_es_stack_entries,
+            NUM_ES_STACK_ENTRIES_shift, NUM_ES_STACK_ENTRIES_mask);
+
+}
+
 /**
  * Calculate initial hardware state and register state functions.
  * Assumes that the command buffer and state atoms have been
@@ -807,6 +1001,25 @@ void r700InitState(GLcontext * ctx) //-------------------
 
     R700_CHIP_CONTEXT *r700 = (R700_CHIP_CONTEXT*)(&context->hw);
 
+    r700->TA_CNTL_AUX.u32All = 0;
+    SETfield(r700->TA_CNTL_AUX.u32All, 28, TD_FIFO_CREDIT_shift, TD_FIFO_CREDIT_mask);
+    r700->VC_ENHANCE.u32All = 0;
+    r700->DB_WATERMARKS.u32All = 0;
+    SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_FREE_shift, DEPTH_FREE_mask);
+    SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_FLUSH_shift, DEPTH_FLUSH_mask);
+    SETfield(r700->DB_WATERMARKS.u32All, 0, FORCE_SUMMARIZE_shift, FORCE_SUMMARIZE_mask);
+    SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_PENDING_FREE_shift, DEPTH_PENDING_FREE_mask);
+    r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All = 0;
+    if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
+           SETfield(r700->TA_CNTL_AUX.u32All, 3, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
+           r700->DB_DEBUG.u32All = 0x82000000;
+           SETfield(r700->DB_WATERMARKS.u32All, 16, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
+    } else {
+           SETfield(r700->TA_CNTL_AUX.u32All, 2, GRADIENT_CREDIT_shift, GRADIENT_CREDIT_mask);
+           SETfield(r700->DB_WATERMARKS.u32All, 4, DEPTH_CACHELINE_FREE_shift, DEPTH_CACHELINE_FREE_mask);
+           SETbit(r700->SQ_DYN_GPR_CNTL_PS_FLUSH_REQ.u32All, VS_PC_LIMIT_ENABLE_bit);
+    }
+
     /* Turn off vgt reuse */
     r700->VGT_REUSE_OFF.u32All = 0;
     SETbit(r700->VGT_REUSE_OFF.u32All, REUSE_OFF_bit);
@@ -823,7 +1036,7 @@ void r700InitState(GLcontext * ctx) //-------------------
     CLEARfield(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_FUNC_mask);
     CLEARbit(r700->SX_ALPHA_TEST_CONTROL.u32All, ALPHA_TEST_ENABLE_bit);
 
-    /* defualt shader connections. */
+    /* default shader connections. */
     r700->SPI_VS_OUT_ID_0.u32All  = 0x03020100;
     r700->SPI_VS_OUT_ID_1.u32All  = 0x07060504;
 
@@ -831,6 +1044,10 @@ void r700InitState(GLcontext * ctx) //-------------------
     r700->SPI_PS_INPUT_CNTL[1].u32All  = 0x00000801;
     r700->SPI_PS_INPUT_CNTL[2].u32All  = 0x00000802;
 
+    r700->SPI_THREAD_GROUPING.u32All = 0;
+    if (context->radeon.radeonScreen->chip_family >= CHIP_FAMILY_RV770)
+           SETfield(r700->SPI_THREAD_GROUPING.u32All, 1, PS_GROUPING_shift, PS_GROUPING_mask);
+
     SETfield(r700->CB_COLOR_CONTROL.u32All, 0xCC, ROP3_shift, ROP3_mask);
     CLEARbit(r700->CB_COLOR_CONTROL.u32All, PER_MRT_BLEND_bit);
 
@@ -853,6 +1070,25 @@ void r700InitState(GLcontext * ctx) //-------------------
             ((RADEONDRIPtr)(context->radeon.radeonScreen->driScreen->pDevPriv))->height,
             PA_SC_SCREEN_SCISSOR_BR__BR_Y_shift, PA_SC_SCREEN_SCISSOR_BR__BR_Y_mask);
 
+    /* 4 clip rectangles */ /* TODO : set these clip rects according to context->currentDraw->numClipRects */
+    r700->PA_SC_CLIPRECT_RULE.u32All = 0;
+    SETfield(r700->PA_SC_CLIPRECT_RULE.u32All, CLIP_RULE_mask, CLIP_RULE_shift, CLIP_RULE_mask);
+
+    if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770)
+           r700->PA_SC_EDGERULE.u32All = 0;
+    else
+           r700->PA_SC_EDGERULE.u32All = 0xAAAAAAAA;
+
+    if (context->radeon.radeonScreen->chip_family < CHIP_FAMILY_RV770) {
+           r700->PA_SC_MODE_CNTL.u32All = 0;
+           SETbit(r700->PA_SC_MODE_CNTL.u32All, WALK_ORDER_ENABLE_bit);
+           SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
+    } else {
+           r700->PA_SC_MODE_CNTL.u32All = 0x00500000;
+           SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_REZ_ENABLE_bit);
+           SETbit(r700->PA_SC_MODE_CNTL.u32All, FORCE_EOV_CNTDWN_ENABLE_bit);
+    }
+
     /* Do scale XY and Z by 1/W0. */
     r700->bEnablePerspective = GL_TRUE;
     CLEARbit(r700->PA_CL_VTE_CNTL.u32All, VTX_XY_FMT_bit);
@@ -878,6 +1114,10 @@ void r700InitState(GLcontext * ctx) //-------------------
     /* Set up line control */
     SETfield(r700->PA_SU_LINE_CNTL.u32All, 0x8,
              PA_SU_LINE_CNTL__WIDTH_shift, PA_SU_LINE_CNTL__WIDTH_mask);
+    SETfield(r700->PA_SU_LINE_CNTL.u32All, 0x2,
+             PA_SU_VTX_CNTL__ROUND_MODE_shift, PA_SU_VTX_CNTL__ROUND_MODE_mask);
+    SETfield(r700->PA_SU_LINE_CNTL.u32All, 0x5,
+             QUANT_MODE_shift, QUANT_MODE_mask);
 
     r700->PA_SC_LINE_CNTL.u32All = 0;
     CLEARbit(r700->PA_SC_LINE_CNTL.u32All, EXPAND_LINE_WIDTH_bit);
@@ -896,6 +1136,22 @@ void r700InitState(GLcontext * ctx) //-------------------
     r700->PA_CL_GB_HORZ_CLIP_ADJ.u32All  = 0x3F800000;
     r700->PA_CL_GB_HORZ_DISC_ADJ.u32All  = 0x3F800000;
 
+    /* CB */
+    r700->CB_CLEAR_RED_R6XX.f32All = 1.0; //r6xx only
+    r700->CB_CLEAR_GREEN_R6XX.f32All = 0.0; //r6xx only
+    r700->CB_CLEAR_BLUE_R6XX.f32All = 1.0; //r6xx only
+    r700->CB_CLEAR_ALPHA_R6XX.f32All = 1.0; //r6xx only
+    r700->CB_FOG_RED_R6XX.u32All = 0; //r6xx only
+    r700->CB_FOG_GREEN_R6XX.u32All = 0; //r6xx only
+    r700->CB_FOG_BLUE_R6XX.u32All = 0; //r6xx only
+
+    r700->CB_BLEND_RED.u32All = 0;
+    r700->CB_BLEND_GREEN.u32All = 0;
+    r700->CB_BLEND_BLUE.u32All = 0;
+    r700->CB_BLEND_ALPHA.u32All = 0;
+
+    r700->CB_BLEND_CONTROL.u32All = 0;
+
     /* Disable color compares */
     SETfield(r700->CB_CLRCMP_CONTROL.u32All, CLRCMP_DRAW_ALWAYS,
              CLRCMP_FCN_SRC_shift, CLRCMP_FCN_SRC_mask);
@@ -923,6 +1179,7 @@ void r700InitState(GLcontext * ctx) //-------------------
 
     r700->SX_MISC.u32All = 0;
 
+    r700InitSQConfig(ctx);
 }
 
 void r700InitStateFuncs(struct dd_function_table *functions) //-----------------