Instruction *insn = val->getUniqueInsn();
if (!insn)
- return;
+ insn = bb->getFirst();
+
assert(bb->getFirst()->serial <= bb->getExit()->serial);
assert(bb->getExit()->serial + 1 >= end);
bool
RegAlloc::buildLiveSets(BasicBlock *bb)
{
+ Function *f = bb->getFunction();
BasicBlock *bn;
Instruction *i;
unsigned int s, d;
// if (!bb->getEntry())
// return true;
+ if (bb == BasicBlock::get(f->cfgExit)) {
+ for (std::deque<ValueRef>::iterator it = f->outs.begin();
+ it != f->outs.end(); ++it) {
+ assert(it->get()->asLValue());
+ bb->liveSet.set(it->get()->id);
+ }
+ }
+
for (i = bb->getExit(); i && i != bb->getEntry()->prev; i = i->prev) {
for (d = 0; i->defExists(d); ++d)
bb->liveSet.clr(i->getDef(d)->id);
{
BasicBlock *bbA = NULL, *bbB = NULL;
- assert(bb->cfg.incidentCount() || bb->liveSet.popCount() == 0);
-
if (bb->cfg.outgoingCount()) {
// trickery to save a loop of OR'ing liveSets
// aliasing works fine with BitSet::setOr
}
}
+ if (bb == BasicBlock::get(func->cfg.getRoot())) {
+ for (std::deque<ValueDef>::iterator it = func->ins.begin();
+ it != func->ins.end(); ++it) {
+ if (it->get()->reg.data.id >= 0) // add hazard for fixed regs
+ it->get()->livei.extend(0, 1);
+ }
+ }
+
return true;
}
void
Function::buildLiveSetsPreSSA(BasicBlock *bb, const int seq)
{
+ Function *f = bb->getFunction();
BitSet usedBeforeAssigned(allLValues.getSize(), true);
BitSet assigned(allLValues.getSize(), true);
assigned.set(i->getDef(d)->id);
}
+ if (bb == BasicBlock::get(f->cfgExit)) {
+ for (std::deque<ValueRef>::iterator it = f->outs.begin();
+ it != f->outs.end(); ++it) {
+ if (!assigned.test(it->get()->id))
+ usedBeforeAssigned.set(it->get()->id);
+ }
+ }
+
bb->liveSet.andNot(assigned);
bb->liveSet |= usedBeforeAssigned;
}