for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
const VkVertexInputAttributeDescription *desc =
&info->pVertexAttributeDescriptions[i];
- const struct anv_format *format = anv_format_for_vk_format(desc->format);
+ enum isl_format format = anv_get_isl_format(desc->format,
+ VK_IMAGE_ASPECT_COLOR_BIT);
assert(desc->binding < 32);
struct GEN7_VERTEX_ELEMENT_STATE element = {
.VertexBufferIndex = desc->binding,
.Valid = true,
- .SourceElementFormat = format->surface_format,
+ .SourceElementFormat = format,
.EdgeFlagEnable = false,
.SourceElementOffset = desc->offset,
- .Component0Control = VFCOMP_STORE_SRC,
- .Component1Control = format->num_channels >= 2 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
- .Component2Control = format->num_channels >= 3 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
- .Component3Control = format->num_channels >= 4 ? VFCOMP_STORE_SRC : VFCOMP_STORE_1_FP
+ .Component0Control = vertex_element_comp_control(format, 0),
+ .Component1Control = vertex_element_comp_control(format, 1),
+ .Component2Control = vertex_element_comp_control(format, 2),
+ .Component3Control = vertex_element_comp_control(format, 3),
};
GEN7_VERTEX_ELEMENT_STATE_pack(NULL, &p[1 + slot * 2], &element);
}
for (uint32_t i = 0; i < info->vertexAttributeDescriptionCount; i++) {
const VkVertexInputAttributeDescription *desc =
&info->pVertexAttributeDescriptions[i];
- const struct anv_format *format = anv_format_for_vk_format(desc->format);
+ enum isl_format format = anv_get_isl_format(desc->format,
+ VK_IMAGE_ASPECT_COLOR_BIT);
assert(desc->binding < 32);
struct GENX(VERTEX_ELEMENT_STATE) element = {
.VertexBufferIndex = desc->binding,
.Valid = true,
- .SourceElementFormat = format->surface_format,
+ .SourceElementFormat = format,
.EdgeFlagEnable = false,
.SourceElementOffset = desc->offset,
- .Component0Control = VFCOMP_STORE_SRC,
- .Component1Control = format->num_channels >= 2 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
- .Component2Control = format->num_channels >= 3 ? VFCOMP_STORE_SRC : VFCOMP_STORE_0,
- .Component3Control = format->num_channels >= 4 ? VFCOMP_STORE_SRC : VFCOMP_STORE_1_FP
+ .Component0Control = vertex_element_comp_control(format, 0),
+ .Component1Control = vertex_element_comp_control(format, 1),
+ .Component2Control = vertex_element_comp_control(format, 2),
+ .Component3Control = vertex_element_comp_control(format, 3),
};
GENX(VERTEX_ELEMENT_STATE_pack)(NULL, &p[1 + slot * 2], &element);
* IN THE SOFTWARE.
*/
+static uint32_t
+vertex_element_comp_control(enum isl_format format, unsigned comp)
+{
+ uint8_t bits;
+ switch (comp) {
+ case 0: bits = isl_format_layouts[format].channels.r.bits; break;
+ case 1: bits = isl_format_layouts[format].channels.g.bits; break;
+ case 2: bits = isl_format_layouts[format].channels.b.bits; break;
+ case 3: bits = isl_format_layouts[format].channels.a.bits; break;
+ default: unreachable("Invalid component");
+ }
+
+ if (bits) {
+ return VFCOMP_STORE_SRC;
+ } else if (comp < 3) {
+ return VFCOMP_STORE_0;
+ } else if (isl_format_layouts[format].channels.r.type == ISL_UINT ||
+ isl_format_layouts[format].channels.r.type == ISL_SINT) {
+ assert(comp == 3);
+ return VFCOMP_STORE_1_INT;
+ } else {
+ assert(comp == 3);
+ return VFCOMP_STORE_1_FP;
+ }
+}
+
static const uint32_t vk_to_gen_cullmode[] = {
[VK_CULL_MODE_NONE] = CULLMODE_NONE,
[VK_CULL_MODE_FRONT_BIT] = CULLMODE_FRONT,